CN107765167B

CN107765167B - TSV test circuit and method based on switch capacitor

Info

Publication number: CN107765167B
Application number: CN201710962060.5A
Authority: CN
Inventors: 俞洋; 方旭; 彭喜元; 徐康康
Original assignee: Harbin Institute of Technology
Current assignee: Harbin Institute of Technology
Priority date: 2017-10-16
Filing date: 2017-10-16
Publication date: 2020-06-09
Anticipated expiration: 2037-10-16
Also published as: CN107765167A

Abstract

The invention discloses a TSV test circuit and a TSV test method based on a switched capacitor, and relates to the field of semiconductors. The equivalent resistance unit of the TSV test circuit based on the switched capacitor comprises a plurality of equivalent resistance modules, each equivalent resistance module corresponds to a to-be-tested through silicon via, a test port of each equivalent resistance module is connected with a test end of the corresponding to-be-tested through silicon via, and charging ports of all equivalent resistance modules are connected together to form a charging end of the equivalent resistance unit; the electric quantity output end of the common test unit is connected with the charging end of the equivalent resistance unit, the common test unit is used for controlling the charging and discharging state of the through silicon via to be tested according to a third control signal of the third control input end, a first control signal of the first control input end and a second control signal of the second control input end so as to carry out testing, and the test result of the through silicon via to be tested is output through the test output end.

Description

TSV test circuit and method based on switch capacitor

Technical Field

The invention belongs to the field of semiconductors, and particularly relates to a Through-silicon via (TSV) test circuit and a TSV test method based on a switched capacitor.

Background

Moore's law is increasingly challenged by the development of the semiconductor industry, where interconnect line delays have far exceeded gate delays, leading to a range of timing, power consumption, coupling, and crosstalk issues. In order to meet the development and innovation requirements of integrated circuits, a Three-dimensional integrated circuit (3D IC) based on TSVs vertically interconnects multiple layers of silicon chips through TSV structures, so that the defects of a two-dimensional integrated circuit are effectively overcome, and a smaller volume is used to accommodate more abundant functions, which becomes the development trend of the next generation of integrated circuits.

In three-dimensional integrated circuit technology, the TSV as a vertical interconnection between multiple layers of chips has a significant impact on the signal integrity of the whole chip. Because the technology of the TSV in the three-dimensional non-memory logic integration is not completely mature, the defect generated in the TSV forming or wafer binding process directly causes the low yield of the three-dimensional integrated chip. According to related reports, the failure rate of TSV before wafer bonding is 0.005% to 5%; in the vertical binding of the wafer, due to the technical processes of thinning, oxidation and the like, the finished product rate of the TSV is further reduced, the factors seriously affect the yield of the three-dimensional integrated circuit chip and hinder the marketization of the three-dimensional integrated circuit. Therefore, how to ensure the effectiveness and reliability of the TSVs in the chip to be bonded is one of the problems that must be solved to realize large-scale application of the three-dimensional integrated circuit. The most direct solution to this problem is to effectively test the TSVs before the three-dimensional integrated circuits are bound.

Disclosure of Invention

The invention aims to solve the problem of effectively testing TSV before the three-dimensional integrated circuit is bound, and provides a TSV testing circuit and a TSV testing method based on a switch capacitor, wherein the TSV testing circuit and the TSV testing method are used for effectively testing the TSV before the three-dimensional integrated circuit is bound.

A TSV test circuit based on switched capacitors comprises:

the equivalent resistance unit comprises a plurality of equivalent resistance modules, each equivalent resistance module corresponds to a to-be-tested through silicon via and comprises a first control input end, a second control input end, a test port, a charging port and a grounding end, the test port is connected with the corresponding test end of the to-be-tested through silicon via, and the charging ports of all the equivalent resistance modules are connected together to form a charging end of the equivalent resistance unit;

the public test unit comprises a third control input end, a test output end, a clock port, a power supply end and an electric quantity output end, wherein the electric quantity output end is connected with a charging end of the equivalent resistance unit, the public test unit is used for controlling the charging and discharging state of the through silicon via to be tested according to a third control signal of the third control input end, a first control signal of the first control input end and a second control signal of the second control input end so as to test, and the test output end outputs a test result of the through silicon via to be tested.

Preferably, the equivalent resistance module includes:

the first transmission gate switch is connected between the charging port and the testing end of the through silicon via to be tested in series, and the first control input end is formed at the control end of the first transmission gate switch;

the second transmission gate switch is connected between the test end of the through silicon via to be tested and the grounding end in series, and the second control input end is formed at the control end of the second transmission gate switch;

and the test end of the through silicon via to be tested is connected between the first transmission gate switch and the second transmission gate switch.

Preferably, the common test unit includes:

the three-input AND gate comprises a first input end, a second input end, a third input end and an output end, wherein the output end of the three-input AND gate forms the test output end, and the first input end forms the clock port;

a third pass gate switch, one end of which forms the power supply terminal;

one end of the standard capacitor is grounded, and the other end of the standard capacitor is connected with the other end of the third transmission gate switch;

the input end of the inverter and the control end of the third transmission gate switch jointly form the third control input end, and the output end of the inverter is connected with the second input end of the three-input AND gate;

and the input end of the driver is simultaneously connected with the other end of the standard capacitor and the other end of the third transmission gate switch to form an electric quantity output end of the common test unit.

The invention also provides a testing method of the TSV testing circuit based on the switched capacitor, which is used for testing a plurality of through silicon vias to be tested one by one, and respectively connecting each through silicon via to be tested to a corresponding equivalent resistance module, and the method for testing each through silicon via to be tested comprises the following steps:

s1, in an initialization stage, inputting a preset clock signal into a public test unit through a clock port, inputting a third control signal into the public test unit through a third control input end, controlling a third transmission door switch to be closed through the third control signal, enabling a standard capacitor in the public test unit to be charged to a preset voltage within a preset time, inputting a first control signal into an equivalent resistance module through a first control input end, controlling the first transmission door switch to be opened through the first control signal, inputting a second control signal into the equivalent resistance module through a second control input end, controlling the second transmission door switch to be closed through the second control signal, and enabling the through silicon via to be tested to be discharged to 0V to the ground within the preset time;

s2, in a testing stage, inputting a preset periodic signal into the public testing unit through a clock port to count, and controlling a third transmission door switch to be disconnected through a third control signal so as to cut off the connection between a standard capacitor in the public testing unit and an on-chip power supply; and meanwhile, the first transmission gate switch and the second transmission gate switch are controlled to be alternately turned on and turned off in a preset period through a first control signal and a second control signal respectively, the first control signal and the second control signal are periodically switched between 0/1 to obtain voltage test data of the standard capacitor, the voltage test data are converted into pulse digital signals through the common test unit and are output by the test output end to obtain a test result of the to-be-tested through silicon via.

The features mentioned above can be combined in various suitable ways or replaced by equivalent features as long as the object of the invention is achieved.

The invention has the advantages that the TSV is tested before binding by adopting the TSV test circuit based on the switched capacitor, the test circuit has simple structure and high effectiveness, and has higher test precision; the test circuit is less influenced by process deviation (processing), and the test robustness is high; the test circuit can be used for testing TSV leakage faults, open-circuit faults and resistive faults, and the fault types are wide in coverage; the testing circuit reasonably utilizes on-chip resources, has short testing time and occupies small area.

Drawings

FIG. 1 is a circuit diagram of an embodiment of a switched capacitor based TSV test circuit according to the present invention;

FIG. 2 is a schematic diagram of an equivalent resistance unit according to the present invention;

FIG. 3 is a schematic diagram of a TSV test circuit based on a switched capacitor according to the present invention;

FIG. 4 is a schematic diagram of the duty cycle of the transmission gate switches S1 and S2;

FIG. 5 is a graph of accuracy of TSV high resistance fault determination;

FIG. 6 is a timing diagram of a TSV leakage fault test;

FIG. 7 is a graph of a fault-free TSV leakage fault test result;

FIG. 8 shows the presence of 20. mu. omega^-1And (5) a leakage fault test result chart of the leakage fault TSV.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.

As shown in fig. 1, a TSV test circuit based on switched capacitors includes:

the equivalent resistance unit comprises a plurality of equivalent resistance modules 2, each equivalent resistance module 2 corresponds to a to-be-tested through silicon via, each equivalent resistance module 2 comprises a first control input end, a second control input end, a test port, a charging port and a grounding end, the test port is connected with the test end of the corresponding to-be-tested through silicon via, and the charging ports of all the equivalent resistance modules 2 are connected together to form a charging end of the equivalent resistance unit;

the common test unit 1 comprises a third control input end, a test output end, a clock port, a power supply end and an electric quantity output end, the electric quantity output end is connected with the charging end of the equivalent resistance unit, and the common test unit 1 is used for controlling the charging and discharging state of the through silicon via to be tested according to a third control signal of the third control input end, a first control signal of the first control input end and a second control signal of the second control input end so as to test and outputting a test result of the through silicon via to be tested through the test output end.

In the embodiment, the TSV is tested before binding by adopting the TSV test circuit based on the switch capacitor, the test circuit is simple in structure and high in effectiveness, and the test precision is high; the test circuit is less influenced by process deviation (processing), and the test robustness is high; the test circuit can be used for testing TSV leakage faults, open-circuit faults and resistive faults, and the fault types are wide in coverage; the testing circuit reasonably utilizes on-chip resources, has short testing time and occupies small area.

In a preferred embodiment, the equivalent resistance module 2 comprises:

the first transmission gate switch is connected between the charging port and the test end of the through silicon via to be tested in series, and a first control input end is formed at the control end of the first transmission gate switch;

the second transmission gate switch is connected in series between the test end of the through silicon through hole to be tested and the grounding end, and a second control input end is formed at the control end of the second transmission gate switch;

the testing end of the through silicon via to be tested is connected between the first transmission gate switch and the second transmission gate switch.

In the present embodiment, the equivalent resistance unit includes a plurality (i.e., n) of TSV Switched Capacitor equivalent resistance modules 2(Switched-Capacitor resistors). Each module is formed by a pair of transmission gate switches TG1_kAnd

and a TSV to be tested. And the two transmission gate switches of each group of equivalent resistance modules 2 are directly connected with the TSV test ends of the group. Meanwhile, each group of equivalent resistance modules 2 is switched through a transmission gate

And a capacitor C_sConnected as shown in fig. 1. Each equivalent resistance module 2 has two input control signals: CP1_kAnd CP2_kFor controlling a transmission gate switch TG1_kAnd TG2_kOn and off. Since all the equivalent resistance modules 2 are connected to the common test unit 1, pass through CP0, CP1_kAnd CP2_kWith proper signal control, the common test unit 1 can provide test service to each equivalent resistance module 2 in series.

In a preferred embodiment, the common Test Unit 1(Public TSV Test Unit) includes:

the three-input AND gate 12 comprises a first input end, a second input end, a third input end and an output end, wherein the output end of the three-input AND gate 12 forms a test output end, and the first input end forms a clock port;

a third transmission gate switch TG0, one end of the third transmission gate switch TG0 forms a power supply terminal;

one end of the standard capacitor is grounded, and the other end of the standard capacitor is connected with the other end of the third transmission gate switch TG 0;

an inverter 11, an input end of the inverter 11 and a control end of the third transmission gate switch TG0 form a third control input end together, and an output end of the inverter 11 is connected with a second input end of the three-input and gate 12;

and the driver 13, wherein the input end of the driver 13 is simultaneously connected with the other end of the standard capacitor and the other end of the third transmission gate switch TG0 to form the power output end of the common test unit 1.

In this embodiment, the common test unit 1 comprises a third transmission gate switch TG0, an inverter 11, and a standard capacitor C_sA driver 13 and a three-input and gate 12. The common test unit 1 has three input signals: voltage signal V_DDThird control information CP0, test clock signal CLK and test output signal Count. Voltage signal V_DDIs a standard on-chip voltage signal, where V can be set_DD1.1V, the third control information CP0 is a control signal of a transmission gate TG0, which can be opened to make the voltage signal V_DDFor standard capacitor C_sCharging is carried out, the testing clock signal CLK can automatically digitize the TSV testing result, and the testing output signal Count can be directly used for judging TSV faults.

As shown in fig. 2, the TSV in the test circuit may be equivalent to a capacitor C_FAnd C_BAnd a resistance R_oForming a pi-type circuit module. Wherein, the capacitor C_FAnd C_BParasitic capacitance and resistance R caused by TSV insulating wall_oIs the on-resistance of the TSV. By adding switches S1 and S2 that are alternately turned on across the TSV, a switched capacitor equivalent resistance can be constructed, as shown in the box area in fig. 2. Assuming that the initial voltage on the TSV capacitor is 0, when switch S1 is closed, switch S2 is open t_p1At second, the voltage on the TSV capacitor is:

wherein, V (t)_p1) Is TSV inlet end at t_p1Voltage at time, V_DDIs the supply voltage charging the TSV, τ is the time constant.

At this time, according to the formula q ═ CV, the charge amount on the TSV capacitor is:

q_IN＝C_TSVV(t_p1) (2)

wherein, C_TSV＝C_F+C_B。

The states of the discontinuous switches S1 and S2 are set to avoid the race risk phenomenon, and the period of switch switching is controlled to be T_cI.e. as shown in fig. 4.

In the second half of the cycle, when the switch S1 is open, the switch S2 is closed t_p2At second, the voltage on the TSV capacitor is:

wherein, V (T)_c/2+t_p2) TSV inlet end is at T_c/2+t_p2The voltage at time, τ, is a time constant.

At this time, the charge amount on the TSV capacitor is:

then the subtraction of equation (2) and equation (4) can be performed over the entire T_cThe amount of charge transfer on the capacitor is, in cycles:

according to the definition of the current, it can be obtained that:

wherein T is_cIs a charge transfer cycle (i.e., a cycle in which the switches S1 and S2 are alternately turned on, as shown in fig. 4).

Substituting equation (5) into equation (6) yields:

equation (7) can be converted to:

the conclusion is drawn that the RC parameter of the TSV can be converted into an equivalent resistor R through a switch capacitor circuit_SCAnd the RC parameter of the TSV can be measured by measuring the value, so that the TSV fault is judged. Therefore, a first order RC discharge circuit as shown in FIG. 3 is used to measure the equivalent R of the TSV_SCThe value is obtained. And the final test circuit is in the configuration shown in figure 1.

In summary, the TSV test circuit based on the switch capacitor has the following beneficial effects:

1) by multiplexing the common test unit 1, the area overhead of the test circuit can be reduced to the maximum extent, and the influence of circuit parameter deviation on the measurement result can be effectively reduced.

2) Converting the TSV resistance-capacitance parameters difficult to measure into the equivalent resistance parameters R easy to measure through the equivalent resistance unit_SCMaking the measurement easy to implement.

3) The measurement result can be directly converted into a pulse digital signal for output by utilizing the switch period Tc of the switch capacitor for counting, so that the cost of external Auxiliary Test Equipment (ATE) is reduced while fault judgment is facilitated.

For the area of the TSV test circuit based on the switched capacitor, an original model in a Nangate 45nm standard library can be adopted to be substituted into a Cadence RTL compiler for estimation, and the estimation result is as follows:

for one transfer gate switch TG, its chip area is: 0.532 mu m²(ii) a For a three-input AND gate 12AND3_ X2, the chip area is: 1.064 μm²For the 4-fold drive capability driver 13BUF _ X4, the chip area is: 0.798 μm²For 4 times of driving capability inversion, INV _ X4 occupies the following area: 0.532 mu m². The chip area of the entire common test unit 1 is therefore:

0.532μm²+1.064μm²+0.532μm²+0.798μm²＝2.926μm²

for each test TSV, the test circuit area is only the area overhead of two transmission gate switches, namely:

0.532μm²x2＝1.064μm²

in conclusion, the TSV test circuit based on the switched capacitor can be realized by utilizing reasonable on-chip resources.

For the test time, an estimate was also made. For each TSV, 200ns of time is needed for test initialization, 5000ns of time is needed for TSV leakage and open circuit tests, and 5000ns of time is needed for TSV high resistance tests. The test time required for each TSV is therefore about:

200ns+5000ns+5000ns＝10200ns

assuming 1000 TSVs on the chip, the overall test time is about 8000ns after a configuration time of about 1000x2x 4:

10200nsx1000+8000ns＝10.2ms

therefore, the method has short test time and cost and high test efficiency.

The invention also provides a testing method of the TSV testing circuit based on the switched capacitor, which is used for testing a plurality of through silicon vias to be tested one by one, and respectively connecting each through silicon via to be tested to the corresponding equivalent resistance module 2, and the method for testing each through silicon via to be tested comprises the following steps:

s1, in an initialization stage, inputting a preset clock signal into a public test unit through a clock port, inputting a third control signal into the public test unit through a third control input end, controlling a third transmission door switch to be closed through the third control signal, enabling a standard capacitor in the public test unit to be charged to a preset voltage within a preset time, inputting a first control signal into an equivalent resistance module through the first control input end, controlling the first transmission door switch to be disconnected through the first control signal, inputting a second control signal into the equivalent resistance module through the second control input end, controlling the second transmission door switch to be closed through the second control signal, and enabling a to-be-tested through silicon via to be discharged to the ground to 0V within the preset time;

s2, in a testing stage, inputting a preset periodic signal into the common testing unit through a clock port to count, and controlling a third transmission door switch to be disconnected through a third control signal so as to cut off the connection between a standard capacitor in the common testing unit and an on-chip power supply; meanwhile, the first transmission gate switch and the second transmission gate switch are respectively controlled by the first control signal and the second control signal to be alternately turned on and off in a preset period, the first control signal and the second control signal are periodically switched between 0/1, voltage test data of the standard capacitor are obtained, the voltage test data are converted into pulse digital signals through the common test unit and are output by the test output end, and therefore the test result of the through silicon via to be tested is obtained.

In the embodiment, for the TSV leakage fault, the method can judge 1 mu omega^-1The above leakage failure; for TSV open circuit faults, the method can judge open circuit faults at any position 90% of the front position of the TSV; for the TSV high resistance fault, the judgment size and the fault position have close relation, and the specific judgment precision is shown in fig. 5. In fig. 5, the abscissa represents the position of the fault, and the ordinate represents the resistance value of the fault.

After the circuit model is built in HSPICE (a tool compatible with many major EDA design tools), leakage fault tests are performed on two TSVs separately. Where TSV1 is a non-failing TSV, and TSV2 has a leakage failure of 50k Ω. The parameters in the test process are set as follows:

failure-free TSV parameters: r ═ 0.1m Ω, C ═ 60fF, G ═ 1p Ω^-1

And (3) fault TSV parameters: r is 0.1m Ω, C is 60fF, and G is 20 μ Ω^-1

Test initialization time: 200 ns;

and (3) testing period: 20 ns;

testing the on-off time of the switch: 5 ns;

on-chip power supply voltage: 1.1V;

capacitance value of standard capacitor: 10 pF;

for convenience of explanation, a test timing diagram of the whole TSV leakage process is first given, as shown in fig. 6.

At the start of the test, a test initialization is first performed, which takes 200ns, and the main purpose is to charge the standard capacitor to 1.1V through the on-chip power supply, and simultaneously discharge the TSV to 0V through the transmission gate TG2 to ground. This phase can be implemented by controlling the transmission gate control signal CP0 to be 1(TG0 closed), CP1 to be 0(TG1 open), and CP2 to be 1(TG2 closed), as shown in fig. 6 in the stage before the dotted line.

When the initialization is finished, the TSV leakage fault test is started, and at the moment, the test pulse starts to count. During the test, the transmission gate TG0 is opened to cut off the reference capacitor C by keeping the control signal CP0 equal to 0_sConnection to an on-chip power supply. Meanwhile, the control signals CP1 and CP2 are periodically switched between 0/1 to control the switches S1 and S2 to be alternately turned on and off at a period of 20ns, as shown in fig. 6 after the dashed line. During this test, the standard capacitance C_sThe charge on the capacitor is transferred to ground through the TSV, and thus the standard capacitor C_sThe voltage on the capacitor will gradually decrease as the test period increases. When standard capacitance C_sWhen the voltage drops below the threshold voltage of the driver 13, the low level signal output by the driver 13 will continue to count the counting pulse. For the TSV with leakage fault, part of charge can leak from a leakage channel in the charge transfer process, so that the standard capacitor C is caused_sThe voltage drop is more rapid, so that whether the TSV to be tested has the leakage fault or not can be judged.

Fig. 7-8 are graphs for a non-failed TSV and the presence of G-20 μ Ω^-1The test result chart of the leakage fault TSV shows that the last pulse count is 128 for the non-fault TSV, and the last pulse count is 51 for the TSV with the leakage fault, so that the fault characteristic is obvious.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.

Claims

1. A TSV test circuit based on switched capacitors comprises:

the equivalent resistance unit comprises a plurality of equivalent resistance modules (2), each equivalent resistance module (2) corresponds to a to-be-tested through silicon via, each equivalent resistance module (2) comprises a first control input end, a second control input end, a test port, a charging port and a grounding end, the test port is connected with the corresponding test end of the to-be-tested through silicon via, and the charging ports of all the equivalent resistance modules (2) are connected together to form the charging end of the equivalent resistance unit;

the common test unit (1) comprises a third control input end, a test output end, a clock port, a power supply end and an electric quantity output end, wherein the electric quantity output end is connected with a charging end of the equivalent resistance unit, and the common test unit (1) is used for controlling the charging and discharging state of the through-silicon via to be tested according to a third control signal of the third control input end, a first control signal of the first control input end and a second control signal of the second control input end so as to test and output a test result of the through-silicon via to be tested through the test output end;

characterized in that said common test unit (1) comprises:

the three-input AND gate (12) comprises a first input end, a second input end, a third input end and an output end, wherein the output end of the three-input AND gate (12) forms the test output end, and the first input end forms the clock port;

a third transmission gate switch (TG0), one end of the third transmission gate switch (TG0) forming the power supply terminal;

a reference capacitor having one end grounded and the other end connected to the other end of the third transmission gate switch (TG 0);

an input end of the inverter (11) and a control end of the third transmission gate switch (TG0) jointly form the third control input end, and an output end of the inverter (11) is connected with a second input end of the three-input AND gate (12);

the input end of the driver (13) is simultaneously connected with the other end of the standard capacitor and the other end of the third transmission gate switch (TG0) to form a power output end of the common test unit (1); the output end of the driver (13) is connected with the third input end of the three-input AND gate (12).

2. Switched capacitor-based TSV test circuit according to claim 1, wherein the equivalent resistance module (2) comprises:

3. A testing method of TSV testing circuit based on the switched capacitor of claim 2, for testing a plurality of through-silicon vias one by one, each through-silicon via to be tested is connected to a corresponding equivalent resistance module,

the equivalent resistance module comprises a first control input end, a second control input end, a test port, a charging port and a grounding end, wherein the test port is connected with the corresponding test end of the through silicon via to be tested, and the charging ports of all the equivalent resistance modules are connected together to form a charging end of the equivalent resistance unit;

the equivalent resistance module also comprises a first transmission gate switch and a second transmission gate switch;

the first transmission door switch is connected between the charging port and the testing end of the through silicon via to be tested in series, and the first control input end is formed at the control end of the first transmission door switch;

the second transmission gate switch is connected in series between the test end of the through silicon via to be tested and the grounding end, and the second control input end is formed at the control end of the second transmission gate switch;

the test end of the through silicon via to be tested is connected between the first transmission gate switch and the second transmission gate switch;

the method for testing each through silicon via to be tested is characterized by comprising the following steps: