CN107749398A - P-type MOSFET preparation method - Google Patents
P-type MOSFET preparation method Download PDFInfo
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- CN107749398A CN107749398A CN201711102808.0A CN201711102808A CN107749398A CN 107749398 A CN107749398 A CN 107749398A CN 201711102808 A CN201711102808 A CN 201711102808A CN 107749398 A CN107749398 A CN 107749398A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 93
- 229910052751 metal Inorganic materials 0.000 claims abstract description 93
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- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000137 annealing Methods 0.000 claims abstract description 20
- 238000002347 injection Methods 0.000 claims abstract description 9
- 239000007924 injection Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 145
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- 239000000463 material Substances 0.000 claims description 18
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- 229910010038 TiAl Inorganic materials 0.000 claims description 6
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- 239000007769 metal material Substances 0.000 claims description 4
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Composite Materials (AREA)
- Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of p-type MOSFET preparation method, including：A p-type MOSFET part is formed on substrate, including：False gate stack above substrate and the grid curb wall around false gate stack；False gate stack is removed to form gate openings；Interfacial oxide layer, high-K gate dielectric layer and the first Metal gate layer are sequentially formed at gate openings；Using isotropic plasma doping in the first Metal gate layer Doped ions, Doped ions is only distributed only in the first Metal gate layer；The second Metal gate layer is formed on the first Metal gate layer to fill gate openings；And carry out annealing and spread Doped ions and accumulate in the lower interface at the upper interface between high-K gate dielectric layer and the first Metal gate layer and between high-K gate dielectric layer and interfacial oxide layer, and interface, lower interface form electric dipole by interfacial reaction on this.The problems such as energy contamination when this method solve ion implanting shadow effect, small energy injection.
Description
Technical field
The disclosure belongs to technical field of semiconductors, is related to a kind of p-type MOSFET preparation method.
Background technology
With the development of semiconductor technology, the characteristic size of mos field effect transistor (MOSFET) is not
It is disconnected to reduce.MOSFET size reduction causes serious short-channel effect, and leakage current sharply increases, and driving current reduces.High K grid
The use of medium allows to increase in the case of keeping equivalent oxide thickness (EOT) constant the physical thickness of gate medium,
Grid tunneling leakage, while EOT reduction thus can be reduced, driving current can be increased.However, traditional polysilicon gate with
High-K gate dielectric is incompatible.Metal gate and high-K gate dielectric are used together the depletion effect that can not only avoid polysilicon gate, reduce
Gate resistance, boron penetration can also be avoided, improve the reliability of device.Therefore, the combination of metal gate and high-K gate dielectric is in MOSFET
In be widely used.Metal gate and the integrated of high-K gate dielectric still suffer from many challenges, such as thermal stability problems, boundary
Face state problem.Especially because Fermi's pinning effect, it is appropriate low to be difficult to acquisition using the MOSFET of metal gate and high-K gate dielectric
Threshold voltage.
P-type MOSFET effective work function should be near Si top of valence band (5.2eV or so).For p-type MOSFET, phase
The combination of the suitable metal gate of selection and high-K gate dielectric is hoped to realize required threshold voltage.However, the choosing only by material
It is difficult to select and obtain so low effective work function.In the prior art, by using the method for ion implanting in the first metal
It is doped in gate layer and distribution of the Doped ions in gate stack is adjusted by subsequent annealing process, adjusts MOSFET's
Threshold voltage, still, the method for existing ion implanting be doped in the presence of its it is intrinsic the shortcomings that, including：Ion implanting shade
Effect；The problem of energy contamination problem and low production efficiency in small energy injection.
The content of the invention
(1) technical problems to be solved
Present disclose provides a kind of p-type MOSFET preparation method, admirably solves the technical problem that the above is run into.
(2) technical scheme
According to an aspect of this disclosure, there is provided a kind of p-type MOSFET preparation method, including：P is formed on substrate
A type MOSFET part, including：Source/drain region in substrate, the false gate stack above substrate between source/drain region
And the grid curb wall around false gate stack；False gate stack is removed to form gate openings on the inside of grid curb wall, makes substrate
Expose on surface；Interfacial oxide layer, high-K gate dielectric layer and the first Metal gate layer are sequentially formed at gate openings；Using it is each to
The plasma doping of same sex Doped ions in the first Metal gate layer, and control the energy of plasma so that doping
Ion is only distributed only in the first Metal gate layer, and the dosage of Doped ions injection is controlled according to desired threshold voltage；Wherein,
The Doped ions are the P-type dopant that can increase effective work function；The second Metal gate layer is formed on the first Metal gate layer
To fill gate openings；And carry out annealing and spread Doped ions and accumulate in high-K gate dielectric layer and the first metal gate
Layer between upper interface at and the lower interface between high-K gate dielectric layer and interfacial oxide layer, and on this interface,
Lower interface is respectively formed electric dipole by interfacial reaction.
In some embodiments of the present disclosure, the energy of plasma doping is between 0.1keV-20keV.
In some embodiments of the present disclosure, the dosage of ion implanting is between 1E13-5E15cm-2Between.
In some embodiments of the present disclosure, P-type dopant includes：Hydride, fluoride and the chloride of boron, are as follows
One kind or its combination in material：B2H6、B4H10、B6H10、B10H14、B18H22、BF3Or BCl3。
In some embodiments of the present disclosure, the material of high-K gate dielectric layer is one kind of following material or its combination：
ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO or
HfLaON。
In some embodiments of the present disclosure, the material of the first Metal gate layer is one kind or its combination in following material：
TiN, TaN, MoN, WN, TaC or TaCN；And/or second Metal gate layer include multiple layer metal material, wherein against the first metal gate
The metal material of layer selects the good metal of oxygen uptake performance, including：At least one of Ti, TiAl, Ta；Followed by potential barrier barrier layer
Metal, including：One or both of TiN, TaN, Ta, MoN, AlN, WN；It is finally filling metal, including：W, Al, TiAl,
One or both of Mo.
In some embodiments of the present disclosure, the thickness of high-K gate dielectric layer is between 1.5nm-5nm；And/or first gold medal
Belong to the thickness of gate layer between 2nm-10nm.
In some embodiments of the present disclosure, the condition that carrying out annealing spreads Doped ions is：Annealing temperature is
350 DEG C -450 DEG C, annealing time 20min-90min.
In some embodiments of the present disclosure, a p-type MOSFET part also includes：Silicification area, it is formed at source/drain region
Surface；And interlayer dielectric layer, be covered in the top of source/drain region, around grid curb wall outer surface and false gate stack top；
The false gate stack includes：False gate medium and false grid conductor, and utilize the table of chemically mechanical polishing planarization interlayer dielectric layer
Face and the top surface of the false grid conductor of exposure.
In some embodiments of the present disclosure, after high-K gate dielectric layer is formed, before the first Metal gate layer is formed also
Comprise the following steps：Made annealing treatment after the making of high-K gate dielectric layer is completed, to improve the quality of high-K gate dielectric layer.
(3) beneficial effect
It can be seen from the above technical proposal that the preparation method for the p-type MOSFET that the disclosure provides, has below beneficial to effect
Fruit：
Using isotropic plasma doping (PLAD) method substitutional ion method for implanting in the first Metal gate layer
Doped p-type dopant, reach the purpose of regulation and control p-type MOSFET effective work functions.The plasma doping obtains each well
Adulterated to the same sex, eliminate the shortcomings that conventional ion injection is intrinsic, including：Ion implanting shadow effect, in small energy injection
Energy contamination problem and low production efficiency the problem of, therefore by improved doping means improve device electrology characteristic,
Reliability and production capacity, in nanoscale 3D cmos circuits and the more production of the Manufacturing Techniques of the nano-device in advanced technology generation
Industry field has more powerful competitiveness.
Brief description of the drawings
Fig. 1 is the flow chart according to embodiment of the present disclosure p-type MOSFET preparation method.
Fig. 2A-Fig. 2 F are the semiconductor junction according to corresponding to each step in embodiment of the present disclosure p-type MOSFET manufacturing process
The schematic cross-section of structure.
Fig. 2A be after the completion of grid technique device the part such as source/drain region, false gate stack, grid curb wall and interlayer dielectric layer
Structural representation.
Fig. 2 B are the structural representation of formation gate openings after the false gate stack of etching.
After Fig. 2 C is are sequentially depositing interfacial oxide layer, high-K gate dielectric layer and the first Metal gate layer at gate openings
Structural representation.
Fig. 2 D are the process schematic of the method doped p-type dopant with PLAD in the first Metal gate layer.
Fig. 2 E are the structural representation for the second Metal gate layer that covering is formed on the first Metal gate layer after doping.
Fig. 2 F are using interlayer dielectric layer as stop-layer, carry out the structural representation after surface planarisation.
【Symbol description】
101- substrates；102- vacation gate mediums；
103- vacation grid conductors；104- grid curb walls；
105- source/drain regions；106- silicification areas；
107- interlayer dielectric layers；108- interfacial oxide layers；
109- high-K gate dielectric layers；The Metal gate layers of 110- first；
The Metal gate layers of 111- second.
Embodiment
Present disclose provides a kind of p-type MOSFET preparation method, by using isotropic plasma doping
(PLAD) method substitutional ion method for implanting doped p-type dopant in the first Metal gate layer, it is effective to reach regulation and control p-type MOSFET
The purpose of work function.The plasma doping obtains good isotropism doping, eliminates conventional ion and injects inherently
Shortcoming, including：Ion implanting shadow effect；The problem of energy contamination problem and low production efficiency in small energy injection,
Therefore by improved doping means device electrology characteristic, reliability and production capacity are improved, in nanoscale 3D cmos circuits and
The more industrial field of the Manufacturing Techniques of the nano-device in advanced technology generation has more powerful competitiveness.
In the disclosure, term " semiconductor structure " refers to the lining formed after each step of experience making semiconductor devices
Bottom and all layers formed on substrate or region.Term " source/drain region " refers to both MOSFET source region and drain regions,
And using one reference sign of identical.Term " P-type dopant " refers to can increase effectively for p-type MOSFET
The dopant of work function.
It describe hereinafter many specific details of the disclosure, such as the structure of device, material, size, processing work
Skill and technology, to be more clearly understood that the disclosure.But just as the skilled person will understand, it can not press
The disclosure is realized according to these specific details.Unless hereinafter particularly point out, the various pieces in semiconductor devices can be with
It is made up of material well known to those skilled in the art, or the material with similar functions of exploitation in the future can be used.
For the purpose, technical scheme and advantage of the disclosure are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, the disclosure is further described.
In first exemplary embodiment of the disclosure, there is provided a kind of p-type MOSFET preparation method.
Fig. 1 is the flow chart according to embodiment of the present disclosure p-type MOSFET preparation method.
Shown in reference picture 1, the p-type MOSFET of disclosure preparation method, including：
Step S102：A p-type MOSFET part is formed on substrate, including：Source/drain region in substrate, serving as a contrast
False gate stack between source/drain region, grid curb wall and interlayer dielectric layer around false gate stack above bottom；
In this step, semiconductor device structure has been completed the fore-end of rear grid technique element manufacturing.In substrate 101
The upper part for forming p-type MOSFET, the part includes：False gate stack, it is formed on substrate 101, including：False gate medium
102 and false grid conductor 103；Grid curb wall 104, it is centered around around false gate stack；Source/drain region 105, in substrate 101, distribution
In the both sides of false gate stack, and including extending at least partially into the extension area of the false lower section of gate medium 102；Silicification area 106, shape
Into in the surface of source/drain region 105；And interlayer dielectric layer 107, it is covered in top, the appearance of grid curb wall 104 of source/drain region 105
Around face.
Fig. 2A be after the completion of grid technique device the part such as source/drain region, false gate stack, grid curb wall and interlayer dielectric layer
Structural representation.In the present embodiment, shown in reference picture 2A, on substrate 101 (for example, silicon substrate or other Semiconductor substrates)
Including the p-type MOSFET limited by shallow trench isolation (not shown) active area.In p-type MOSFET active area, in substrate 101
Upper formation includes false gate medium 102 (for example, silica) and the false grid of false grid conductor 103 (for example, polysilicon, alpha Si) are folded
Layer.The false gate stack is surrounded by grid curb wall 104 (for example, silicon nitride).P-type MOSFET source/drain is formd in the substrate 101
Area 105.Source/drain region 105 is located at the both sides of false gate stack, and can include extending at least partially under false gate medium 102
The extension area of side.Silicification area 106 (for example, nickle silicide) is yet forms both on the surface of source/drain region 105, to reduce source/drain region 105
Series resistance and contact resistance.The semiconductor structure also include covering active area interlayer dielectric layer 107 (for example, silica,
Silicon nitride), the interlayer dielectric layer 107 is covered in the top of source/drain region 105, around the outer surface of grid curb wall 104 and false grid are folded
The top of layer.By chemically-mechanicapolish polishing (CMP), the surface of interlayer dielectric layer 107 and the top of the false grid conductor 103 of exposure are planarized
Portion surface, structure is as shown in Figure 2 A obtained.The interlayer dielectric layer 107 not only protects active area in a subsequent step, and
And also serve as hard mask.
Step S104：False gate stack is removed to form gate openings on the inside of grid curb wall, exposes the surface of substrate；
In this step, by the use of interlayer dielectric layer 107 as hard mask, using the means of dry etching or wet etching by vacation
Gate stack is removed, and gate openings are formed in active area, expose the surface of substrate.
Fig. 2 B are the structural representation of formation gate openings after the false gate stack of etching.In the present embodiment, shown in reference picture 2B,
Interlayer dielectric layer 107 is used as hard mask, by dry etching, such as ion beam milling etching, plasma etching, reactive ion etching, swashs
The methods of light ablation, or by wherein using the wet etching of etchant solutions, false grid conductor 103 is optionally removed, and
And false gate medium 102 is further optionally removed, gate openings, and exposure substrate are formed in p-type MOSFET active area
101 surface.
Step S106：Interfacial oxide layer, high-K gate dielectric layer and the first Metal gate layer are sequentially formed at gate openings；
After Fig. 2 C is are sequentially depositing interfacial oxide layer, high-K gate dielectric layer and the first Metal gate layer at gate openings
Structural representation.In the present embodiment, shown in reference picture 2C, by chemical oxidation or additional thermal oxide, in Semiconductor substrate 101
Exposed surface on formed interfacial oxide layer 108 (for example, silica)；Then known depositing operation, such as atomic layer are passed through
Deposition (ALD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), physical vapour deposition (PVD) (PVD), splash
Penetrate, the Metal gate layer 110 of high-K gate dielectric layer 109 and first, high-K gate dielectric layer are sequentially formed on the surface of semiconductor structure
109 and first Metal gate layer 110 be located on the bottom and side wall in gate openings, but unfilled gate openings.
In the present embodiment, high-K gate dielectric layer 109 is more than SiO by dielectric constant2Suitable material form, such as can be
Selected from ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO and
HfLaON one kind or its combination.First Metal gate layer 110 is made up of the suitable material that can be used for being formed metal gate, such as can
Be selected from TiN, TaN, MoN, WN, TaC and TaCN one kind or its combination.In an example, high-K gate dielectric layer 109
Thickness about 1.5nm-5nm HfO in this way2Layer, the first Metal gate layer 110 are, for example, thickness about 2nm-10nm TiN layer.
Preferably, can also include between the step of forming high-K gate dielectric layer 109 and forming the first Metal gate layer 110
Following steps：Annealed (post deposition annealing) after the deposition of high-K gate dielectric layer 109 is completed, to change
The quality of kind high-K gate dielectric layer 109, this first Metal gate layer 110 for being advantageous to subsequently form obtain uniform thickness.
Step S108：Using isotropic plasma doping (PLAD) method adulterated in the first Metal gate layer from
Son, and control the energy of plasma so that Doped ions are only distributed only in the first Metal gate layer, and according to desired threshold value
Voltage controls the dosage of ion implanting；
In this step, doping is realized in the first Metal gate layer using PLAD method, Doped ions selection can increase
The P-type dopant of effective work function, the typical P-type dopant can be selected from hydride, fluoride and the chloride of boron, such as
B2H6、B4H10、B6H10、B10H14、B18H22、BF3Or BCl3In one kind or its combination, but not limited to this.
Fig. 2 D are the process schematic of the method doped p-type dopant with PLAD in the first Metal gate layer.In this implementation
In example, shown in reference picture 2D, plasma doping is carried out in p-type MOSFET active grid metal area, in the first Metal gate layer 110
With PLAD method doped p-type dopant.
By the energy for controlling PLAD so that PLAD Doped ions are only distributed only in the first Metal gate layer 110, and are not had
Have and enter high-K gate dielectric layer 109.
By the dosage for controlling ion implanting so that the first Metal gate layer 110 has suitable doping concentration, to obtain the phase
The threshold voltage of prestige.
In certain embodiments, PLAD energy is about 0.1keV-20keV；In certain embodiments, the agent of ion implanting
Amount is about 1E13-5E15cm-2。
Step S110：The second Metal gate layer is formed on the first Metal gate layer to fill gate openings；
Fig. 2 E are the structural representation for the second Metal gate layer that covering is formed on the first Metal gate layer after doping.Fig. 2 F
Using interlayer dielectric layer as stop-layer, to carry out the structural representation after surface planarisation.
Shown in reference picture 2E and Fig. 2 F, in this step, the mode for forming the second Metal gate layer 111 is known deposition work
Skill, as ald (ALD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), physical vapor are sunk
Product (PVD), sputtering etc..The thickness of second Metal gate layer 111 is sufficiently thick so as to can at least fill up gate openings, such as Fig. 2 E institutes
Show.This step S110 also includes：Using interlayer dielectric layer 107 as stop-layer, the step of carrying out surface planarisation, such as passing through
Learn the surface of mechanical polishing planarizing semiconductor structures.The surface planarization step removes the second Metal gate layer successively from top to bottom
111st, the first Metal gate layer 110 and high-K gate dielectric layer 109 are located at the part outside gate openings so that the second Metal gate layer
111st, the first Metal gate layer 110 and high-K gate dielectric layer 109 are located at remainder inside gate openings as p-type MOSFET's
Gate stack.
In the present embodiment, p-type MOSFET gate stack includes：Second Metal gate layer 111, the first Metal gate layer 110, high K
Gate dielectric layer 109 and interfacial oxide layer 108, as a result as shown in Figure 2 F.
In the present embodiment, the second Metal gate layer 111 is by low-resistance multilayer suitable material that can be used for forming metal gate
Form.Preferably, the multiple layer metal composition of the second Metal gate layer includes：Metal wherein against the first Metal gate layer 110 selects
The good metal of oxygen uptake performance, Ti is such as selected from, TiAl is one or two kinds of to be formed；Followed by potential barrier barrier metal, TiN such as is selected from,
TaN, Ta, MoN, AlN, WN one or two kinds of compositions；It is finally that filling metal is such as selected from W, Al, TiAl, Mo one kind or two
Kind even a variety of compositions, but the second Metal gate layer 111 respectively forms metal and is not limited only to above-mentioned material.
Step S112：Carrying out annealing spreads Doped ions and accumulates in high-K gate dielectric layer and the first Metal gate layer
Between upper interface at and the lower interface between high-K gate dielectric layer and interfacial oxide layer, and on this interface, under
Interface forms electric dipole by interfacial reaction；
After the gate stack for completing p-type MOSFET in step s 110, this step S112 annealing steps are carried out.
In the present embodiment, in inert atmosphere (such as N2) or weak reducing atmosphere (such as N2And H2Mixed atmosphere) in enter
Row annealing.In an example, annealed in stove, annealing temperature is about 350 DEG C -450 DEG C, and annealing time is about 20-90
Minute.Annealing drives the Doped ions of injection to spread and accumulates in the upper interface of high-K gate dielectric layer 109 and lower interface, and
Electric dipole is further formed by interfacial reaction in the upper and lower interface of high-K gate dielectric layer 109.Here, high-K gate dielectric layer
109 upper interface refers to its interface between the first Metal gate layer 110 of top, and the lower interface of high-K gate dielectric layer 109 refers to
Its interface between the interfacial oxide layer 108 of lower section.
The annealing changes the distribution of Doped ions.On the one hand, mixed what the upper interface of high K grid interlayer matter 109 was built up
Heteroion had both changed the property of metal gate, also formed dipole in interface, so as to advantageously have adjusted having for P-MOSFET
Imitate work function.On the other hand, the Doped ions built up in the lower interface of high-K gate dielectric layer 109 also form the electricity of suitable polarity
Dipole, so as to advantageously further adjust P-MOSFET effective work function.
In summary, present disclose provides a kind of p-type MOSFET preparation method, by using isotropic plasma
Body adulterates (PLAD) method substitutional ion method for implanting doped p-type dopant in the first Metal gate layer, reaches regulation and control p-type
The purpose of MOSFET effective work functions.The plasma doping obtains good isotropism doping, eliminates conventional ion
Inject the shortcomings that intrinsic, including：Ion implanting shadow effect；Energy contamination problem and low production efficiency in small energy injection
The problem of lower, therefore device electrology characteristic, reliability and production capacity are improved by improved doping means, in nanoscale 3D
Cmos circuit and the more industrial field of the Manufacturing Techniques of the nano-device in advanced technology generation have more powerful competitiveness.
It should be noted that do not describe MOSFET all details hereinbefore, such as source/drain region contacts, added
Interlevel dielectric layer and conductive channel formation.The standard CMOS process of above-mentioned part is formed known to those skilled in the art
And how to be applied in the MOSFET of above-described embodiment, therefore this is no longer described in detail.
It should also be noted that, the direction term mentioned in embodiment, for example, " on ", " under ", "front", "rear", " left side ",
" right side " etc., only it is the direction of refer to the attached drawing, is not used for limiting the protection domain of the disclosure.Through accompanying drawing, identical element by
Same or like reference represents.When understanding of this disclosure may be caused to cause to obscure, conventional structure will be omitted
Or construction.And the shape and size of each part do not reflect actual size and ratio in figure, and only illustrate the embodiment of the present disclosure
Content.In addition, in the claims, any reference symbol between bracket should not be configured to the limit to claim
System.
Unless there are known entitled phase otherwise meaning, the numerical parameter in this specification and appended claims are approximations, energy
Enough required characteristic changings according to as obtained by content of this disclosure.Specifically, it is all to be used in specification and claim
The numeral of the middle content for representing composition, reaction condition etc., it is thus understood that repaiied by the term of " about " in all situations
Decorations.Generally, the implication of its expression refers to include by specific quantity ± 10% change in certain embodiments, at some
± 5% change in embodiment, ± 1% change in certain embodiments, in certain embodiments ± 0.5% change.
Furthermore word "comprising" or " comprising " do not exclude the presence of element or step not listed in the claims.Positioned at member
Word "a" or "an" before part does not exclude the presence of multiple such elements.Specification and the sequence used in claim
The word of numerical example such as " first ", " second ", " the 3rd ", to modify corresponding element, itself it is not meant to that the element has
Any ordinal number, does not represent a certain element and the order in the order or manufacture method of another element yet, and those ordinal numbers make
With only be used for enable with certain name an element be able to make clear differentiation with another element with identical name.
Particular embodiments described above, the purpose, technical scheme and beneficial effect of the disclosure are carried out further in detail
Describe in detail bright, should be understood that the specific embodiment that the foregoing is only the disclosure, be not limited to the disclosure, it is all
Within the spirit and principle of the disclosure, any modification, equivalent substitution and improvements done etc., the guarantor of the disclosure should be included in
Within the scope of shield.
Claims (10)
1. a kind of p-type MOSFET preparation method, including：
A p-type MOSFET part is formed on substrate, including：Source/drain region in substrate, above substrate positioned at source/
False gate stack between drain region and the grid curb wall around false gate stack；
False gate stack is removed to form gate openings on the inside of grid curb wall, exposes the surface of substrate；
Interfacial oxide layer, high-K gate dielectric layer and the first Metal gate layer are sequentially formed at gate openings；
Using isotropic plasma doping in the first Metal gate layer Doped ions, and control the energy of plasma
Amount so that Doped ions are only distributed only in the first Metal gate layer, and control Doped ions injection according to desired threshold voltage
Dosage；Wherein, the Doped ions are the P-type dopant that can increase effective work function；
The second Metal gate layer is formed on the first Metal gate layer to fill gate openings；And
Carry out the upper interface that annealing spreads Doped ions and accumulated between high-K gate dielectric layer and the first Metal gate layer
And the lower interface between high-K gate dielectric layer and interfacial oxide layer, and interface, lower interface pass through interface on this
Reaction is respectively formed electric dipole.
2. preparation method according to claim 1, wherein, the energy of the plasma doping is between 0.1keV-20keV
Between.
3. preparation method according to claim 1, wherein, the dosage of the ion implanting is between 1E13-5E15cm-2It
Between.
4. preparation method according to claim 1, wherein, the P-type dopant includes：The hydride of boron, fluoride and
Chloride, it is one kind in following material or its combination：B2H6、B4H10、B6H10、B10H14、B18H22、BF3Or BCl3。
5. preparation method according to claim 1, wherein, the material of the high-K gate dielectric layer is one kind of following material
Or its combination：ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、
HfLaO or HfLaON.
6. preparation method according to claim 1, wherein：
The material of first Metal gate layer is one kind or its combination in following material：TiN, TaN, MoN, WN, TaC or
TaCN；And/or
Second Metal gate layer includes multiple layer metal material, wherein the metal material against the first Metal gate layer selects oxygen uptake
The good metal of energy, including：At least one of Ti, TiAl, Ta；Followed by potential barrier barrier metal, including：TiN, TaN, Ta,
One or both of MoN, A1N, WN；It is finally filling metal, including：One or both of W, Al, TiAl, Mo.
7. preparation method according to claim 1, wherein：
The thickness of the high-K gate dielectric layer is between 1.5nm-5nm；And/or
The thickness of first Metal gate layer is between 2nm-10nm.
8. preparation method according to claim 1, wherein, the condition for carrying out annealing and spreading Doped ions
For：Annealing temperature is 350 DEG C -450 DEG C, annealing time 20min-90min.
9. preparation method according to claim 1, wherein, a part of the p-type MOSFET also includes：Silicification area, shape
Into in the surface of source/drain region；And interlayer dielectric layer, it is covered in the top of source/drain region, is around grid curb wall outer surface and false
The top of gate stack；The false gate stack includes：False gate medium and false grid conductor, and utilize and chemically-mechanicapolish polish planarization layer
Between the surface of dielectric layer and the top surface of the false grid conductor of exposure.
10. according to the preparation method described in any one of claim 1 to 9, wherein, after high-K gate dielectric layer is formed, formed
Also comprise the following steps before first Metal gate layer：Made annealing treatment after the making of high-K gate dielectric layer is completed, to improve height
The quality of K gate dielectric layers.
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