CN107742607A - A kind of method that film resistor is made of ICP dry etchings - Google Patents
A kind of method that film resistor is made of ICP dry etchings Download PDFInfo
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- CN107742607A CN107742607A CN201710767049.3A CN201710767049A CN107742607A CN 107742607 A CN107742607 A CN 107742607A CN 201710767049 A CN201710767049 A CN 201710767049A CN 107742607 A CN107742607 A CN 107742607A
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000001312 dry etching Methods 0.000 title claims abstract description 25
- 239000010408 film Substances 0.000 claims abstract description 61
- 230000000873 masking effect Effects 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 238000000926 separation method Methods 0.000 claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 6
- 229910019974 CrSi Inorganic materials 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 230000000717 retained effect Effects 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 229910016570 AlCu Inorganic materials 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 210000002381 plasma Anatomy 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000000203 mixture Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 150000003254 radicals Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Semiconductor Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of method that film resistor is made of ICP dry etchings, it is characterised in that including：Substrate dielectric layer, thin film resistive layer, masking layer, dielectric layer, separation layer and metal level.Follow the steps below：1) one layer of resistive film layer is deposited on substrate dielectric layer.2) one layer of masking layer is deposited on the resistive film layer.3) resistive film layer and masking layer are removed by the method for ICP dry etchings, forms resistance pattern.4) one layer of dielectric layer is deposited on the resistance pattern.Unnecessary dielectric layer is removed using lithographic etch process, retains termination dielectric layer.5) masking layer unnecessary on thin film resistive layer is removed using etching technics, retains the masking layer under the protection of termination dielectric layer.6) separation layer is deposited on resistance pattern, and etches to form connecting hole in resistance termination.7) deposited metal, connecting hole is filled, draws resistance.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, specifically a kind of side that film resistor is made of ICP dry etchings
Method.
Background technology
CRSI film resistors are compared compared with diffusion resistance with injection resistance, have that temperature coefficient is lower, parasitic parameter is smaller and
The advantages that Standard resistance range is wider, therefore become the basis of high-precision integrated circuit and modular circuit precision resistance network.With
Integrated circuit is to high accuracy, the further development in high stability direction, the CRSI film resistors to forming precision resistance network
Preparation technology proposes higher requirement.
CRSI generally use wet-etching technologies, but wet etching is poor to the controlling of critical size, and it is thin to limit CrSi
The application of film.And the United States Patent (USP) US20110086488AL for authorizing Abbas ALI et al. discloses one kind and utilizes Cl2 and O2Carve
The method of the films such as SICR, SICRC, SICRCO, CRON is lost, it is slower using reactive ion etching (RIE) technique, etch rate
(SICRC, reaction rate 0.57nm/Sec that 34nm is etched in 60 seconds), and it is difficult to the Damage Coutrol of substrate.
Substrate is processed compared with RIE techniques, in ICP plasmas and carries automatic bias, in process, passes through control
The size of substrate radio frequency automatic bias can control plasma to the size of substrate bombarding energy, overcome ion bombardment energy and
Plasma density is unable to the shortcomings that independent control.
The content of the invention
Present invention aim to address problems of the prior art, there is provided one kind makes film with ICP dry etchings
The method of resistance, to realize that high etch rate improves production capacity, control and substrate dielectric is damaged, the CRSI for obtaining high stability is thin
Film, application of the extension CRSI metal thin film resistors in IC products.
To realize that the technical scheme that the object of the invention uses is a kind of such, inductively coupled plasma (ICP)
The method that dry etching makes film resistor, it is characterised in that including：Substrate dielectric layer, thin film resistive layer, masking layer, medium
Layer, separation layer and metal level.
Follow the steps below：
1) one layer of resistive film layer is deposited on substrate dielectric layer.
2) one layer of masking layer is deposited on the resistive film layer.
3) resistive film layer and masking layer are removed by the method for ICP dry etchings, forms resistance pattern.
4) one layer of dielectric layer is deposited on the resistance pattern.Unnecessary dielectric layer is removed using lithographic etch process, is protected
Stay termination dielectric layer.
5) masking layer unnecessary on thin film resistive layer is removed using etching technics, retains the masking under the protection of termination dielectric layer
Layer.
6) separation layer is deposited on resistance pattern, and etches to form connecting hole in resistance termination.
7) deposited metal, connecting hole is filled, draws resistance.
Further, the resistive film layer in the step 1) is the metallic film containing Cr, including CrSi.
Further, the masking layer in the step 2) is to include Ti or Tin with high selectivity material, the masking layer.
The selection of the resistance film layer material and masking layer material is compared more than or equal to 6.
Further, ICP plasma etchings are used in the step 3), chamber pressure 10~30mTorr, ICP RF are
200~600w, BIAS RF are 80~200w.
The etching gas include Cl2, HBr and Ar.Cl in etching gas2For 30~100sccm, HBr is 10~
30sccm, Ar are 40~200sccm.
Further, the dielectric material of the dielectric layer in the step 4) includes SiO2Or Si3N4。
Further, the material of the separation layer in the step 6) is Si3N4。
Further, the material of the metal level in the step 7) is conductive metallic material, the metal level include AlSiCu,
Al or AlCu.
The solution have the advantages that unquestionable, the present invention has advantages below：
1) present invention uses ICP dry etch process, by the control of article on plasma quantity and energy, can effectively go
Except film resistor material, and effective control is realized to substrate damage.
2) a kind of method for making film resistor that the present invention uses, the stabilization of thin-film material resistance can effectively be ensured
Property, the temperature coefficient of CRSI resistance films reaches -10~+10ppm；
Brief description of the drawings
Fig. 1 is to deposit the schematic diagram of thin film resistive layer and masking layer in substrate dielectric layer surface in the present invention；
Fig. 2 is the stereogram that photoetching offset plate figure is formed on masking layer；
Fig. 3 be dry etching after formd on substrate dielectric layer CRSI/ shelter layer pattern stereogram；
Fig. 4 is the schematic diagram of the dielectric layer deposited on resistance pattern；
Fig. 5 is reservation termination dielectric layer schematic diagram after dry etching；
Fig. 6 is to remove the figure after unnecessary masking layer；
Fig. 7 is the schematic diagram that separation layer is deposited on figure in figure 6；
Fig. 8 is to form the schematic diagram of contact hole in termination；
Fig. 9 is Metal deposition schematic diagram；
Figure 10 is the schematic diagram that metal draws film resistor.
In figure：Substrate dielectric layer 1, thin film resistive layer 2, masking layer 3, dielectric layer 4, separation layer 5 and metal level 6.
Embodiment
With reference to embodiment, the invention will be further described, but should not be construed the above-mentioned subject area of the present invention only
It is limited to following embodiments.Without departing from the idea case in the present invention described above, according to ordinary skill knowledge and used
With means, various replacements and change are made, all should be included within the scope of the present invention.
Embodiment 1：
A kind of method that film resistor is made of ICP dry etchings, it is characterised in that including：Substrate dielectric layer 1, film
Resistive layer 2, masking layer 3, dielectric layer 4, separation layer 5 and metal level 6.
Follow the steps below：
1) one layer of resistive film layer 2 is deposited on substrate dielectric layer 1.
Resistive film layer 2 in the step 1) is the metallic film containing Cr, including CrSi.
2) one layer of masking layer 3 is deposited on the resistive film layer 2.
Masking layer 3 in the step 2) is to include Ti or Tin with high selectivity material, the masking layer 3.
The selection of the material of resistive film layer 2 and the material of masking layer 3 is compared more than or equal to 6.
3) resistive film layer 2 and masking layer 3 are removed by the method for ICP dry etchings, forms resistance pattern.
Using ICP plasma etchings in the step 3), chamber pressure 10~30mTorr, ICP RF is 200~
600w, BIAS RF are 80~200w.
The etching gas include Cl2, HBr and Ar.Cl in etching gas2For 30~100sccm, HBr is 10~
30sccm, Ar are 40~200sccm.
4) one layer of dielectric layer 4 is deposited on the resistance pattern.Unnecessary dielectric layer 4 is removed using lithographic etch process,
Retain termination dielectric layer 4.
The dielectric material of dielectric layer 4 in the step 4) includes SiO2Or Si3N4。
5) masking layer 3 unnecessary on thin film resistive layer 2 is removed using etching technics, is retained under the protection of termination dielectric layer 4
Masking layer 3.
6) separation layer 5 is deposited on resistance pattern, and etches to form connecting hole in resistance termination.
The material of separation layer 5 in the step 6) is Si3N4。
7) deposited metal 6, connecting hole is filled, draws resistance.
The material of metal level 6 in the step 7) is conductive metallic material, the metal level 6 include AlSiCu, Al or
AlCu。
Embodiment 2：
A kind of method that film resistor is made of ICP dry etchings, it is characterised in that including：Substrate dielectric layer 1, film
Resistive layer 2, masking layer 3, dielectric layer 4, separation layer 5 and metal level 6.
Follow the steps below：
1) as shown in figure 1, depositing one layer of resistive film layer 2 on substrate dielectric layer 1.
The dielectric of substrate dielectric layer 1；
The resistive film layer 2 is CrSi, and the thickness of resistive film layer 2 is 45 ± 5nm；
2) one layer of masking layer 3 is deposited on the resistive film layer 2 as shown in Figure 1.
Masking layer 3 in the step 2) is to include Ti or Tin with high selectivity material, the masking layer 3；It is described to cover
The thickness for covering layer 3 is about 10 ± 1nm.
The selection of the material of resistive film layer 2 and the material of masking layer 3 is compared more than or equal to 6.
3) resistive film layer 2 and masking layer 3 are removed by the method for ICP dry etchings, forms resistance pattern.
3.1) as shown in Fig. 2 coating the positive photoresist that a layer thickness is 1.23 ± 0.1um, photoresist on masking layer 3
Through front baking, exposure, after dry, after development is graphical, obtain the etch mask with required etched features；
3.2) after making litho pattern, masking layer/CRSI films are performed etching using ICP etching machines, etching parameters
It is arranged to：
Chamber pressure is 10~30mt, and ICP RF are 200~600w, and BIAS RF are 80~200w, Cl2Gas flow
For 30~100sccm, HBr gas flow is 10~30sccm；Ar gas flow is 40~200sccm；
Main quarter is end point determination, and the time is 12~18 seconds, and the second step over etching time is 10 ± 5sec；Obtain such as Fig. 3 institutes
The figure shown.
4) one layer of dielectric layer 4 is deposited on the resistance pattern.Unnecessary dielectric layer 4 is removed using lithographic etch process,
Retain termination dielectric layer 4.
Specifically：One layer of dielectric layer 4 is first deposited on resistance pattern, figure termination is retained after gluing, exposure, development
Photoresist, remove unnecessary dielectric layer using dry etching, obtain figure as shown in Figure 5.
The dielectric layer 4 is SiO2, thickness 100nm-200nm；
5) masking layer 3 unnecessary on thin film resistive layer 2 is removed using etching technics, is retained under the protection of termination dielectric layer 4
Masking layer 3.
Specifically：After dry etching obtains resistance film figure, photomask surface glue is removed, using etching technics, is removed not
Masking layer under being protected by dielectric layer, obtains figure as shown in Figure 6.
In the present embodiment, unnecessary masking layer is removed using etching technics, etch period is 120 seconds~270 seconds.
6) separation layer 5 is deposited on resistance pattern, and etches to form connecting hole in resistance termination.
The material of separation layer 5 in the step 6) is Si3N4, the thickness of the separation layer 5 is about 90-150nm；
A contact hole is etched using being dry-etched on the masking layer of resistance film termination, as shown in Figure 7 and Figure 8.
7) deposited metal 6, connecting hole is filled, draws resistance.
Specifically：As shown in figure 9, in Si3N4Deposited metal 6 on film, the metal level in the present embodiment are that AlSiCu is closed
Gold, thickness are 2 ± 0.5um, and unnecessary metal material is removed by lithographic etch process, obtains figure as indicated by 10.
Embodiment 3：
In the present embodiment, the design parameter performed etching using ICP to CRSI metal levels is as shown in table 1：
Table 1
Specifically：
The OMEGA boards of TRIKON companies are utilized in the present invention, by the way of two steps etching：
The first step, the etching gas used is Cl2, HBr and Ar, and by way of end point determination, for etching big portion
Parting category；
First step etching uses Cl in the present invention2, HBr and Ar flow specifically can be according to the compositions and etching of metallic film
It is required that it is adjusted, wherein Cl2For main etching gas, Ar mainly provides physical bombardment；HBr is used for auxiliary etch and side wall
Protection；
The first step is etching through the mode detection etch terminal of end point determination, in the present embodiment, 55 ± 6nm masking
12~18sec of layer/CRSI films catches terminal, and etch rate is 2.72~5nm/sec.
Second step, by adjusting power, pressure and reacting gas ratio, remaining a small amount of metal is removed, ensures the damage of substrate
Wound control and side wall protection.
Above-mentioned three kinds of etching gas are still used in second step etching, but specific flow value has adjusted：Cl2Reduced with Ar,
Reduce and the excess of substrate is damaged；HBr relative increases, increase side wall protection, prevent from undercuting, while power and the more main quarter work of pressure
Step has reduction (specific decrement can the specific requirement according to metallic film composition and to substrate depending on), removes a small amount of residue gold
Category, reduces etch rate, reduces the damage to substrate dielectric layer,
In the present embodiment, using inductively coupled plasma (ICP) dry etch process, high density, high-energy are produced
Ion and free radical, high-speed, anisotropic etching to masking layer/CRSI metal materials are realized, etch rate is up to 2.72
~5nm/sec；To the Damage Coutrol of substrate dielectric layer in 10nm.
It is abnormal in order to avoid occurring in subsequent technique, after obtaining resistance pattern by dry etching, on resistance pattern
One layer of dielectric layer is deposited, using photoetching and dry etch process, unnecessary dielectric layer is removed, after removing photoresist, utilizes etching
Technique, unnecessary masking layer is removed, retain the masking layer under the protection of termination dielectric layer.And separation layer is deposited on above-mentioned figure, lead to
Cross to be dry-etched on the masking layer of termination and output VIA holes；The deposited metal on said structure afterwards, gold is drawn by VIA holes
Belong to electrode, obtain CRSI films.
The normal temperature resistance value and temperature coefficient of the CRSI films are as shown in table 2.
Table 2
| Normal temperature resistance value | 1561 ± 1 Ω/square |
| TCR | - 10~+10ppm/ DEG C |
Claims (7)
- A kind of 1. method that film resistor is made of ICP dry etchings, it is characterised in that including：Substrate dielectric layer (1), film Resistive layer (2), masking layer (3), dielectric layer (4), separation layer (5) and metal level (6)；Follow the steps below：1) one layer of resistive film layer (2) is deposited on substrate dielectric layer (1)；2) one layer of masking layer (3) is deposited on the resistive film layer (2)；3) resistive film layer (2) and masking layer (3) are removed by the method for ICP dry etchings, forms resistance pattern；4) one layer of dielectric layer (4) is deposited on the resistance pattern；Unnecessary dielectric layer (4) is removed using lithographic etch process, Retain termination dielectric layer (4)；5) masking layer (3) unnecessary on thin film resistive layer (2) is removed using etching technics, is retained under termination dielectric layer (4) protection Masking layer (3)；6) separation layer (5) is deposited on resistance pattern, and etches to form connecting hole in resistance termination；7) deposited metal (6), connecting hole is filled, draws resistance.
- A kind of 2. method that film resistor is made of ICP dry etchings according to claim 1, it is characterised in that：It is described Resistive film layer (2) in step 1) is the metallic film containing Cr, including CrSi.
- A kind of 3. method that film resistor is made of ICP dry etchings according to claim 1, it is characterised in that：It is described Masking layer (3) in step 2) is to include Ti or Tin with high selectivity material, the masking layer (3)；The selection of resistive film layer (2) material and masking layer (3) material is compared more than or equal to 6.
- A kind of 4. method that film resistor is made of ICP dry etchings according to claim 1, it is characterised in that：It is described ICP plasma etchings are used in step 3), chamber pressure 10~30mTorr, ICP RF are 200~600w, and BIAS RF are 80 ~200w；The etching gas include Cl2, HBr and Ar；Cl in etching gas2For 30~100sccm, HBr is 10~30sccm, Ar For 40~200sccm.
- A kind of 5. method that film resistor is made of ICP dry etchings according to claim 1, it is characterised in that：It is described The dielectric material of dielectric layer (4) in step 4) includes SiO2Or Si3N4。
- A kind of 6. method that film resistor is made of ICP dry etchings according to claim 1, it is characterised in that：It is described The material of separation layer (5) in step 6) is Si3N4。
- A kind of 7. method that film resistor is made of ICP dry etchings according to claim 1, it is characterised in that：It is described The material of metal level (6) in step 7) is conductive metallic material, and the metal level (6) includes AlSiCu, Al or AlCu.
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| CN201710767049.3A CN107742607B (en) | 2017-08-31 | 2017-08-31 | Method for manufacturing thin film resistor by ICP dry etching |
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Cited By (5)
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| CN110993582A (en) * | 2019-10-31 | 2020-04-10 | 重庆中科渝芯电子有限公司 | Metal thin film resistor suitable for multilayer metal wiring, integrated circuit using metal thin film resistor and integrated circuit manufacturing method |
| CN111510093A (en) * | 2020-04-27 | 2020-08-07 | 济南晶正电子科技有限公司 | Piezoelectric film body for manufacturing bulk acoustic wave device and preparation method thereof |
| CN112186103A (en) * | 2020-10-12 | 2021-01-05 | 北京飞宇微电子电路有限责任公司 | Resistor structure and manufacturing method thereof |
| CN112992447A (en) * | 2019-12-18 | 2021-06-18 | 光颉科技股份有限公司 | Thin film resistor element and method for manufacturing the same |
| CN113410382A (en) * | 2021-06-15 | 2021-09-17 | 西安微电子技术研究所 | Chromium-silicon film resistor and preparation method thereof |
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| CN112992447A (en) * | 2019-12-18 | 2021-06-18 | 光颉科技股份有限公司 | Thin film resistor element and method for manufacturing the same |
| CN111510093A (en) * | 2020-04-27 | 2020-08-07 | 济南晶正电子科技有限公司 | Piezoelectric film body for manufacturing bulk acoustic wave device and preparation method thereof |
| CN111510093B (en) * | 2020-04-27 | 2023-10-03 | 济南晶正电子科技有限公司 | Piezoelectric film body for manufacturing bulk acoustic wave device and preparation method thereof |
| CN112186103A (en) * | 2020-10-12 | 2021-01-05 | 北京飞宇微电子电路有限责任公司 | Resistor structure and manufacturing method thereof |
| CN112186103B (en) * | 2020-10-12 | 2024-03-19 | 北京飞宇微电子电路有限责任公司 | Resistor structure and manufacturing method thereof |
| CN113410382A (en) * | 2021-06-15 | 2021-09-17 | 西安微电子技术研究所 | Chromium-silicon film resistor and preparation method thereof |
| CN113410382B (en) * | 2021-06-15 | 2022-11-29 | 西安微电子技术研究所 | Chromium-silicon film resistor and preparation method thereof |
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