CN107731750B - Ultra-high aspect ratio SONO etching process - Google Patents
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- 238000005530 etching Methods 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 57
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 43
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- 239000010409 thin film Substances 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 103
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 32
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 31
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 15
- 238000001312 dry etching Methods 0.000 claims description 13
- 239000010408 film Substances 0.000 claims description 11
- 238000003486 chemical etching Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000000635 electron micrograph Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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Abstract
The invention provides an SONO etching process, which comprises the steps of changing the structure of a thin film layer in the prior art, optimizing a conventional one-step etching process into a two-step etching process, ensuring that all SONO holes are opened in the etching process, realizing good connection between a channel hole and bottom epitaxial silicon, ensuring that the side wall of the channel hole is not damaged by hard mask silicon nitride, increasing the process window of subsequent processes and improving the performance of products.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to an etching process with ultra-high depth-to-width ratio in a batch process of SONO (silicon-oxide-nitride-oxide) memory chips.
Background
With the increasing widespread application of micro-electromechanical devices and micro-electromechanical systems in the fields of automobiles and consumer electronics and the broad prospect of silicon channel hole etching technology in the future packaging field, the dry plasma deep silicon etching technology gradually becomes one of the most popular heat-generating technologies in the field of micro-electromechanical system processing and the silicon channel hole etching technology.
In the field of semiconductor technology, 3D package-on-package technology has been considered as a key to manufacturing high performance chips with smaller dimensions. In the application of the 3D stacked package technology, deep via etching is usually performed on materials such as silicon, and vertical conduction is made between chips and between silicon wafers through the deep vias formed by etching, so as to realize interconnection between the chips.
In most cases, through-silicon-via fabrication requires different material layers to be opened, and the through-silicon-via formed thereby must meet the requirements of profile control (e.g., sidewall roughness, etc.), so the through-silicon-via etching process becomes the key of the through-silicon-via fabrication technology.
After the conventional Channel Hole (CH) deep Hole etching process is finished, in the conventional Channel Hole etching process, the stacked structure on the substrate is formed by sequentially depositing silicon oxide, silicon nitride and silicon oxide, wherein the thickness of the silicon oxide film is equal to
The film thickness of silicon nitride is
The thickness of the silicon oxide is
And the specific etching thereof generally employs the following steps:
step S1, forming a layer of epitaxial silicon at the bottom of the channel hole through epitaxial growth deposition;
step S2, depositing silicon oxide, silicon nitride, silicon oxide and amorphous silicon film layer on the side wall and bottom of the trench hole in sequence; wherein the amorphous silicon has a thickness of
And step S3, performing one-step dry etching to open the film at the bottom of the trench hole so as to connect the film to the epitaxial silicon.
Fig. 1 is a microscopic electron micrograph of a trench hole generated by the above conventional etching process. As shown in fig. 1, in the above conventional process, since the material of the trench hole and the material of the top hard mask are the same, the etching rate of the top of the trench hole is very high by using a one-step etching method, and the etching rate of the trench hole is very low, which finally causes the defect that the top hard mask of the trench hole is not blocked enough to cause damage, and the bottom of the hole cannot be opened.
Therefore, how to improve the SONO etching process and ensure that all SONO holes are opened, thereby forming an etching process that is connected with bottom epitaxial silicon and obtains a high aspect ratio, is a direction of research by those skilled in the art.
Disclosure of Invention
The invention aims to provide an SONO etching process with an ultrahigh depth-to-width ratio, and by adopting the etching process, on one hand, all SONO holes can be effectively ensured to be opened, and the SONO holes can be well connected with epitaxial silicon at the bottom; on the other hand, the SONO holes are efficiently opened, meanwhile, the hard mask silicon nitride layer is guaranteed not to be damaged, and the process window of the subsequent processing procedure is enlarged.
In order to achieve the purpose, the invention provides a high aspect ratio SONO etching process which is characterized by comprising the steps of providing a substrate stacking structure, specifically, providing a substrate, wherein a plurality of interlaminar dielectric layers and sacrificial dielectric layers which are stacked in a staggered mode are formed on the surface of the substrate, and the sacrificial dielectric layers are formed between the adjacent interlaminar dielectric layers; the interlayer dielectric layer is a silicon oxide layer, the sacrificial dielectric layer is a silicon nitride layer, so that an O/N (O/N Stacks) stack structure is formed, and the silicon nitride layer on the uppermost layer is used as an etching hard mask layer; the method is characterized in that:
step S1: depositing an amorphous silicon layer on the uppermost etching hard mask layer;
step S2: forming a channel hole on the substrate stack structure; forming a layer of epitaxial silicon at the bottom of the channel hole through epitaxial growth deposition;
step S3, depositing silicon oxide, silicon nitride, silicon oxide and amorphous silicon film layer on the side wall and bottom of the trench hole in sequence;
step S4, adopting dry etching to open the silicon layers at the top and the bottom of the trench hole and simultaneously ensuring that the amorphous silicon film on the side wall has a certain residue;
and step S5, adopting dry chemical etching to remove the silicon oxide and the silicon nitride layer deposited at the bottom of the through hole.
Further, the etching process is characterized in that:
the thickness of the silicon oxide layer immediately below the etching hard mask layer is controlled to
The thickness of the etched hard mask silicon nitride layer is controlled to
The thickness of the amorphous silicon layer is controlled to
Further, the etching process is characterized in that:
further, the thickness of the amorphous silicon thin film layer in the step S3 is controlled to be
Furthermore, the etching process is characterized in that:
further, the dry etching method of the present invention is plasma etching.
Furthermore, the etching process is characterized in that:
the etching gas for the plasma etching is Cl2Or HBr.
Furthermore, the etching process is characterized in that:
in the step S4
Furthermore, the etching process is characterized in that:
further, in step S4 of the present invention, the selection ratio of the etching gas to the silicon oxide and silicon nitride layer to the amorphous silicon in the dry chemical etching is set as: OX & SiN/Si >500: 1.
Compared with the prior art, the invention has the following beneficial effects:
firstly, the structure of a thin film layer in the prior art is changed, and a one-step etching process is optimized to a two-step etching process, so that all SONO holes are ensured to be opened, and the channel holes can be well connected with bottom epitaxial silicon;
secondly, the structure of the film layer and the optimization of the etching process ensure that the hard mask silicon nitride is not damaged after etching, and the process window of the subsequent processing procedure is enlarged;
thirdly, through the process, the thickness of the thin film layer can be effectively reduced, so that the depth-to-width ratio of the channel hole and the SONO etching is reduced, and the etching difficulty is reduced.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a microscopic electron micrograph of a trench hole produced by a conventional etching process in the prior art. When the conventional etching process is adopted, as shown in fig. 1a, a hard mask is damaged at the top of a channel hole; as shown in fig. 1b, the bottom of the trench hole is not opened.
FIG. 2 is a schematic structural diagram of a thin film layer in the etching process according to the present invention. Wherein, FIG. 2a is a schematic diagram of a deposition stack structure and a SONO structure on a substrate before the dry etching step of the present invention. Fig. 2b is a schematic structural diagram of the structure after the top and bottom silicon layers of the channel hole are removed after the dry etching in step S4, and the silicon layer remains on the sidewall of the channel hole as shown in fig. 2 b. Fig. 2c shows the structure in which the silicon layer is completely opened at the bottom of the trench hole after the dry chemical etching in step S5.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2, a first embodiment of the present invention provides a novel high aspect ratio SONO etching process after a conventional Channel Hole (CH) deep Hole etching process is completed, wherein the process includes providing a substrate stack structure, specifically, providing a substrate, and forming a plurality of staggered stacked interlayer dielectric layers and sacrificial dielectric layers on the surface of the substrate, where the sacrificial dielectric layers are formed between adjacent interlayer dielectric layers; the interlayer dielectric layer is a silicon oxide layer, the sacrificial dielectric layer is a silicon nitride layer, so that an O/N (O/N Stacks) stack structure 7 is formed, and the silicon nitride layer on the uppermost layer is used as an etching hard mask layer; the method is characterized in that:
step S1: depositing an amorphous silicon layer on the uppermost etching hard mask layer;
step S2: forming a channel hole on the substrate stack structure; forming a layer of epitaxial silicon at the bottom of the channel hole through epitaxial growth deposition;
step S3, depositing silicon Oxide (OX), silicon nitride (SiN), silicon Oxide (OX) and amorphous silicon (Si) film layers on the side wall and the bottom of the trench hole in sequence;
step S4, opening the silicon layers at the top and the bottom of the trench hole by adopting dry etching, and simultaneously ensuring that the silicon layer on the side wall has a certain residue;
and step S5, adopting dry chemical etching to remove the silicon oxide and the silicon nitride layer deposited at the bottom of the through hole.
Specifically, as shown in fig. 2a, 1 is a base silicon layer on a trench hole substrate; wherein a multilayer staggered O/N Stacks (O/N Stacks)7 is formed on the surface of the substrate, and a hard mask layer and an amorphous silicon thin film layer 3(Si) are etched by silicon nitride (SIN) 4;
in the stacked structure, the thickness of the silicon oxide layer 5 immediately adjacent to the etched hard mask layer is controlled to
The thickness of the silicon nitride layer 4 for etching the hard mask layer is controlled to
The thickness of the amorphous silicon layer 3 redeposited on the uppermost etched hard mask layer is controlled in step S1
In step S2, an epitaxial silicon layer 2 is epitaxially grown on the bottom of the trench hole.
In step S3, silicon Oxide (OX), silicon nitride (SiN), silicon Oxide (OX), amorphous silicon (Si) thin film layer are sequentially deposited on the trench hole sidewall and bottom, i.e. the SONO layer structure 6 (in the figure, the structure 6 is sequentially Si, OX, SiN, OX layers from top to bottom) is formed, as shown in fig. 2a, 6, wherein the thickness of the silicon layer on the outermost surface of the SONO structure 6 is preferably as shown in fig. 2a
The deposition steps S1-S3 are conventional in the art, such as the conventional Atomic Layer Deposition (ALD) process for depositing the oxide, and thus are not shown and will not be described in detail herein.
In step S4, the silicon layers at the top and bottom of the trench hole are opened by dry etching, specifically, plasma dry etching, and the silicon layers at the sidewall of the trench hole are ensured to remain, wherein
After etching, the epitaxial silicon layers at the top and the bottom of the channel hole are removed, and only the epitaxial silicon layers on the side wall of the channel hole are remained, as shown in fig. 2 b. After the dry etching in the step S4, the structure of the top and bottom of the trench hole becomes silicon Oxide (OX), silicon nitride (SiN), and silicon Oxide (OX), and the specific structure is shown in fig. 2 b.
The etching gas for dry etching is usually selective, so that the silicon layer can be accurately opened by selecting the type of the etching gas, and the silicon layer on the side wall of the channel hole is ensured to keep a certain residual thickness. For the above purpose, Cl is preferably used2and/HBr is used as etching gas for the plasma etching. Among them, the applicant has shown Cl in a plurality of tests2The selectivity of/HBr to silica is high and there is substantially no loss of silica during this step.
Finally, dry chemical etching is performed in step S5 to selectively etch the silicon oxide and silicon nitride layers (OX & SiN). The selection ratio of the etching gas to the silicon oxide and silicon nitride layers to the amorphous silicon is (OX & SiN/Si) >500:1, so that the silicon oxide and silicon nitride layers (OX & SiN) can be accurately etched enough, the bottom of a channel hole is completely opened, the channel hole can be well connected with epitaxial silicon, and meanwhile, the side wall and the hard mask SiN cannot be damaged. The etched channel hole structure is shown in fig. 2c, where the silicon Oxide (OX), silicon nitride (SiN) layers at the top and bottom of the channel hole are opened.
In summary, the invention changes the structure of the thin film layer in the prior art, thereby improving the performance of the thin film layer in the prior art
Replacement of HMO OX structure
On the other hand, the conventional one-step etching process is optimized into a two-step etching process: the first step is dry etching to etch Si, and the second step is dry chemical etching to etch OX/SIN. The process ensures that all SONO holes are opened in the etching process, thereby realizing good connection between the channel holes and the bottom epitaxial silicon, simultaneously ensuring that the side wall hard mask silicon nitride of the channel holes is not damaged, increasing the process window of the subsequent processing procedure and improving the performance of the product.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (6)
1. An SONO etching process with an ultrahigh depth-to-width ratio comprises the steps of providing a substrate stacking structure, specifically, providing a substrate, wherein a plurality of interlaminar dielectric layers and sacrificial dielectric layers which are stacked in a staggered mode are formed on the surface of the substrate, and the sacrificial dielectric layers are formed between adjacent interlaminar dielectric layers; the interlayer dielectric layer is a silicon oxide layer, the sacrificial dielectric layer is a silicon nitride layer, so that an O/N (O/N Stacks) stack structure is formed, and the silicon nitride layer on the uppermost layer is used as an etching hard mask layer; the method is characterized in that:
step S1: depositing an amorphous silicon layer on the uppermost etching hard mask layer;
step S2: forming a channel hole on the substrate stack structure; forming a layer of epitaxial silicon at the bottom of the channel hole through epitaxial growth deposition;
step S3, depositing silicon oxide, silicon nitride, silicon oxide and amorphous silicon film layer on the side wall and bottom of the trench hole in sequence;
step S4, opening the silicon layers at the top and the bottom of the trench hole by adopting dry etching, and simultaneously ensuring that the amorphous silicon film layer on the side wall has certain residue; the selection ratio of the etching gas to the silicon oxide and the silicon nitride layer to the amorphous silicon is set as follows: OX & SiN/Si >500: 1;
and step S5, adopting dry chemical etching to remove the silicon oxide and the silicon nitride layer deposited at the bottom of the channel hole.
2. An etching process according to claim 1, characterized in that:
the thickness of the silicon oxide layer immediately below the etching hard mask layer is controlled to
The thickness of the etched hard mask silicon nitride layer is controlled to
The thickness of the amorphous silicon layer is controlled to
3. An etching process according to claim 1, characterized in that:
the thickness of the amorphous silicon thin film layer in the step S3 is controlled to
4. An etching process according to claim 1, characterized in that:
the dry etching is plasma etching.
5. An etching process according to claim 4, wherein:
the etching gas for the plasma etching is Cl2Or HBr.
6. An etching process according to claim 1, characterized in that:
controlling the thickness of the silicon layer remaining on the sidewall in the step S4
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