CN107729039A - Embedded OS loading mode selection circuit - Google Patents
Embedded OS loading mode selection circuit Download PDFInfo
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- CN107729039A CN107729039A CN201710834099.9A CN201710834099A CN107729039A CN 107729039 A CN107729039 A CN 107729039A CN 201710834099 A CN201710834099 A CN 201710834099A CN 107729039 A CN107729039 A CN 107729039A
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- gpp
- loading mode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Small-Scale Networks (AREA)
- Stored Programmes (AREA)
Abstract
The present invention proposes a kind of embedded OS loading mode selection circuit.The technical scheme is that：CPLD bus read write line connects GPP by parallel bus respectively；Ethernet link status register connection PHY link establishment instruction pin；Peripheral hardware resets control generator connection FLASH reseting pin and connection PHY reseting pin；Cpu reset control generator connection GPP reseting pin；After bus read write line receives GPP calling-on signal, the value of ethernet link status register is exported to GPP；Ethernet link status register indicates pin level by PHY link establishment, judges whether link is effective, effectively then makes ethernet link status register into 1, invalid, makes ethernet link status register into 0.The present invention solves prior art and realizes scheme that loading mode selects, it is necessary to wait user to input time-out, the problem of influenceing loading velocity by serial port command.
Description
Technical field
The present invention relates to Embedded System Design field, and in particular to a kind of circuit and method of loading mode selection.
Background technology
Embedded OS (Embedded Operating System, referred to as：EOS) refer to be used for embedded system
Operating system.Embedded OS is a kind of widely used system software, is generally all needed in the application system of complexity
Want the support of embedded OS.Before embedded OS work, it is necessary first to startup optimization BootLoader, with
The initialization of embedded OS hardware is completed, then from local storage or the webserver by embedded OS
Image file is loaded onto internal memory, and embedded OS is started working.The position deposited according to image file, can will be embedded
Operating system loading mode is divided into local storage loading and two kinds of loading modes of Ethernet remote loading.Debugging the stage or
The later maintenance stage would generally use Ethernet remote loading embedded OS mirror image, to facilitate debugging.But delivering
User is in use, embedded OS is generally all using local storage loading mode loading embedded OS mirror
Picture, with the start quickly time and reduce the network equipment.
At present, the selection of embedded OS loading mode is generally by serial port command.Realized and added by serial port command
The scheme for carrying model selection is to select loading mode in middle wait user, if time-out is non-selected, selects the loading mould of acquiescence
Formula adds embedded OS to carry image file.In the scene that delivery user uses, it need to generally fix loading mode and be deposited to be local
Reservoir loading mode, although user can also be had to wait for by the way that local storage loading to be set to give tacit consent to loading mode
Input time-out, and time-out time can not too short (be usually 7s), can have little time to input loading mode selection string at all if too short
Mouth order.
There is the following shortcoming in currently existing scheme：
The scheme of loading mode selection is realized by serial port command, it is necessary to wait user defeated in the scene that delivery user uses
Enter time-out, so as to influence loading velocity.
The content of the invention
It is an object of the invention to provide a kind of embedded behaviour for not sacrificing loading velocity and increasing extra hardware spending
Make system loads mode selection circuit and method.
To achieve the above objectives, embedded OS loading mode selection circuit provided by the invention, including：Processor
GPP, ethernet physical layer equipment PHY, parallel Flash chip and complex programmable logic device (CPLD), wherein, inside CPLD
Circuit includes bus read write line, ethernet link status register, peripheral hardware and resets control generator and cpu reset control generation
Device, it is characterised in that：CPLD bus read write line connects processor GPP by parallel bus respectively；Ethernet link state is posted
The link establishment that storage connects PHY by a discrete lines indicates pin；Peripheral hardware resets control generator and passes through a discrete lines
Connect FLASH reseting pin, another discrete lines connection PHY reseting pin；Cpu reset control generator by one from
Loose wire connects GPP reseting pin；After bus read write line receives GPP calling-on signal, by ethernet link status register
Value export to GPP；Ethernet link status register indicates pin level by PHY link establishment, whether judges link
Effectively, effectively, then ethernet link status register is made into 1, it is invalid, then make ethernet link status register into 0.
A kind of embedded OS loading mode system of selection based on foregoing circuit provided by the invention, including it is following
Step：A, after embedded system electrification reset, CPLD peripheral hardware resets control generator and cpu reset control generator successively produces
Raw peripheral hardware reset signal and cpu reset signal, after resetting FLASH and PHY respectively, reset GPP；B, after PHY resets, will attempt to build
Vertical link connection, ethernet link status register receive PHY link establishment indication signal and change ethernet link in real time
The value of status register；C, after GPP resets, BootLoader will be run, BootLoader by bus read write line read with
The too value of net Link Status register, select embedded OS loading mode；If D, value is 1, select Ethernet remote
Journey loading mode, perform Ethernet remote loading embedded OS；If value is 0, local storage loading mould is selected
Formula, perform parallel Flash loadings embedded OS.
The present invention has the advantages that compared to prior art：
The present invention connects GPP by control line, data wire, address wire respectively using CPLD bus read write line；Ethernet link
The link establishment that status register connects PHY by a discrete lines indicates pin；Peripheral hardware resets control generator and passes through one
Discrete lines connect FLASH reseting pin, another discrete lines connection PHY reseting pin；Cpu reset control generator passes through
Piece discrete lines connection GPP reseting pin composition embedded OS loading mode selection circuit；Believed by Link State
Breath realizes that embedded OS loading mode selects, and neither increasing extra hardware spending also not sacrifice loading velocity, solution
Prior art of having determined realizes the scheme of loading mode selection by serial port command, it is necessary to wait in the scene that delivery user uses
Treat that user inputs time-out, the problem of influenceing loading velocity.
Brief description of the drawings
Further illustrate technical scheme below in conjunction with the accompanying drawings, but the content protected of the present invention be not limited to
It is lower described.
Fig. 1 is the embedded OS loading mode selection circuit schematic diagram of the present invention.
Fig. 2 is the schematic flow sheet of Fig. 1 selection embedded OS loading modes.
Embodiment
Refering to Fig. 1.In embodiment described below, embedded OS loading mode selection circuit, including：Processing
Device GPP, ethernet physical layer equipment PHY, parallel Flash chip and complex programmable logic device (CPLD), wherein, inside CPLD
Circuit include bus read write line, ethernet link status register, peripheral hardware reset control generator and cpu reset control occur
Device, GPP connect FLASH by parallel bus respectively, and PHY is connected by medium access control MAC interface.CPLD bus read-write
Device connects GPP by parallel bus respectively；Ethernet link status register connects PHY link establishment by a discrete lines
Indicate pin；Peripheral hardware resets the reseting pin that control generator connects FLASH by a discrete lines, another discrete lines connection
PHY reseting pin；Cpu reset controls reseting pin of the generator by a discrete lines connection GPP；Bus read write line receives
To after GPP calling-on signal, the value of ethernet link status register is exported to GPP；Ethernet link status register leads to
PHY link establishment instruction pin level is crossed, judges whether link is effective, effectively, then changes ethernet link status register
It is invalid into 1, then make ethernet link status register into 0.Cpu reset control generator produces cpu reset signal, resets
GPP.Peripheral hardware resets control generator and produces peripheral hardware reset signal, resets FLASH and PHY respectively.Parallel bus include control line,
Data wire and address wire.
Refering to Fig. 2.Based on above-mentioned embedded OS loading mode selection circuit, adding for embedded OS is selected
Load pattern, in embedded system after electricity, CPLD electrifying self-resettings start normal operation, and peripheral hardware resets control generator and produced point
Not Fu Wei FLASH and PHY peripheral hardware reset signal, cpu reset control generator produce reset GPP cpu reset signal, GPP
After reset, BootLoader is run, BootLoader performs initialization, establishes PHY link connection, and ethernet link state is posted
Storage indicates pin level by PHY link establishment, judges whether link is effective, effectively, then posts ethernet link state
Storage makes 1 into, invalid, then makes ethernet link status register into 0；BootLoader judges ethernet link Status register
Whether the value of device is 0, if 0, then selects local storage loading mode, performs parallel Flash loadings embedded OS,
Otherwise, then Ethernet remote loading pattern is selected, performs Ethernet remote loading embedded OS.
In the loading mode of selection embedded OS, BootLoader reads ether network chain by bus read write line
The value of line state register, select embedded OS loading mode；When the value that bus read write line is read is 1, net is represented
Network link establishment success, then select Ethernet remote loading pattern, performs Ethernet remote loading embedded OS；If read
The value gone out is 0, and expression is that network link is not set up, then selects local storage loading mode, performs parallel Flash loadings insertion
Formula operating system.
Circuit provided by the invention and method are described in detail below by 2 embodiments.
Embodiment 1
In debugging or later maintenance, netting twine is connected, GPP is accessed into network by PHY.
It is electric in embedded system, after CPLD electrifying self-resettings, start normal operation, resetting control generator by peripheral hardware produces
Raw peripheral hardware reset signal, resets parallel Flash and ethernet PHY equipment respectively；After ethernet PHY device reset, link is established
Connection, due to having entered network, connection will be successfully established, and the value of ethernet link status register will be changed to 1.CPLD passes through
Cpu reset control generator produces cpu reset signal, resets GPP.After GPP resets, start to perform BootLoader.
After BootLoader has performed initialization, the value of ethernet link status register is read by bus read write line, due to network
Link establishment success, the value are 1.BootLoader judges whether the value of ethernet link status register is 0, and the value is 1, no
Ethernet remote loading pattern is selected for 0, BootLoader, performs Ethernet remote loading embedded OS.
Embodiment 2
In user's normal use, netting twine is pulled out, network is disconnected.
It is electric in embedded system, after CPLD electrifying self-resettings, start normal operation.CPLD resets control by peripheral hardware
Device produces peripheral hardware reset signal, resets parallel Flash and ethernet PHY equipment respectively.After ethernet PHY device reset, establish
Link connection, because network disconnects, failure is established in connection, and the value of ethernet link status register will be changed to 0.CPLD passes through
Cpu reset control generator produces cpu reset signal, resets GPP.After GPP resets, start to perform BootLoader.
After BootLoader has performed initialization, the value of ethernet link status register is read by bus read write line, due to network
Link establishment fails, and the value is 0.BootLoader judges whether the value of ethernet link status register is 0, and the value is 0,
BootLoader selects local storage loading mode, performs parallel Flash loadings embedded OS.
The present invention is not limited to the above-described embodiments, for those skilled in the art, is not departing from
On the premise of the principle of the invention, some improvements and modifications can also be made, these improvements and modifications are also considered as the protection of the present invention
Within the scope of.The content not being described in detail in this specification belongs to prior art known to professional and technical personnel in the field.
Claims (8)
1. a kind of embedded OS loading mode selection circuit, including：Processor GPP, ethernet physical layer equipment PHY,
Parallel Flash chip and complex programmable logic device (CPLD), wherein, the circuit inside CPLD includes bus read write line, ether
Net Link Status register, peripheral hardware reset control generator and cpu reset control generator, it is characterised in that：CPLD bus
Read write line connects GPP by parallel bus respectively；Ethernet link status register connects PHY link by a discrete lines
Establish instruction pin；Peripheral hardware resets the reseting pin that control generator connects FLASH by a discrete lines, another discrete lines
Connect PHY reseting pin；Cpu reset controls reseting pin of the generator by a discrete lines connection GPP；Bus read write line
After the calling-on signal for receiving GPP, the value of ethernet link status register is exported to GPP；Ethernet link Status register
Device indicates pin level by PHY link establishment, judges whether link is effective, effectively, then by ethernet link Status register
Device makes 1 into, invalid, then makes ethernet link status register into 0.
2. embedded OS loading mode selection circuit as claimed in claim 1, it is characterised in that：GPP passes through respectively
Parallel bus connects FLASH, and PHY is connected by medium access control MAC interface.
3. embedded OS loading mode selection circuit as claimed in claim 1, it is characterised in that：Cpu reset controls
Generator produces peripheral hardware reset signal, resets GPP peripheral hardwares and resets control generator generation peripheral hardware reset signal, resets respectively
FLASH and PHY.
4. embedded OS loading mode selection circuit as claimed in claim 1, it is characterised in that：Parallel bus includes
Control line, data wire and address wire.
5. a kind of method based on embedded OS loading mode selection circuit selection loading mode described in claim 1,
It is characterized in that comprise the following steps：Based on embedded OS loading mode selection circuit, embedded OS is selected
Loading mode, in embedded system after electricity, CPLD electrifying self-resettings start normal operation, and peripheral hardware resets control generator production
It is estranged not Fu Wei FLASH and PHY peripheral hardware reset signal, cpu reset control generator produce reset GPP cpu reset signal,
After GPP resets, BootLoader is run, BootLoader performs initialization, establishes PHY link connection, ethernet link shape
State register indicates pin level by PHY link establishment, judges whether link is effective, effectively, then by ethernet link shape
State register makes 1 into, invalid, then makes ethernet link status register into 0；BootLoader judges ethernet link state
Whether the value of register is 0, if 0, then selects local storage loading mode, performs parallel Flash loadings embedded operation
System, otherwise, then Ethernet remote loading pattern is selected, perform Ethernet remote loading embedded OS.
6. the method for selection loading mode as claimed in claim 5, it is characterised in that：In adding for selection embedded OS
In load pattern, BootLoader reads the value of ethernet link status register by bus read write line, selects embedded operation
System loads pattern；When the value that bus read write line is read is 1, represent that network link is successfully established, then select Ethernet long-range
Loading mode, perform Ethernet remote loading embedded OS；If the value read is 0, expression is that network link is not set up,
Local storage loading mode is then selected, performs parallel Flash loadings embedded OS.
7. the method for selection loading mode as claimed in claim 5, it is characterised in that：Electric in embedded system, the upper electricity of CPLD is certainly
After reset, start normal operation, resetting control generator by peripheral hardware produces peripheral hardware reset signal, resets parallel Flash respectively
With ethernet PHY equipment；After ethernet PHY device reset, link connection is established, connection is successfully established, ethernet link state
The value of register will be changed to 1.
8. the method for selection loading mode as claimed in claim 5, it is characterised in that：CPLD is controlled by cpu reset to be occurred
Device produces cpu reset signal, resets GPP；After GPP resets, start to perform BootLoader, BootLoader has performed initialization
Afterwards, network link is successfully established, and the value that BootLoader reads ethernet link status register by bus read write line is 1.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710834099.9A CN107729039B (en) | 2017-09-15 | 2017-09-15 | Loading mode selection circuit of embedded operating system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710834099.9A CN107729039B (en) | 2017-09-15 | 2017-09-15 | Loading mode selection circuit of embedded operating system |
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| CN107729039A true CN107729039A (en) | 2018-02-23 |
| CN107729039B CN107729039B (en) | 2023-05-26 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113504773A (en) * | 2021-07-29 | 2021-10-15 | 安徽江淮汽车集团股份有限公司 | Ethernet test method and Ethernet test system of vehicle-mounted controller |
| CN114124663A (en) * | 2021-11-16 | 2022-03-01 | 太原市华纳方盛科技有限公司 | Method, device and equipment for disconnecting and reconnecting Ethernet chip |
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| CN114124663A (en) * | 2021-11-16 | 2022-03-01 | 太原市华纳方盛科技有限公司 | Method, device and equipment for disconnecting and reconnecting Ethernet chip |
| CN114124663B (en) * | 2021-11-16 | 2023-12-01 | 太原市华纳方盛科技有限公司 | Method, device and equipment for reconnecting Ethernet chip in disconnected mode |
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