CN107707252A - A kind of FPGA lock phase amplification systems and method - Google Patents
A kind of FPGA lock phase amplification systems and method Download PDFInfo
- Publication number
- CN107707252A CN107707252A CN201710939573.4A CN201710939573A CN107707252A CN 107707252 A CN107707252 A CN 107707252A CN 201710939573 A CN201710939573 A CN 201710939573A CN 107707252 A CN107707252 A CN 107707252A
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- Prior art keywords
- fpga
- signal
- phase amplification
- processing apparatus
- multiplication factor
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- 230000003321 amplification Effects 0.000 title claims abstract description 21
- 238000003199 nucleic acid amplification method Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000010363 phase shift Effects 0.000 claims description 5
- 238000001914 filtration Methods 0.000 claims description 3
- 238000010276 construction Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/36—Indexing scheme relating to amplifiers the amplifier comprising means for increasing the bandwidth
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Superheterodyne Receivers (AREA)
Abstract
The invention discloses a kind of FPGA lock phase amplification systems and method, signal receiving device, ADC signal converter, FPGA signal processing apparatus and FIR filter, the signal receiving device, ADC signal converter, FPGA signal processing apparatus and FIR filter link successively.Provide a kind of FPGA lock phase amplification system and method described in described the invention, its is simple in construction, is substantially reduced PCB sizes, can single fpga chip substitute most of circuit in one piece of receiver board；Reduce hardware cost, each passage consistency is good and affected by environment small.
Description
Technical field
The invention is related to field of signal processing, more particularly to a kind of FPGA lock phase amplification systems and method.
Background technology
Relative to other method for detecting weak signals, lock-in amplifier has higher stability and flexibility.Lock phase
Amplifier extracts signal using the correlation of signal, correlation detection can compression bandwidth to greatest extent, suppress noise.Pass
The lock-in amplifier of system is realized using analog component, but can so introduce more noises.At present, digital lock-in amplifier
More and more applied.
Current lock phase amplification system is mutually put device, low pass filter, subcarrier selector etc. by a simulation lock and formed,
It is with high costs, easily it is affected by temperature, pcb board area is big, each passage global consistency caused by device uniformity differs
It is poor, certain deviation is had to final data.
The content of the invention
For above-mentioned weak point of the prior art, the purpose of the invention is that providing a kind of FPGA locks mutually amplifies
System and method, PCB sizes are substantially reduced for providing, can single fpga chip substitute most of electricity in one piece of receiver board
Road；Reduce hardware cost；Each passage consistency is good and small FPGA locks phase amplification system affected by environment.
The above-mentioned purpose of the invention is achieved by the following technical programs.
A kind of FPGA lock phase amplification systems and method, including：Signal receiving device, ADC signal converter, at FPGA signals
Manage device and FIR filter, the signal receiving device, ADC signal converter, FPGA signal processing apparatus and FIR filter
Link successively.
Preferably, in addition to DDS frequency synthesizers, the DDS frequency synthesizers are connected with FPGA signal processing apparatus.
Preferably, in addition to signal selector, the signal selector point than with DDS frequency synthesizers and FPGA signals
Manage device connection.
Present invention also offers a kind of FPGA to lock phase amplification method, it is characterised in that including：
S1a. the signal of reception is subjected to ADC and is converted into data signal；
S1b. the multiplication factor of two 90 degree of phase shifts is produced；
S2. data signal is subjected to multiplying respectively according to two multiplication factors；
S3. two data signals after progress multiplying are filtered.
S4. the data signal after two filtering is subjected to vector summation.
Preferably, the multiplication factor is produced by DDS frequency synthesizers, and the multiplication factor is the signal frequency with reception
Identical carrier wave.
Preferably, the vector sum formula is：Vector=X and y is respectively two after multiplying
Individual data signal.
Preferably, it is described to be screened with signal frequency identical multiplication factor that is receiving by signal selector.
Compared with prior art, the beneficial effect for the technical scheme that the invention provides is：Its is simple in construction, significantly
Reduce PCB sizes, can single fpga chip substitute most of circuit in one piece of receiver board；Reduce hardware cost；, each passage
Uniformity is good and affected by environment small.
Brief description of the drawings
Fig. 1 is the structural representation that a kind of FPGA of the invention locks phase amplification system.
Fig. 2 is the method flow schematic diagram that a kind of FPGA of the invention locks phase amplification method
Embodiment
With reference to embodiments and the invention is described in detail accompanying drawing.Wherein, being given for example only property of accompanying drawing
Illustrate, expression is only schematic diagram, rather than pictorial diagram, it is impossible to is interpreted as the limitation to this patent；In order to which this hair is better described
The embodiment of bright creation, some parts of accompanying drawing have omission, zoomed in or out, and do not represent the size of actual product；To ability
For field technique personnel, some known features and its explanation may be omitted and will be understood by accompanying drawing.
Present embodiment provides a kind of FPGA lock phase amplification systems and method, as shown in figure 1, including：Signal receives
Device, ADC signal converter, FPGA signal processing apparatus and FIR filter, the signal receiving device, ADC signal conversion
Device, FPGA signal processing apparatus and FIR filter link successively.
Also include DDS frequency synthesizers, the DDS frequency synthesizers are connected with FPGA signal processing apparatus.
Also include signal selector, the signal selector point ratio and DDS frequency synthesizers and FPGA signal processing apparatus
Connection.
A kind of FPGA locks phase amplification method is additionally provided, as shown in Fig. 2 including：
S1a. the signal of reception is subjected to ADC and is converted into data signal；
S1b. the multiplication factor of two 90 degree of phase shifts is produced；
S2. data signal is subjected to multiplying respectively according to two multiplication factors；
S3. two data signals after progress multiplying are filtered.
S4. the data signal after two filtering is subjected to vector summation.
The multiplication factor is produced by DDS frequency synthesizers, and the multiplication factor is the signal frequency identical with reception
Carrier wave.
The vector sum formula is：X and y is respectively two numeral letters after multiplying
Number.
It is described to be screened with signal frequency identical multiplication factor that is receiving by signal selector.
The signal of reception is converted into data signal through ADC, and multiplying is carried out into FPGA；Multiplication factor is DDS module
Produce, caused signal is the signal frequency identical carrier wave with reception；Again through FIR filter, the processing of signal all the way is realized.
Multichannel useful signal and noise, digital multiplier of the noise through FPGA signal processing apparatus are mixed with the signal of reception
After can be filtered out by FIR；And multichannel useful signal is the modulating wave for being modulated into different frequency, thus relative unlike signal is carried out
Separation need to select different frequency carrier wave to make multiplication factor, and signal selector is to play the purpose of the desired useful signal of separation.
In whole process, due to not to phase shifter；Due to signal, caused phase shift can influence finally in external path
The amplitude of output.Thus, when DDS produces carrier wave, incidentally produce a carrier wave with 90 degree of frequency and phase shift go to make it is same
The multiplication factor of signal.Vector by 0 degree with 90 degree of two paths of signals again.
When providing a kind of FPGA lock phase amplification systems and method described in the invention, its is simple in construction, can pass through
Reception signal is carried out separating processing with sending signal, signal is subjected to layered shaping, substantially increases conversion speed.
Obviously, above-described embodiment of the invention is used for the purpose of clearly demonstrating the invention example,
And it is not the restriction to the embodiment of the invention.For those of ordinary skill in the field, stated upper
It can also be made other changes in different forms on the basis of bright, there is no need and unable to give all embodiments
With exhaustion.All all any modification, equivalent and improvement made within the spirit and spirit of the invention etc., all should
Within the invention scope of the claims.
Claims (7)
1. a kind of FPGA locks phase amplification system, it is characterised in that including：Signal receiving device, ADC signal converter, FPGA letters
Number processing unit and FIR filter, the signal receiving device, ADC signal converter, FPGA signal processing apparatus and FIR filters
Ripple device links successively.
A kind of 2. FPGA lock phase amplification system according to claim 1, it is characterised in that also including DDS frequency synthesizers,
The DDS frequency synthesizers are connected with FPGA signal processing apparatus.
3. a kind of FPGA locks phase amplification system according to claim 1, it is characterised in that also including signal selector, institute
Signal selector point ratio is stated to be connected with DDS frequency synthesizers and FPGA signal processing apparatus.
4. a kind of FPGA locks phase amplification method, it is characterised in that including：
S1a. the signal of reception is subjected to ADC and is converted into data signal；
S1b. the multiplication factor of two 90 degree of phase shifts is produced；
S2. data signal is subjected to multiplying respectively according to two multiplication factors；
S3. two data signals after progress multiplying are filtered.
S4. the data signal after two filtering is subjected to vector summation.
5. a kind of FPGA locks phase amplification method according to claim 3, it is characterised in that the multiplication factor is by DDS frequencies
Rate synthesizer produces, and the multiplication factor is the signal frequency identical carrier wave with reception.
6. a kind of FPGA lock phase amplification method according to claim 3, it is characterised in that the vector sum formula is：X and y is respectively two data signals after multiplying.
A kind of 7. FPGA locks phase amplification method according to claim 5, it is characterised in that the signal frequency with receiving
Identical multiplication factor is screened by signal selector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710939573.4A CN107707252A (en) | 2017-09-30 | 2017-09-30 | A kind of FPGA lock phase amplification systems and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710939573.4A CN107707252A (en) | 2017-09-30 | 2017-09-30 | A kind of FPGA lock phase amplification systems and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107707252A true CN107707252A (en) | 2018-02-16 |
Family
ID=61183407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710939573.4A Pending CN107707252A (en) | 2017-09-30 | 2017-09-30 | A kind of FPGA lock phase amplification systems and method |
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| Country | Link |
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| CN (1) | CN107707252A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102124649A (en) * | 2008-08-18 | 2011-07-13 | 日本电信电话株式会社 | Vector synthesis type phase shifter, optical transceiver, and control circuit correction |
| CN103580719A (en) * | 2012-08-06 | 2014-02-12 | 上海航天测控通信研究所 | Full-digital intermediate-frequency despreading demodulation receiver |
| CN104635576A (en) * | 2015-01-07 | 2015-05-20 | 成都九洲迪飞科技有限责任公司 | Transmission pulse upper and lower edge control system |
| CN105553471A (en) * | 2015-12-15 | 2016-05-04 | 成都九洲迪飞科技有限责任公司 | High-sensitivity digital phase-locked loop |
| CN106291105A (en) * | 2016-09-12 | 2017-01-04 | 电子科技大学 | A kind of sweep generator based on digital zero intermediate frequency |
-
2017
- 2017-09-30 CN CN201710939573.4A patent/CN107707252A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102124649A (en) * | 2008-08-18 | 2011-07-13 | 日本电信电话株式会社 | Vector synthesis type phase shifter, optical transceiver, and control circuit correction |
| CN103580719A (en) * | 2012-08-06 | 2014-02-12 | 上海航天测控通信研究所 | Full-digital intermediate-frequency despreading demodulation receiver |
| CN104635576A (en) * | 2015-01-07 | 2015-05-20 | 成都九洲迪飞科技有限责任公司 | Transmission pulse upper and lower edge control system |
| CN105553471A (en) * | 2015-12-15 | 2016-05-04 | 成都九洲迪飞科技有限责任公司 | High-sensitivity digital phase-locked loop |
| CN106291105A (en) * | 2016-09-12 | 2017-01-04 | 电子科技大学 | A kind of sweep generator based on digital zero intermediate frequency |
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Application publication date: 20180216 |
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