CN107707217B - high-dB-gain broadband variable-transconductance six-bit active phase shifter - Google Patents
high-dB-gain broadband variable-transconductance six-bit active phase shifter Download PDFInfo
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Abstract
The invention discloses a high-dB-gain broadband variable transconductance six-bit active phase shifter, which mainly solves the problem of larger mirror image current error in the conventional phase shifter. The system comprises a single-turn double balun, a quadrature signal generator, an analog adder, a buffer and a control circuit. After the radio frequency signal enters the active balun circuit, the single-end radio frequency signal is converted into a differential signal with opposite phase and same amplitude, and the overall gain of the circuit is improved. After the differential signals pass through a triple-pole orthogonal signal generator, four orthogonal signals with the same amplitude are generated to serve as the input of the analog adder, under the action of a controller, a cluster of signals with equal phase shift are synthesized in an orthogonal vector synthesis mode, and the output signals of the phase shifter are obtained through the action of a buffer. The invention not only improves the phase precision, but also reduces the gain attenuation of the passive module, avoids applying bias current by using a digital-to-analog conversion circuit, reduces the power consumption of the circuit and can be used in a radio frequency integrated circuit.
Description
The invention belongs to the technical field of electronic devices, and particularly relates to a six-bit active phase shifter in a frequency range of 3 to 8GHz, which can be used in radio frequency integrated circuits such as radio frequency microwave phased array receivers and the like which need high-precision phase shifters.
Background
Early phased array technologies utilized the concept of hybrid design to develop and study, including transistors, single-machine phase shifters, and the like. With the development of solid-state semiconductor integrated circuit technology, some control electronics have used a form in which group III-V compound semiconductors, such as GaAs, GaN, or InP, are integrated on a single chip. While typical analog components are implemented using III-V technology, silicon-based DSPs can be assembled with printed circuit boards, similar to commercial PC board structures.
While III-V technology provides high Q passive devices and low loss, high isolation switches, this comes at the expense of cost and chip area. In addition, significant breakthroughs in some areas of silicon technology have reduced the cost of phased array technology to some extent, and particularly silicon germanium materials have proven to have properties comparable to III-V materials for low power electronics up to the millimeter wave frequency range. Therefore, in the current state of the art, silicon germanium material is mainly used for the implementation of related circuits.
Based on the silicon germanium process condition, in the phased array transceiver, the types of the phase shifters mainly include a loading line type phase shifter, a reflection type phase shifter, a switch line type phase shifter, a high-pass low-pass phase shifter, a vector modulation phase shifter and the like. Among them, a passive phase shifter using a switching transmission line, a 90-degree hybrid coupling line, and a periodic load line has been developed. However, their physical size in commercial IC operations prevents them from being integrated on multiple arrays. To address this problem, the physical size of the phase shifter can be reduced using a distributed network to lumped element parametric transition synthesis topology. However, in broadband operation, the chip size requirements have not been met due to the rapid growth in size of lumped passive networks, mainly due to the use of various on-chip inductances. Therefore, it is not suitable for an integrated phased array system on a chip. Compared with a passive design, the active phase shifter can obtain higher integration level through good digital phase control under the action of a driving load.
As shown in fig. 1, the active phase shifter generally adopts a reference current as a current of a path through a DAC mirror image of a digital-to-analog conversion circuit to a MOS transistor of an analog adder, and further derives a corresponding phase size through a relationship between a current in the circuit and a gain by a root sign. The active phase shifter has the disadvantages that the size change among the transistors is large, the corresponding transistors cannot be completely ensured to work in a proper area, and meanwhile, errors among the mirror image currents can also have certain influence on the phase.
Disclosure of Invention
The invention aims to provide a high-dB-gain broadband variable transconductance six-bit active phase shifter aiming at the defects of the existing active phase shifter, so that the size of a transistor in the active phase shifter is fixed, the error of a mirror current is reduced, and the phase precision is improved.
In order to achieve the above object, the present invention provides a high dB gain broadband variable transconductance six-bit active phase shifter, comprising: the single-conversion double-balun, the orthogonal signal generator, the analog adder, the buffer and the controller are sequentially connected, and the controller is connected with the analog adder and is characterized in that:
the analog adder adopts a cascode circuit, and the gain of the circuit is changed in an equivalent manner by changing the grid voltage, so that a signal with continuous amplitude and flat phase is output;
the controller adopts the bias voltage generated by the variable resistance circuit to directly act on the transistor grid in the analog adder, and generates radio frequency signals with equal phase shift from the output port of the analog adder.
Preferably, the cascode circuit includes: the active inductor comprises an active inductor, four groups of NMOS transistors and four paths of analog switches, wherein two ends of the active inductor are respectively connected with one end of the four paths of analog switches and a power supply voltage VDD, the other ends of the four paths of analog switches are respectively connected with output ports of the four groups of NMOS transistors, and the other ends of the four groups of NMOS transistors are connected to a ground GND;
preferably, the single-turn double balun includes: the active inductor, the PMOS current mirror, the differential module, the bias resistor, the filter capacitor and the bypass capacitor, wherein two ends of the active inductor are respectively connected with an output port of the differential module and a power supply voltage VDD, two ends of the PMOS current mirror are respectively connected with an output port of the differential module and the power supply voltage VDD, two ends of the bias resistor are respectively connected with a control port of the differential module and the bias voltage, two ends of the filter capacitor are respectively connected with an input port of the differential module and a radio frequency input signal, and two ends of the bypass capacitor are respectively connected with one end of the bias resistor and a ground GND;
preferably, the buffer includes: the output port of the amplifying module is connected with one end of the load resistor, the other end of the load resistor is connected with a power supply voltage VDD, two ends of the bias resistor are respectively connected with a control port and a bias voltage of the amplifying module, two ends of the bypass capacitor are respectively connected with one end of the bias resistor and the power supply voltage VDD, two ends of the filter capacitor are respectively connected with the output port and a radio frequency output signal of the amplifying module, and two ends of the NPN triode current mirror are respectively connected with a current mirror image port of the amplifying module and a ground GND;
preferably, the variable resistance circuit includes: two low-resistance resistors with the resistance value of 1-5K and two high-resistance resistors with the resistance value of more than 5K;
preferably, the orthogonal signal generator includes: and two ends of the first-stage orthogonal module are respectively connected with an input port of the second-stage orthogonal module and a radio frequency input signal, and the other end of the second-stage orthogonal module is connected with an input port of the analog adder.
The invention has the following advantages:
1) according to the invention, the cascode circuit is adopted, and the grid voltage is directly changed, so that the gain of the circuit is equivalently changed, signals with continuous amplitude and flat phase are output, the current mirror error in the traditional analog adder is avoided, and the output phase precision is improved.
2) The variable resistance circuit is adopted, the generated bias voltage is directly acted on the grid electrode of the transistor in the analog adder, and then the radio frequency signal with equal phase shift is generated from the output port of the analog adder, so that the digital-to-analog conversion circuit with larger transistor size in the traditional phase shifter is avoided, the power consumption of the whole circuit is reduced, and the phase precision is ensured.
Drawings
FIG. 1 is an analog summer circuit in a conventional active phase shifter;
FIG. 2 is a block diagram of the overall structure of the present invention;
FIG. 3 is a circuit diagram of a triple-pole quadrature signal generator according to the present invention;
FIG. 4 is a circuit diagram of an analog adder according to the present invention;
FIG. 5 is a circuit diagram of a single-turn dual-active balun circuit in accordance with the present invention;
FIG. 6 is a circuit diagram of a buffer with a differential structure according to the present invention;
fig. 7 is a graph of a simulation using the present invention to produce 16 phase states between 0 and 90 degrees.
Detailed Description
The example takes a broadband variable transconductance six-bit active phase shifter with high dB gain in the range of 3 to 8GHz as an example.
Referring to fig. 2, the active phase shifter of this example includes a single-to-double balun, a quadrature signal generator, an analog adder, a buffer, and a controller, the single-to-double balun, the quadrature signal generator, the analog adder are sequentially connected to the buffer, and the controller is connected to the analog adder; after the radio frequency signal enters the single-conversion double-balun, the radio frequency signal input by the single end is converted into a pair of differential signals with opposite phases and the same amplitude; after the differential signal passes through the orthogonal signal generator, four orthogonal signals with the same amplitude and the same phase distance of 90 degrees are generated and serve as the input of the next-stage analog adder; in the analog adder, a cluster of signals with equal phase shift is generated in a vector synthesis mode; and finally, obtaining an output signal of the phase shifter under the action of the buffer.
Referring to fig. 3, the quadrature signal generator in this example includes two stages of quadrature modules; the first-stage quadrature module is used for generating two poles in a frequency band and comprises four capacitors C1, C2, C3 and C4 and four resistors R1, R2, R3 and R4, and the second-stage quadrature module is used for generating one pole in the frequency band and comprises four capacitors C5, C6, C7 and C8 and four resistors R5, R6, R7 and R8, and the connection relations are as follows:
two ends of a first resistor R1 are respectively connected with an output end of a first capacitor C1 and an input end of a second capacitor C2, two ends of a second resistor R2 are respectively connected with an output end of the second capacitor C2 and an input end of a third capacitor C3, two ends of a third resistor R3 are respectively connected with an output end of the third capacitor C3 and an input end of a fourth capacitor C4, and two ends of a fourth resistor R4 are respectively connected with an output end of the fourth capacitor C4 and an input end of the first capacitor C1; the output end of the first resistor R1 is connected with the output end of the first capacitor C1, the input end of the fifth resistor R5 and the input end of the fifth capacitor C5; the output end of the second resistor R2 is connected with the output end of the second capacitor C2, the input end of the seventh resistor R7 and the input end of the seventh capacitor C7; the output end of the third resistor R3 is connected with the output end of the third capacitor C3, the input end of the sixth resistor R6 and the input end of the sixth capacitor C6; the output end of the fourth resistor R4 is connected with the output end of the fourth capacitor C4, the input end of the eighth resistor R8 and the input end of the eighth capacitor C8; two ends of a fifth capacitor C5 are respectively connected with the output end of the first capacitor C1 and the second positive output end QOUT + of the second-stage orthogonal module, two ends of a sixth capacitor C6 are respectively connected with the output end of the third capacitor C3 and the first negative output end IOUT + of the second-stage orthogonal module, two ends of a seventh capacitor C7 are respectively connected with the output end of the second capacitor C2 and the second negative output end QOUT + of the second-stage orthogonal module, and two ends of an eighth capacitor C8 are respectively connected with the output end of the fourth capacitor C4 and the first positive output end IOUT + of the second-stage orthogonal module.
In the first-stage orthogonal module, because two poles are generated, the resistance capacitance values of the top two paths and the bottom two paths of the first-stage orthogonal module are different. Firstly, formulas of voltage V1 and V3 at the output end of the first-stage orthogonal module are derived, and then the formulas of the voltage V1 and the voltage V3 are subjected to quotient to obtain an output function H(s) which is as follows:
wherein Ra represents the resistance of the first resistor R1 and the second resistor R2, Rb represents the resistance of the third resistor R3 and the fourth resistor R4, Ca represents the capacitance of the first capacitor C1 and the second capacitor C2, and Cb represents the capacitance of the third capacitor C3 and the fourth capacitor C4.
Suppose R in the formulaaCa＜RbCbWhen the condition 8R is satisfiedaCa＝RbCbThen, the two calculated pole frequencies are 1/2R respectivelyaCaAnd 1/4RaCa。
In the second-stage orthogonal module, the pole frequency is approximately close to 1/2 pi RC, the value of the resistor R is fixed to be 100 ohms, and then the value of the capacitor C is determined; finally, the value of the capacitor or the resistor is adjusted near the fixed pole, and the pole direction which can increase the orthogonality of the radio frequency signal is found out.
The first-stage orthogonal module of the orthogonal signal generator is provided with two poles 4GHZ and 7GHZ, the second-stage orthogonal module is provided with one pole 5GHZ, the relative error of the phase is within 0.5 degree, the attenuation of the gain S21 is small, and the reduction can be ignored.
Referring to fig. 4, the analog adder in this example includes an active inductor, four sets of NMOS transistors, four analog switches, and a variable resistance circuit. Wherein:
the first active inductor is used as a load port in the analog adder and comprises a first active inductor resistor R9 and a single-ended triode N1, wherein two ends of the resistor R9 are respectively connected with the base of the single-ended triode N1 and a power supply voltage VDD;
four groups of NMOS transistors are used for amplifying the signal amplitude in the analog adder, the four groups of NMOS transistors comprise eight NMOS transistors M1, M2, M3, M4, M5, M6, M7 and M8, the drain electrode of the first transistor M1 is connected with the source electrode of the fifth transistor M5; the drain of the second transistor M2 is connected to the source of the sixth transistor M6; the drain of the third transistor M3 is connected to the source of the seventh transistor M7; the drain of the fourth transistor M4 is connected to the source of the eighth transistor M8, and the sources of the four transistors M1, M2, M3 and M4 are grounded; the gates of the fifth transistor M5 and the sixth transistor M6 are connected; the seventh transistor M7 is connected to the gate of the eighth transistor M8;
the four-way analog switch is used for controlling the on-off of signals in the analog adder and comprises four switches SI, SIN, SQ and SQN, the polarity of the first switch SI is opposite to that of the second switch SIN, and two ends of the first switch SI are respectively connected with the drain electrode of the fifth transistor M5 and the emitting electrode of the triode N1; two ends of the second switch SIN are respectively connected with the drain of the sixth transistor M6 and the emitter of the triode N1; the polarity of the third switch SQ is opposite to that of the fourth switch SQN, and two ends of the third switch SQ are respectively connected with the drain electrode of the seventh transistor M7 and the emitting electrode of the triode N1; the two ends of the fourth switch SQN are respectively connected to the drain of the eighth transistor M8 and the emitter of the transistor N1.
The variable resistance circuit is used for controlling the grid voltage of an output transistor in the analog adder and comprises two low-resistance resistors with the resistance value of 1-5K and two high-resistance resistors with the resistance value of more than 5K;
the low-resistance resistor is used as an input resistor in the variable resistor circuit and comprises two resistors R10 and R12;
the high-resistance resistor is used as an output resistor in the variable resistor circuit and comprises two resistors R11 and R13;
one end of the first input resistor R10 is connected with one end of the second output resistor R11, the other end of the first input resistor R10 is connected with the power supply voltage VDD, and the other end of the second output resistor R11 is grounded GND;
one end of the third input resistor R12 is connected to one end of the fourth output resistor R13, the other end of the third input resistor R12 is connected to the power supply voltage VDD, and the other end of the fourth output resistor R13 is grounded GND.
Analyzing a single cascode circuit in an analog adder, taking into account a small-signal resistance ro1And ro2The overall transconductance gm and the voltage gain | Av | of the circuit are derived as:
|Av|＝gm1ro1[(gm2+gmb2)ro2+1] <3>
wherein gm1 represents the transconductance of the input transistor, gm2 represents the transconductance of the common-gate transistor, gmb2 represents the transconductance generated by the body effect, and ro1Representing the small signal resistance of the input transistor, ro2Representing the small signal resistance of the common-gate tube.
As can be seen from the formulas <2> and <3>, the gain | Av | of the circuit is related to the transconductance gm1 of the input transistor and the transconductance gm2 of the common-gate transistor, and the overall gain of the circuit can be changed by controlling the magnitudes of the transconductors gm1 and gm2 of the two transistors, so that the single-ended output signal and other amplitudes are changed, and finally the signals with the same phase are synthesized.
The analog adder adopts NFET radio frequency tubes to form a cascade structure, bias voltage generated by a variable resistor is used for controlling grid voltage Va and grid voltage Vb of the cascade tubes, the variation range of the voltage Va and the voltage Vb is 0.7-3.1V, the variation interval of Va is about 0.3V, the variation interval of Vb is about 0.5V, and 16 phase state curves with better linearity between 0 degree and 90 degrees are obtained after some nonlinear phase states are removed.
Referring to fig. 5, the single-to-double balun in this example includes an active inductor, a PMOS current mirror, a differential module, a bias resistor, a filter capacitor, and a bypass capacitor;
the second active inductor is used as a load port in a single-to-double balun and comprises two second active inductor load resistors R14 and R15 and two load triodes N2 and N3, wherein two ends of the first load resistor R14 are respectively connected with the base of the first load triode N2 and the power supply voltage VDD, and two ends of the second load resistor R15 are respectively connected with the base of the second load triode N3 and the power supply voltage VDD;
the PMOS current mirror is used for generating bias current in a single-to-double balun and comprises three PMOS mirror image transistors M9, M10 and M11, the grids of the three transistors M9, M10 and M11 are connected, the sources of the three transistors are all connected to a power supply voltage VDD, the grid and the drain of a first mirror image transistor M9 are connected, the drain end of a second mirror image transistor M10 is connected with the emitter of a second load triode N3, and the drain end of a third mirror image transistor M11 is connected with the emitter of a first load triode N2;
the differential module is used for improving the gain of signals in the single-to-double balun and comprises four differential triodes N4, N5, N6 and N7, wherein a collector of the first differential triode N4 is connected with an emitter of a triode N2, a base of a first differential triode N4 is connected with a base of a triode N5, an emitter of the first differential triode N4 is connected with a collector of a triode N6, a base of a third differential triode N6 is connected with one end of a capacitor C9, an emitter of the third differential triode N6 is connected with a collector of a triode N9, a collector of the second differential triode N5 is connected with an emitter of a triode N3, an emitter of the second differential triode N5 is connected with a collector of a triode N7, a base of a fourth triode N7 is connected with one end of a capacitor C11, and an emitter of a fourth differential triode N7 is connected with a collector of a triode N9;
the bias resistor is used for generating direct-current bias voltage in a single-conversion double-balun and comprises three bias resistors R16, R17 and R18, two ends of a first bias resistor R16 are respectively connected to a base electrode of a triode N4 and bias voltage Vc, two ends of a second bias resistor R17 are respectively connected to a base electrode of a triode N6 and bias voltage Vbias, and two ends of a third bias resistor R18 are respectively connected to the base electrode of the triode N7 and the bias voltage Vbias;
the filter capacitor is used for filtering signals at an output end in a single-to-double balun and comprises a capacitor C9, and two ends of a ninth capacitor C9 are respectively connected with a radio frequency input end RF _ in and a base electrode of a triode N6;
the bypass capacitor is used for stabilizing direct current bias in the single-turn double-balun and comprises three capacitors C10, C11 and C12, two ends of the first bypass capacitor C10 are respectively connected with a bias voltage Vbias and ground GND, two ends of the second bypass capacitor C11 are respectively connected with a base of the triode N7 and the ground GND, and two ends of the third bypass capacitor C12 are respectively connected with the base of the triode N5 and the ground GND.
Referring to fig. 6, the buffer in this example includes an amplifying module, a load resistor, a bias resistor, a bypass capacitor, a filter capacitor, and an NPN triode current mirror;
the amplifying module is used for improving the gain of radio-frequency signals in the buffer and comprises four amplifying triodes N14, N15, N16 and N17, emitting electrodes of a first amplifying triode N14 and a second amplifying triode N15 are respectively connected with collecting electrodes of a third amplifying triode N16 and a fourth amplifying triode N17, bases of the first amplifying triode N14 and a second amplifying triode N15 are connected, a collecting electrode of the first amplifying triode N14 is connected with one end of a resistor R19, a collecting electrode of the second amplifying triode N15 is connected with one end of a resistor R21, emitting electrodes of the third amplifying triode N16 and a fourth amplifying triode N17 are connected with a collecting electrode of a second mirroring triode N20, a base electrode of the third amplifying triode N16 is connected with an input positive port, and a base electrode of the fourth amplifying triode N17 is connected with an input negative port Vin-;
the load resistor is used as a load port in the buffer and comprises two resistors R19 and R21, two ends of the resistor R19 are respectively connected with a collector of the triode N14 and the power supply voltage VDD, and two ends of the resistor R21 are respectively connected with a collector of the second amplification type triode N15 and the power supply voltage VDD;
the bias resistor is used for generating direct-current bias voltage in the buffer and comprises two resistors R20 and R22, two ends of the resistor R20 are respectively connected with the base of the triode N15 and the power voltage VDD, and two ends of the resistor R22 are respectively connected with the base of the second amplification type triode N15 and the ground GND;
the bypass capacitor is used for stabilizing direct current bias in the buffer and comprises a capacitor C14, and two ends of the capacitor C14 are respectively connected with the base electrode of the second amplifying type triode N15 and the power supply voltage VDD;
the filter capacitor is used for filtering signals at the output end of the buffer and comprises a capacitor C15, and two ends of the capacitor C15 are respectively connected with an emitter of the emitter transistor N18 and an output port RF _ OUT;
the NPN triode current mirror is used for generating bias current in the buffer and comprises three NPN mirror image triodes N19, N20 and N21, bases of the three mirror image triodes N19, N20 and N21 are connected, an emitter electrode is connected to the ground GND, a collector electrode of a first NPN 19 mirror image triode is connected with the current mirror input port Ic3, a collector electrode of a second NPN mirror image triode N20 is connected with an emitter electrode of a triode N16, and a collector electrode of a third NPN mirror image triode N21 is connected with an emitter electrode of a triode N18.
The simulation experiment of the present invention is further explained:
first, experimental conditions
In the experiment, the power voltage VDD is 3.3V, the ground GND is 0V, the mirror currents Ic1 and Ic2 of the single-to-double balun and the mirror current Ic3 in the buffer are all 1mA, the resistance value change ranges of the low-resistance resistors R10 and R12 in the variable resistor circuit are between 1K and 5K, the resistance value change ranges of the high-resistance resistors R11 and R13 are between 5K and 8K, the change ranges of the generated bias voltages Va and Vb are between 0.7V and 3.1V, the MOS transistors in the cascode circuit all use NMOS transistors, the transistors in the active inductor, the amplifying module and the differential module all use NPN transistors, the capacitance values of the filter capacitor and the bypass capacitor are both 2PF, and the resistance value of the bias resistor is 5K.
Second, simulation experiment
In the experiment, cadence software is used, a phase shifter circuit module is built under an ADE simulation platform based on a 0.18um BiCMOS process, then whole circuit simulation is carried out, and finally the performance of the phase shifter is reflected through a phase curve graph.
Firstly, building a module symbol for the built single-turn double balun, the orthogonal signal generator, the analog adder, the buffer and the controller respectively, then sequentially connecting the modular single-turn double balun, the orthogonal signal generator, the analog adder and the buffer, and connecting the controller and the analog adder to complete the building of the simulation circuit.
Next, simulation parameters are set on an ADE simulation platform, wherein the frequency range of radio frequency signals is 3 to 8GHZ, the amplitude of the signals is 10mV, the center frequency point is 5GHZ, the number of linear stepping points of each simulation curve is 50, after the above parameters are set, circuit simulation is performed on the ADE platform, and a generated phase curve is tested on an output port of the phase shifter, as shown in fig. 7.
Fig. 7 shows 16 better-linearity phase state curves of the phase shifter output end between 0 and 90 degrees, the vertical axis shows the magnitude of the phase shifter output, and the horizontal axis shows the frequency range of the phase shifter, which can be obtained from the simulation result of fig. 7: in the frequency range of 3 to 8GHZ, the phase error of the phase shifter is within 4.6 degrees, and the design requirement is met.
Claims (7)
1. A high-dB gain broadband variable transconductance six-bit active phase shifter comprises: the single-conversion double-balun, the orthogonal signal generator, the analog adder, the buffer and the controller are sequentially connected, and the controller is connected with the analog adder and is characterized in that:
the analog adder adopts a cascode circuit, and the gain of the circuit is changed in an equivalent manner by changing the grid voltage, so that a signal with continuous amplitude and flat phase is output; the cascode circuit includes: the power supply comprises a first active inductor, four groups of NMOS transistors and four paths of analog switches, wherein two ends of the active inductor are respectively connected with one end of the four paths of analog switches and a power supply voltage VDD, the other ends of the four paths of analog switches are respectively connected with output ports of the four groups of NMOS transistors, and the other ends of the four groups of NMOS transistors are connected to a ground GND; each group of transistors in the four groups of NMOS transistors consists of a common source NMOS transistor and a common gate NMOS transistor; the grid electrode of the common source NMOS transistor is connected with an input signal, and the drain electrode of the common source NMOS transistor is connected with the common gate NMOS transistor; the grid electrodes of two transistors in the common-grid NMOS transistor are connected and loaded with a first bias voltage Va, and the grid electrodes of the other two transistors are also connected and loaded with a bias voltage Vb;
the controller adopts the bias voltage generated by the variable resistance circuit to directly act on the grid electrode of the common-grid NMOS transistor in the analog adder, and generates radio-frequency signals with equal phase shift from the output port of the analog adder.
2. The active phase shifter of claim 1, wherein the single-turn double balun comprises: the active inductor comprises a second active inductor, a PMOS current mirror, a differential module, a bias resistor, a filter capacitor and a bypass capacitor, wherein two ends of the active inductor are respectively connected with an output port of the differential module and a power supply voltage VDD, two ends of the PMOS current mirror are respectively connected with an output port of the differential module and the power supply voltage VDD, two ends of the bias resistor are respectively connected with a control port of the differential module and the bias voltage, two ends of the filter capacitor are respectively connected with an input port of the differential module and a radio frequency input signal, and two ends of the bypass capacitor are respectively connected with one end of the bias resistor and a ground GND.
3. The active phase shifter of claim 1, wherein the buffer comprises: the output port of the amplifying module is connected with one end of the load resistor, the other end of the load resistor is connected with a power supply voltage VDD, two ends of the bias resistor are respectively connected with a control port and a bias voltage of the amplifying module, two ends of the bypass capacitor are respectively connected with one end of the bias resistor and the power supply voltage VDD, two ends of the filter capacitor are respectively connected with the output port and a radio frequency output signal of the amplifying module, and two ends of the NPN triode current mirror are respectively connected with a current mirror image port and a ground GND of the amplifying module.
4. The active phase shifter of claim 1, wherein the variable resistance circuit comprises: two low-resistance resistors with the resistance value of 1-5K and two high-resistance resistors with the resistance value of more than 5K;
the low-resistance resistor is used as an input resistor in the variable resistor circuit and comprises two resistors R10 and R12;
the high-resistance resistor is used as an output resistor in the variable resistor circuit and comprises two resistors R11 and R13;
one end of the first input resistor R10 is connected with one end of the second output resistor R11, the other end of the first input resistor R10 is connected with the power supply voltage VDD, and the other end of the second output resistor R11 is grounded GND;
one end of the third input resistor R12 is connected to one end of the fourth output resistor R13, the other end of the third input resistor R12 is connected to the power supply voltage VDD, and the other end of the fourth output resistor R13 is grounded GND.
5. Active phase shifter as claimed in claim 1, characterized in that the quadrature signal generator comprises: and two ends of the first-stage orthogonal module are respectively connected with an input port of the second-stage orthogonal module and a radio frequency input signal, and the other end of the second-stage orthogonal module is connected with an input port of the analog adder.
6. The active phase shifter of claim 3, wherein the amplifying module comprises two differential input transistors N16, N17 and two common-base amplifying transistors N14, N15, wherein bases of the two differential input transistors N16 and N17 are respectively connected with an input positive signal Vin + and a negative signal Vin-, emitters of the two differential input transistors are both connected with an output port of the NPN triode current mirror, and collectors of the two differential input transistors are respectively connected with emitters of the common-base amplifying transistors N14 and N15; the bases of the two common-base amplifying tubes N14 and N15 are connected, and the emitter is connected with one end of a load resistor.
7. The active phase shifter of claim 5, wherein the first-stage quadrature block comprises a first pole block and a second pole block, the first pole block has left ends respectively connected to the input positive signal Vin + and the input negative signal Vin-, right ends connected to the input port of the second-stage quadrature block, bottom ends connected to the top port of the second pole block, the second pole block has left ends respectively connected to the input positive signal Vin + and the input negative signal Vin-, and right ends connected to the input port of the second-stage quadrature block.
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| US11183973B1 (en) | 2020-06-02 | 2021-11-23 | Samsung Electronics Co., Ltd | Method and circuit for power consumption reduction in active phase shifters |
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| CN109546987B (en) * | 2018-11-16 | 2021-09-03 | 西安电子科技大学 | Broadband active phase shifter |
| CN111371430B (en) * | 2018-12-26 | 2023-08-08 | 深圳市中兴微电子技术有限公司 | Vector synthesis phase shifter and vector synthesis phase shifting method |
| CN110212887B (en) * | 2019-04-28 | 2020-04-07 | 南京汇君半导体科技有限公司 | Radio frequency active phase shifter structure |
| CN111130503B (en) * | 2020-03-30 | 2020-08-18 | 南京汇君半导体科技有限公司 | Low-phase-difference numerical control radio frequency attenuator |
| CN111510072B (en) * | 2020-05-19 | 2021-09-17 | 成都天锐星通科技有限公司 | High-frequency vector modulation type passive phase shifter |
| CN112787628A (en) * | 2020-12-15 | 2021-05-11 | 西安电子科技大学 | Ultra-wideband reconfigurable active phase shifter |
| CN113328728B (en) * | 2021-06-02 | 2022-09-27 | 南京理工大学 | High-precision active phase shifter based on time-varying vector synthesis |
| CN113452345B (en) * | 2021-06-16 | 2022-06-03 | 电子科技大学 | Broadband active phase shifter based on III-V group compound semiconductor process |
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