CN107689351A - 封装结构 - Google Patents

封装结构 Download PDF

Info

Publication number
CN107689351A
CN107689351A CN201610999383.7A CN201610999383A CN107689351A CN 107689351 A CN107689351 A CN 107689351A CN 201610999383 A CN201610999383 A CN 201610999383A CN 107689351 A CN107689351 A CN 107689351A
Authority
CN
China
Prior art keywords
encapsulation
semiconductor element
molding material
top surface
exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610999383.7A
Other languages
English (en)
Inventor
王垂堂
吴凱强
陈颉彦
王彦评
张守仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107689351A publication Critical patent/CN107689351A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种封装结构，包含封装、至少一第一模制材料与至少一第二半导体元件。封装包含至少一第一半导体元件于其中，封装具有顶表面。第一模制材料位于封装的顶表面，并具有至少一开口于其中。封装的顶表面的至少一区域被第一模制材料的开口所暴露。第二半导体元件位于封装的顶表面，并被第一模制材料所模制。

Description

封装结构
技术领域
本发明实施例是有关于一种封装结构。
背景技术
在半导体工业的领域中，本同的电子部件(例如晶体管、二极管、电阻器及电容器等)的集成密度，都在以不断减少的最小特征尺寸来改善，借此容许在特定范围内可以集成更多的部件。这些较小的电子部件亦需要较小的封装，并在一些应用上比旧式的封装占用更小面积。一些半导体较小的封装款式包括方形扁平式封装(quad flat pack；QFP)、插针网格阵列(pin grid array；PGA)、球栅阵列封装(ball grid array；BGA)、覆晶(flipchips；FC)、三维晶片(three dimensional integrated circuits；3DICs)、晶圆级封装(wafer level packages；WLPs)、连封装(bump-on-trace；BOT)及叠合封装(package onpackage；PoP)结构。
发明内容
根据本揭露多个实施例，一种封装结构包含封装、至少一第一模制材料与至少一第二半导体元件。封装包含至少一第一半导体元件于其中，封装具有顶表面。第一模制材料位于封装的顶表面，并具有至少一开口于其中。封装的顶表面的至少一区域被第一模制材料的开口所暴露。第二半导体元件位于封装的顶表面，并被第一模制材料所模制。
附图说明
当结合所附附图阅读时，以下详细描述将较容易理解本揭露的态样。应注意，根据工业中的标准实务，各特征并非按比例绘制。事实上，出于论述清晰的目的，可任意增加或减小各特征的尺寸。
图1～图19为绘示根据本揭露多个实施例的制造封装结构的中间阶段的剖面示意图；
图20为绘示图19的结构的上视图；
图21～图22为绘示根据本揭露多个实施例的制造封装结构的中间阶段的剖面示意图；
图23为绘示图22的结构的上视图；
图24为绘示根据本揭露多个实施例的封装结构的剖面示意图；
图25为绘示图24的结构的上视图；
图26为绘示根据本揭露多个实施例的封装结构的剖面示意图；
图27为绘示图26的结构的上视图。
具体实施方式
以下揭示内容提供许多不同实施例或实例，以便实施所提供标的的不同特征。下文描述组件及排列的特定实例以简化本揭露。当然，这些实例仅为示例且并不意欲为限制性。举例来说，以下描述中在第二特征上方或第二特征上形成第一特征可包括以直接接触形成第一特征及第二特征的实施例，且亦可包括可在第一特征与第二特征之间形成额外特征以使得第一特征及第二特征可不处于直接接触的实施例。另外，本揭露可在各实例中重复元件符号及/或字母。此重复是出于简明性及清晰的目的，且本身并不指示所论述的各实施例及/或配置之间的关系。
进一步地，为了便于描述，本文可使用空间相对性术语(诸如“之下”、“下方”、“下部”、“上方”、“上部”及类似者)来描述诸图中所绘示一个元件或特征与另一元件(或多个元件)或特征(或多个特征)的关系。除了诸图所描绘的定向外，空间相对性术语意欲包含使用或操作中装置的不同定向。设备可经其他方式定向(旋转90度或处于其他定向)，因此可同样解读本文所使用的空间相对性描述词。
请参照图1～图19，其为绘示根据本揭露多个实施例的制造封装结构的中间阶段的剖面示意图。如图1所示，粘着层A形成于载板C上。载板C可为空白的玻璃载板、空白的陶瓷载板或类似的载板。粘着层A可能以紫外线(Ultra-Violet；UV)胶、光热转换(light-to-heat conversion；LTHC)胶或类似的粘着胶所形成，虽然亦可使用其他类型的粘着胶。
请参照图2。缓冲层110形成于粘着层A上。缓冲层110为介电层，其可能是聚合物层。聚合物层可能包括，举例而言，聚酰亚胺(polyimide)、聚苯并(polybenzoxazole；PBO)、苯并环丁烯(benzocyclobutene；BCB)、环氧树脂膜(ajinomoto buildup film；ABF)或抗焊膜(solder resist film；SR)等。缓冲层110为实质上平坦的阶层，并具有实质上均匀的厚度，其中厚度可能实质上大于2微米，或是范围可能实质上在2微米至40微米之间。在一些实施例中，缓冲层110的顶表面及底表面均实质上平坦。
举例而言，晶种层123通过物理气相沉积(physical vapor deposition；PVD)或金属箔层压形成于缓冲层110上。晶种层123可能包括铜、铜合金、铝、钛、钛合金或以上的任意组合。在一些实施例中，晶种层123包括钛层，以及覆盖于钛层上的铜层。在其他的实施例中，晶种层123为铜层。
请参照图3，光阻剂P被应用于晶种层123上并且被图案化。因此，光阻剂P上形成开口O1。通过开口O1，部分的晶种层123被暴露。
如图4所示，导电特征125以镀的方式形成在光阻剂P上，镀的方式可为电镀或化学镀。导电特征125被镀于晶种层123被暴露的部分上。导电特征125可能包括铜、铝、钨、镍、焊料或以上材料的合金。导电特征125的俯视形状可能为长方形、四方形或圆形等。导电特征125的高度取决于随后放置的第一半导体元件130(请参照图7)的厚度，而在一些实施例中，导电特征125的高度大于第一半导体元件130的厚度。当导电特征125被镀后，光阻剂P将被移除，而所形成的结构显示于图5。当光阻剂P将被移除后，部分的晶种层123被暴露出来。
请参照图6，蚀刻步骤被执行以把晶种层123被暴露的部分移除，其中蚀刻步骤可能包括各向异性蚀刻。另一方面，晶种层123被导电特征125覆盖的部分，则维持没有被蚀刻。在整个描述中，导电特征125以及晶种层123余下位于导电特征125下的部分组合成为直通整合型扇出型穿孔(through integrated fan-out(InFO)vias；TIVs)120，亦称为通孔120。虽然晶种层123被显示为导电特征125以外的一层结构，但是当晶种层123是以相似于或实质上相同于对应于其上的导电特征125的材料所制造时，晶种层123可能与导电特征125合并，且两者之间不具有可分辨的界面。在其他的实施例中，晶种层123与其上的导电特征125之间具有可分辨的界面。
图7绘示出第一半导体元件130被放在缓冲层110上。第一半导体元件130可能被粘着层131粘着于缓冲层110。在一些实施例中，第一半导体元件130为未封装的半导体元件，亦即装置祼晶。举例而言，第一半导体元件130可为包括逻辑晶体管于其中的逻辑装置祼晶。在一些实施例中，第一半导体元件130是为移动的应用而设计，亦可为中央计算单元(central computing unit；CPU)祼晶、能源管理集成电路(power management integratedcircuit；PMIC)祼晶或收发(transceiver；TRX)祼晶等。每个第一半导体元件130包括一个半导体基板132(例如硅基板)，半导体基板132接触粘着层131，其中半导体基板132的背表面与粘着层131接触。
在一些实施例中，导电柱136(例如铜柱)形成为第一半导体元件130的上部分，并电性连接至第一半导体元件130中例如晶体管(图未示)的子装置。在一些实施例中，介电层134形成于对应的第一半导体元件130的顶表面上，而导电柱136于介电层134中具有至少下部分。在一些实施例中，导电柱136的顶表面可能与介电层134的顶表面实质上同平面。另一方面，介电层并没有形成，而导电柱136从对应的第一半导体元件130的顶介电层(图未示)凸出。
请参照图8，模制材料135模制于第一半导体元件130及直通整合型扇出型穿孔120上。模制材料135填充第一半导体元件130与直通整合型扇出型穿孔120之间的间隙，并可能与缓冲层110接触。再者，当导电柱136为凸出金属柱时(图未示此情况)，模制材料135填充导电柱136之间的间隙。模制材料135的顶表面是高于导电柱136及直通整合型扇出型穿孔120的上端。
在一些实施例中，模制材料135包括以聚合物为本的材料。“聚合物”一词，可代表热固性聚合物、热塑性聚合物或以上的任意组合。聚合物为本的材料可包括，举例而言，塑料材料、环氧树脂、聚酰亚胺、聚乙烯对苯二甲酸酯(polyethylene terephthalate；PET)、聚氯乙烯(polyvinyl chloride；PVC)、聚甲基丙烯酸甲酯(polymethylmethacrylate；PMMA)、掺杂有包括纤维、粘土、陶瓷或无机颗粒的填料的聚合物，或以上的任意组合。
随后，研磨步骤被执行以把模制材料135变薄，直至导电柱136与直通整合型扇出型穿孔120被暴露出来，而所形成的结构显示于图9，其中模制材料135接触第一半导体元件130及直通整合型扇出型穿孔120的侧壁。通过研磨，直通整合型扇出型穿孔120的上端与导电柱136的顶端实质上同平面，并与模制材料135的顶表面实质上同平面。研磨可能会产生导电的残留物例如金属颗粒，并留于图9所示结构的顶表面。如此一来，在研磨之后，可能要进行清洁，例如以湿式蚀刻，以使导电的残留物得以清除。
请参照图10，重新分配线(redistribution lines；RDLs)150于模制材料135上形成，以连接导电柱136与直通整合型扇出型穿孔120。重新分配线150亦可把导电柱136及直通整合型扇出型穿孔120相互连接。根据不同的实施例，一个或多个介电层140形成于第一半导体元件130、模制材料135及直通整合型扇出型穿孔120上，而重新分配线150形成于介电层140中。在一些实施例中，一层重新分配线150的形成包括形成毯铜晶种层、于毯铜晶种层上形成一层遮罩层并使其图案化、执行电镀以形成重新分配线150、移除遮罩层以及执行闪光蚀刻以移除毯铜晶种层没有被重新分配线150覆盖的部分。在其他的实施例中，重新分配线150是以沉积金属层、把金属层图案化及填充重新分配线150与介电层140之间的间隙所形成。重新分配线150可能包括金属或金属合金，包括铝、铜、钨及/或其合金。在整个描述中，由缓冲层110、第一半导体元件130、直通整合型扇出型穿孔120、模制材料135、重新分配线150以及介电层140所组合出来的结构，可被称为直通整合型扇出型穿孔封装100，其可为复合晶圆。
图10绘示两层重新分配线150，而根据对应封装的布线设计，其亦可具有一层或多于两层的重新分配线150。在这些实施例中，介电层140可能包括聚合物，例如聚酰亚胺、苯并环丁(benzocyclobutene；BCB)烯或聚苯并恶唑(polybenzoxazole；PBO)等。另一方面，介电层140可能包括无机介电材料，例如氧化硅(silicon oxide)、氮化硅(siliconnitride)、碳化硅(silicon carbide)或氮氧化硅(silicon oxynitride)等。
随后，请参照图11，第二半导体元件200连接至直通整合型扇出型穿孔封装100。第二半导体元件200的外部连接器210结合至重新分配线150的一些暴露的部分。在一些实施例中，第二半导体元件200是为移动的应用而设计，亦可为通讯模块，例如无线网络(Wireless Fidelity；Wi-Fi)的前端模块或第五代(5th Generation；5G)移动网络的前端模块等。在一些实施例中，第二半导体元件200为封装的半导体元件，亦即装置封装。在其他的实施例中，第二半导体元件200为未封装的半导体元件，亦即装置祼晶。在一些实施例中，举例而言，第二半导体元件200的外部连接器210可为应用于第二半导体元件200底部的焊球。
请参照图12，模具组件M已经就位，并举例而言以夹紧的方式压向直通整合型扇出型穿孔封装100及载板C。在一些实施例中，模具组件M包括至少一凸出结构MP，凸出结构MP往下延伸并被压向放置电子部件400(请参照图18)的至少一区域ER。再者，模具组件M的至少一边缘部EP与缓冲层110接触。在一些实施例中，以柔性材料制成的离型膜R，是贴附至模具组件M的内表面。模具组件M可能以不锈钢、陶瓷、铜或铝等制造。如图12所示的实施例，模具组件M为晶圆级，其中第二半导体元件200亦同时被模制。
随后，模制材料300被注射至模具组件M所定义的空间。模制材料300处于液体状态并可流动。模制材料300可能与直通整合型扇出型穿孔封装100的顶表面接触，亦可能与第二半导体元件200的外部连接器210、顶表面、底表面及侧壁接触。模制材料300的顶表面可能高于第二半导体元件200的顶表面，因此，第二半导体元件200有可能被完全地包覆于模制材料300中。然后，虽然其他的固化方式也可被使用，但是模制材料300可在例如热固化过程中被固化。之后，模具组件M则可被拿掉。当模具组件M被拿掉后，所形成的结构显示于图14，其中模制材料300具有至少一开口O2于其中，而区域ER被模制材料300的开口O2所暴露出来。
在一些实施例中，模制材料300包括以聚合物为本的材料。“聚合物”一词，可代表热固性聚合物、热塑性聚合物或以上的任意组合。聚合物为本的材料可包括，举例而言，塑料材料、环氧树脂、聚酰亚胺、聚乙烯对苯二甲酸酯(polyethylene terephthalate；PET)、聚氯乙烯(polyvinyl chloride；PVC)、聚甲基丙烯酸甲酯(polymethylmethacrylate；PMMA)、掺杂有包括纤维、粘土、陶瓷或无机颗粒的填料的聚合物，或以上的任意组合。
在其他的实施例中，如图13所示，在放置模具组件M前，光阻剂DF被应用于直通整合型扇出型穿孔封装100的顶表面，并以光刻处理使其图案化。如此一来，被图案化的光阻剂DF形成于放置电子部件400(请参照图18)的区域ER。在一些实施例中，光阻剂DF，举例而言，可为干膜光阻片。随后，模具组件M被放置好，并举例而言以夹紧的方式压向直通整合型扇出型穿孔封装100及载板C。在图13中所示的一些实施例中，模具组件M可能并不具有延伸并被压向区域ER的凸出结构。随后，模制材料300被注射至模具组件M所定义的空间。然后，虽然其他的固化方式也可被使用，但是模制材料300可在例如热固化过程中被固化。之后，模具组件M则可被拿掉，而光阻剂DF从区域ER被移除。
然后，直通整合型扇出型穿孔封装100从载板C被脱离。粘着层A亦从直通整合型扇出型穿孔封装100被清理掉。由于粘着层A被移除，因此缓冲层110被暴露出来。如图15所示，连接有第二半导体元件200及模制材料300的直通整合型扇出型穿孔封装100被进一步粘附到切割胶带DT，其中模制材料300面向并可能接触切割胶带DT。在一些实施例中，护卡膜(图未示)被放置在暴露出来的缓冲层110上，其中护卡膜可能包括抗焊膜、环氧树脂膜或背面涂布胶带等。在其他的实施例中，并没有护卡膜放置于缓冲层110上。
进一步而言，如图15所示，开口O3形成于缓冲层110及护卡膜中。根据一些实施例，开口O3是以激光钻所形成，虽然亦可使用光刻处理。此时，缓冲层110与模具组件M(请参照图12)的边缘部EP(请参照图12)所接触的部分，在模具组件M(请参照图12)被拿掉前，是被激光钻所移除。直通整合型扇出型穿孔120是分别透过开口O3而被暴露出来。在一些实施例中，当晶种层123包括钛层时，蚀刻步骤被执行以把钛层移除，以使晶种层123的铜层被暴露出来。若晶种层123不包括钛层，蚀刻步骤则被跳过。
随后，如图16所示，电性连接器160形成于直通整合型扇出型穿孔120上。电性连接器160的形成可能包括于直通整合型扇出型穿孔120上放置焊球，以及其后把焊球软熔。在其他的实施例中，电性连接器160的形成可能包括于直通整合型扇出型穿孔120上形成焊膏区域。
随后，如图17所示，切割分离过程被执行以把直通整合型扇出型穿孔封装100、第二半导体元件200及模制材料300的组合锯开而形成多个封装结构101。在一些实施例中，封装结构101可能沿至少一切割分离线102被分开以形成个别的封装结构101。
随后，如图18所示，至少一电子部件400连接至直通整合型扇出型穿孔封装100被模制材料300的开口O2所暴露出来的区域ER，连接至区域ER的电子部件400是设置于模制材料300的开口O2。电子部件400的外部连接器410结合至重新分配线150的一些暴露的部分。在一些实施例中，举例而言，电子部件400为感应器，感应器可为声音感应器或光感应器等。由于电子部件400连接至被模制材料300的开口O2所暴露出来的区域ER，因此电子部件400是位于模制材料300的外部。当电子部件400为声音感应器或光感应器等时，模制材料300阻挡电子部件400所要感应的声音或光的机会将会减少。如此一来，电子部件400的运作效率将得以维持。在一些实施例中，在经过切割分离过程后，电子部件400是连接至直通整合型扇出型穿孔封装100的区域ER。在其他的实施例中，在经过切割分离过程前，电子部件400是连接至直通整合型扇出型穿孔封装100的区域ER。
如图19所示，具有电子部件400的封装结构101是连接至基板500。直通整合型扇出型穿孔封装100的电子连接器160是结合至基板500的一些接合垫510。基板500，举例而言，为印刷电路板。
图20为绘示图19的结构的上视图。如图20所示，被模制材料300的开口O2所暴露出来的区域ER抵接直通整合型扇出型穿孔封装100的顶表面的至少一边缘。在一些实施例中，直通整合型扇出型穿孔封装100的顶表面的至少一角落被模制材料300的开口O2暴露出来。也就是说，被模制材料300的开口O2所暴露出来的区域ER重叠于直通整合型扇出型穿孔封装100的顶表面的角落。而且，电子部件400是放置于区域ER。也就是说，电子部件400是放置于直通整合型扇出型穿孔封装100的顶表面的角落。如此一来，电子部件400是位于模制材料300的外部，因而电子部件400的运作效率将得以维持。在一些实施例中，电子部件400与毗邻电子部件400的第二半导体元件200之间的距离D，实质上大于1毫米。
如图21所示，在一些实施例中，在电子部件400连接至区域ER前，屏蔽涂料600被应用至模制材料300的至少顶表面及侧壁。在一些实施例中，屏蔽涂料600被进一步应用至直通整合型扇出型穿孔封装100的侧壁。屏蔽涂料600为金属，例如不锈钢、含铜金属或含铟金属等。在一些实施例中，屏蔽涂料600是以喷洒的方式被应用。
随后，屏蔽涂料600位于直通整合型扇出型穿孔封装100的区域ER的部分被移除。根据一些实施例，屏蔽涂料600于区域ER被移除的部分是通过激光钻来进行，虽然亦可使用光刻处理。在一些实施例中，举例而言，屏蔽涂料600是通过重新分配线150至少一暴露出来的部分电性接地。当屏蔽涂料600形成后，至少一电子部件400是连接至直通整合型扇出型穿孔封装100的区域ER，而具有第二半导体元件200、模制材料300及电子部件400的直通整合型扇出型穿孔封装100则连接至基板500，所形成的结构显示于第22～23图，其中图23为绘示图22的结构的上视图。
请参照图24～图25，其中图25为绘示图24的结构的上视图。在一些实施例中，模制材料300的开口O2的位置远离直通整合型扇出型穿孔封装100的顶表面的周界。因此，当电子部件400被放置于模制材料300的开口O2时，电子部件400是被模制材料300围绕，而电子部件400是独立于模制材料300。
请参照图26～图27，其中图27为绘示图26的结构的上视图。第26～27图所绘示的实施例与图24～图25所绘示的实施例的差异在于图26～图27所绘示的结构进一步包括屏蔽涂料600。屏蔽涂料600是形成于模制材料300的至少顶表面及侧壁。在一些实施例中，屏蔽涂料600更形成于直通整合型扇出型穿孔封装100的侧壁。相似于图21～图22，举例而言，屏蔽涂料600是通过重新分配线150至少一暴露出来的部分电性接地。
根据本揭露多个实施例，封装结构具有至少一电子部件，且电子部件位于封装结构的模制材料的外部。当电子部件为声音感应器或光感应器等时，模制材料阻挡电子部件所要感应的声音或光的机会将会减少。如此一来，电子部件的运作效率将得以维持。
根据本揭露多个实施例，一种封装结构包含封装、至少一第一模制材料与至少一第二半导体元件。封装包含至少一第一半导体元件于其中，封装具有顶表面。第一模制材料位于封装的顶表面，并具有至少一开口于其中。封装的顶表面的至少一区域被第一模制材料的开口所暴露。第二半导体元件位于封装的顶表面，并被第一模制材料所模制。
在本揭露多个实施例中，上述的封装结构还包含至少一电子部件。此电子部件位于封装的顶表面被暴露的区域。
在本揭露多个实施例中，上述的封装的顶表面的至少一角落被开口所暴露。
在本揭露多个实施例中，上述的封装的顶表面被暴露的区域抵接封装的顶表面的至少一边缘。
在本揭露多个实施例中，上述的封装还包含第二模制材料、至少一介电层与至少一重新分配线。第二模制材料至少接触第一半导体元件的至少一侧壁。介电层位于第一半导体元件及第二模制材料上。重新分配线至少部分位于介电层，并电性连接第一半导体元件。
在本揭露多个实施例中，上述的封装还包含至少一直通整合型扇出型穿孔。此直通整合型扇出型穿孔通过第二模制材料电性连接重新分配线。
在本揭露多个实施例中，上述的第二半导体元件为未封装的半导体元件。
在本揭露多个实施例中，上述的封装结构还包含屏蔽涂料。此屏蔽涂料位于第一模制材料上。
在本揭露多个实施例中，上述的屏蔽涂料进一步位于封装的至少一侧壁。
根据本揭露多个实施例，一种封装结构包含封装、至少一第一模制材料、至少一第二半导体元件与至少一电子部件。封装包含至少一第一半导体元件于其中。第二半导体元件位于封装，并被模制于第一模制材料内。电子部件位于封装，并位于第一模制材料之外。
在本揭露多个实施例中，上述的电子部件被第一模制材料所围绕。
在本揭露多个实施例中，上述的电子部件位于封装的角落。
在本揭露多个实施例中，上述的电子部件为感应器。
在本揭露多个实施例中，上述的第一模制材料具有至少一开口于其中，而电子部件设置于第一模制材料的开口中。
根据本揭露多个实施例，一种封装结构制造方法，包含形成封装；放置至少一半导体元件于封装的顶表面上；模制半导体元件于模制材料内并保留以暴露封装的顶表面的至少一区域；以及放置至少一电子部件于封装的顶表面的被暴露的区域上。
在本揭露多个实施例中，上述的模制半导体元件的步骤包含利用模具以定义模制材料内的至少一开口以暴露封装的表面的区域。
在本揭露多个实施例中，上述的模制半导体元件的步骤包含形成图案薄膜于封装的顶表面的区域上；以及于形成图案薄膜后，模制半导体元件于模制材料内。
在本揭露多个实施例中，上述的形成图案薄膜的步骤包含形成光阻剂于封装的顶表面上；以及以光刻处理使光阻剂图案化。
在本揭露多个实施例中，上述的光阻剂为干膜光阻片。
在本揭露多个实施例中，上述的封装结构制造方法还包含至少于模制材料上形成屏蔽涂料。
尽管参看本揭露的某些实施例已相当详细地描述了本揭露，但其他实施例是可能的。因此，所附权利要求书的精神及范畴不应受限于本文所含实施例的描述。
将对熟悉此项技术者显而易见的是，可在不脱离本揭露的范畴或精神的情况下对本揭露的结构实行各种修改及变化。鉴于上述，本揭露意欲涵盖本揭露的修改及变化，前提是这些修改及变化属于权利要求书的范畴内。
上文概述若干实施例的特征，使得熟悉此项技术者可更好地理解本揭露的态样。熟悉此项技术者应了解，可轻易使用本揭露作为设计或修改其他制程及结构的基础，以便实施本文所介绍的实施例的相同目的及/或实现相同优势。熟悉此项技术者亦应认识到，此类等效结构并未脱离本揭露的精神及范畴，且可在不脱离本揭露的精神及范畴的情况下产生本文的各种变化、替代及更改。

Claims (1)

1.一种封装结构，其特征在于，包含：
一封装包含至少一第一半导体元件于其中，该封装具有一顶表面；
至少一第一模制材料，位于该封装的该顶表面，并具有至少一开口于其中，其中该封装的该顶表面的至少一区域被该第一模制材料的该开口所暴露；以及
至少一第二半导体元件，位于该封装的该顶表面，并被该第一模制材料所模制。
CN201610999383.7A 2016-08-05 2016-11-14 封装结构 Pending CN107689351A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/229,711 US9818722B1 (en) 2016-08-05 2016-08-05 Package structure and method for manufacturing thereof
US15/229,711 2016-08-05

Publications (1)

Publication Number Publication Date
CN107689351A true CN107689351A (zh) 2018-02-13

Family

ID=60255758

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610999383.7A Pending CN107689351A (zh) 2016-08-05 2016-11-14 封装结构

Country Status (3)

Country Link
US (2) US9818722B1 (zh)
CN (1) CN107689351A (zh)
TW (1) TW201806090A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112399791A (zh) * 2019-08-14 2021-02-23 三星电机株式会社 电子组件模块以及包括所述电子组件模块的电子器件

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI649856B (zh) * 2016-05-13 2019-02-01 精材科技股份有限公司 晶片封裝體與其製造方法
US10553542B2 (en) * 2017-01-12 2020-02-04 Amkor Technology, Inc. Semiconductor package with EMI shield and fabricating method thereof
JP2019110201A (ja) * 2017-12-18 2019-07-04 ルネサスエレクトロニクス株式会社 電子装置および電子機器
US11251135B2 (en) 2018-04-02 2022-02-15 Samsung Electro-Mechanics Co., Ltd. Electronic device module and method of manufacturing the same
US10886149B2 (en) * 2019-01-31 2021-01-05 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN111866326B (zh) * 2019-04-30 2022-03-29 宁波舜宇光电信息有限公司 摄像模组及其电子元器件模块、感光组件、制备方法和电子元器件模块制备方法
US10937772B2 (en) * 2019-05-29 2021-03-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and method for manufacturing the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732907B2 (en) * 2006-05-30 2010-06-08 Stats Chippac Ltd. Integrated circuit package system with edge connection system
US8304869B2 (en) * 2008-08-01 2012-11-06 Stats Chippac Ltd. Fan-in interposer on lead frame for an integrated circuit package on package system
US7732252B2 (en) * 2008-10-09 2010-06-08 Stats Chippac Ltd. Multi-chip package system incorporating an internal stacking module with support protrusions
US8558392B2 (en) * 2010-05-14 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
US9293358B2 (en) * 2014-01-23 2016-03-22 Silicon Storage Technology, Inc. Double patterning method of forming semiconductor active areas and isolation regions
US9527723B2 (en) * 2014-03-13 2016-12-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming microelectromechanical systems (MEMS) package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112399791A (zh) * 2019-08-14 2021-02-23 三星电机株式会社 电子组件模块以及包括所述电子组件模块的电子器件
CN112399791B (zh) * 2019-08-14 2023-10-31 三星电机株式会社 电子组件模块以及包括所述电子组件模块的电子器件

Also Published As

Publication number Publication date
TW201806090A (zh) 2018-02-16
US20180061808A1 (en) 2018-03-01
US9818722B1 (en) 2017-11-14
US10163854B2 (en) 2018-12-25

Similar Documents

Publication Publication Date Title
CN107689351A (zh) 封装结构
CN106356340B (zh) 半导体器件及其制造方法
CN104051334B (zh) 半导体封装和封装半导体装置的方法
CN105304509B (zh) 半导体封装和封装半导体装置的方法
CN108666280A (zh) 封装结构
US10269619B2 (en) Wafer level chip scale packaging intermediate structure apparatus and method
TWI710073B (zh) 具有天線的半導體封裝及其製造方法
CN109494202B (zh) 一种半导体芯片封装方法及封装结构
CN103972140B (zh) 封装方法及封装半导体器件
CN108695267A (zh) 封装结构
CN107689333A (zh) 半导体封装件及其形成方法
CN107346766A (zh) 整合扇出型封装及其制造方法
CN103915414A (zh) 倒装芯片晶片级封装及其方法
CN106169466A (zh) 半导体封装组件及其制造方法
JP2000340714A (ja) 半導体パッケージ及びその製造方法
JP2000340713A (ja) 半導体パッケージ及びその製造方法
CN112233986B (zh) 芯片封装结构的制作方法及塑封模具
US20130234330A1 (en) Semiconductor Packages and Methods of Formation Thereof
US10096567B2 (en) Package substrate and package
CN107546186B (zh) 衬底、包含衬底的半导体封装及其制造方法
CN105720018B (zh) 在缓冲层中具有开口的集成扇出结构
CN107342278A (zh) 封装结构
JP2009272512A (ja) 半導体装置の製造方法
CN101796634B (zh) 包括功率半导体管芯和具有暴露表面部分的热沉的子组件
CN111883431B (zh) 一种具有高效散热结构的封装基板及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180213

WD01 Invention patent application deemed withdrawn after publication