CN107688506A - A kind of BCH decoding systems of flowing structure - Google Patents
A kind of BCH decoding systems of flowing structure Download PDFInfo
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- CN107688506A CN107688506A CN201710769471.2A CN201710769471A CN107688506A CN 107688506 A CN107688506 A CN 107688506A CN 201710769471 A CN201710769471 A CN 201710769471A CN 107688506 A CN107688506 A CN 107688506A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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Abstract
The invention discloses a kind of BCH decoding systems of flowing structure, belong to computer storage error correcting technique field.Present system includes：The sub- computing module of parallel correction, for according to the data parallel syndrome received；Key equation solving parallel Chien search module, for going out key equation according to syndrome computations, and find out the solution of key equation；FIFO memory module, for caching the data that are read from NAND Flash chips, and when calculating the solution of key equation, progressively data in output fifo memory module；BCH decoding controller modules, for realizing that BCH decodes the parallel execution of two level production lines.Present system is carried out BCH decodings using parallel and pipeline structure, can be effectively increased the throughput of BCH decodings and reduce hardware spending by the hardware resource being multiplexed in BCH decoders in disparate modules.
Description
Technical field
The invention belongs to computer storage field of error correction field, and system is decoded more particularly, to a kind of BCH of flowing structure
System.
Background technology
With the extensive use using NAND Flash as the non-volatile memory apparatus of medium, individual layer NAND Flash without
Method meets the requirement of Large Copacity, low cost storage device, and Multilayer Memory unit cost of new generation is low, storage density is high, storage is held
Amount is big, is increasingly being applied in Nonvolatile memory system, yet with chip technology processing procedure and adjacent programmed rank away from
From less and less, NAND Flash raw bit error rate (RBER) sharply increases, and traditional error correcting code can not meet can
Required by property.BCH (Bose, Ray-Chaudhuri, Hocquenghem) codes are as a kind of cyclic code, its function admirable, structure
Simply, it is a kind of error-correcting code technique for being widely used in storage system.When writing data to NAND Flash chips, original number
According to 8 parallel-by-bit Bose-Chaudhuri-Hocquenghem Code devices are passed through, NAND Flash chips are write after completing data encoding, are read when from NAND Flash chips
During data, the reading data of 8 parallel-by-bits from chip, and BCH decoders are input to simultaneously, if the error in data quantity of storage
The maximum number of errors that can be corrected less than BCH code, then export correct initial data, if error in data quantity is higher than BCH
The maximum number of errors that code can be corrected then reports decoding failure.
The cataloged procedure of BCH code is relatively simple, is realized using linear feedback shift register (LFSR).The decoding of BCH code
Process, three steps are broadly divided into, are syndrome computations, key equation solving and chien search respectively.Wherein key equation is asked
Solution preocess is complicated, consumes substantial amounts of hardware logic resource, is the nucleus module in BCH decoding circuits, current research is main
The implementation complexity for reducing key equation solving circuit is concentrated on, and lifts the decoding speed of BCH decoders mainly by parallel
The mode of change is realized, syndrome computations and chien search algorithm during being decoded by parallelization, can significantly be improved
BCH decoding speed.But the modules of discrete research BCH decoders, consider not from entirety in BCH decoders
Circuit resource share, cause substantial amounts of hardware resource cost.There is research team to propose a kind of shared hardware resource at present
Syndrome-chien search block circuit structure, the overall hardware complexity of BCH decoders can be reduced, but can not realize and translate
The pipeline mode of code process performs, and constrains the raising of performance.
The content of the invention
For the disadvantages described above or Improvement requirement of prior art, the invention provides a kind of BCH of flowing structure to decode system
System, its object is to the characteristics of digital independent, lead in the hardware design of overall thinking BCH decoders and SSD storage devices
The hardware resource in disparate modules in multiplexing BCH decoders is crossed, BCH decodings are carried out using parallel and pipeline structure, thus reduce BCH
The hardware spending of decoder, improve the decoding speed of BCH decoders.
To achieve the above object, according to one aspect of the present invention, there is provided a kind of BCH decoding systems of flowing structure,
The system includes：
The sub- computing module of parallel correction, for according to the data parallel syndrome received；
Key equation solving-parallel Chien search module, for going out key equation according to syndrome computations, and pass through search
Key equation root finds out the solution of key equation, and finite field is multiplexed during key equation and search key equation root is calculated
Multiplier；
FIFO memory module, for caching the data read from NAND Flash chips, and calculating key equation
Solution when, progressively data in output fifo memory module；
BCH decoding controller modules, for realizing that BCH decodes the parallel execution of two level production lines：The first of streamline
Level, read data from NAND Flash chips and be written to simultaneously in the sub- computing module of parallel correction and FIFO memory module；
In the second level of streamline, the syndrome obtained in the sub- computing module of parallel correction is input to key equation solving-parallel money
In family name's search module, the progressively data in output fifo memory module, and FIFO is corrected according to the solution of obtained key equation
The wrong data exported in memory module.
Further, the sub- computing module of the parallel correction is specifically used for：
Receive to read data from NAND Flash chips, according to the data parallel of reading calculate data corresponding to it is minimum
Polynomial residue, and according to corresponding to calculating residue syndrome value.
Further, the key equation solving-parallel Chien search module is specifically used for calculating using SIBM algorithms
Key equation, use chien search algorithm search key equation root.
In general, by the contemplated above technical scheme of the present invention compared with prior art, have following technology special
Sign and beneficial effect：
(1) translated by being multiplexed Galois field multiplier reduction during key equation and search key equation root is calculated
The hardware spending of code；
(2) the parallel execution that BCH decodes two level production lines is realized, improves decoding efficiency throughput.
Brief description of the drawings
Fig. 1 is the structural representation of the embodiment of technical solution of the present invention；
Fig. 2 is the parallel correction submodular circuits schematic diagram of the embodiment of the present invention
Fig. 3 is the SIBM algorithm circuit diagrams of the embodiment of the present invention；
Fig. 4 is the parallel Chien search circuit diagram of the embodiment of the present invention；
Fig. 5 is key equation solving-parallel Chien search circuit diagram of the embodiment of the present invention；
Fig. 6 (a) is that BCH of the embodiment of the present invention is decoded without flowing water schematic diagram；
Fig. 6 (b) is that BCH of the embodiment of the present invention decodes flowing water schematic diagram；
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, not
For limiting the present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below that
Conflict can is not formed between this to be mutually combined.
The technical term of the present invention is explained and illustrated first, and following provisions are made in subsequent descriptions：
BCH (n, k, t) code：Expression code word size is n positions (n<=2m- 1, m are positive integer, work as n=2mWhen -1, the BCH code
For standard BCH code), information bit length is k positions, and redundant digit information bit is r positions (r=n-k), and t represents the error correction energy of the error correcting code
Power, any mistake less than t bits for representing to occur in the n positions of code word can correct.
BCH shortens code：For all n<2m- 1 BCH code word, all it is that a kind of of standard BCH code shortens code, a shortening
BCH code can be seen as a high bit sequence be 0 standard BCH code, therefore shorten BCH code error correcting capability keep not
Become.
It is as shown in Figure 1 the structural representation of one embodiment of the present invention, including the sub- computing module of parallel correction, key
Equation solution-parallel Chien search module, FIFO memory module and BCH decoding controller modules；
The sub- computing module of parallel correction, for calculation code syndrome, for BCH (n, k, t) code, parallel correction calculates
Module calculates the 2t syndromes being defined as below：
Wherein, SiRepresent i-th of syndrome；αiRepresent i-th of element in finite field；R(αi) represent to receive multinomial, N
Represent the maximum power exponent of remainder polynomid, r (αi) represent αiThe residue of corresponding minimal polynomial；rj(αi) represent that remainder is multinomial
Number is j value in formula.
The syndrome computations modular circuit schematic diagram of one 8 parallel-by-bit is as shown in Fig. 2 data are defeated in a manner of 8 parallel-by-bits
Entering, intermediate result is maintained in register (Parity Reg) by the sub- computing module of parallel correction, after completing data input, deposit
Value in device (Parity Reg) is r (x), by αiSubstitute into r (x) and obtain required syndrome.
Key equation solving-parallel Chien search module, for solving BCH decoding key equations and searching for key equation
Root, wherein solving BCH decoding key equations uses SIBM algorithms, the root for searching for key equation uses chien search algorithm.It is crucial
Equation solution-parallel Chien search module uses 2t syndrome Si, 0<i<2t solves key equation and passed through as input
The form for searching for key equation root judges whether some data bit malfunctions.
SIBM algorithms circuit diagram is as shown in figure 3, syndrome Si, 0<i<2t is progressively shifted in a manner of shift register
Into SIBM algorithm circuits, according to SIBM algorithms, circuit as shown in Figure 3 needs to use 2t general finite domain multiplier, warp
Cross t iteration, you can calculate key equation.
8 parallel-by-bit Chien search circuit schematic diagrames are as shown in figure 4, the Chien search circuit of 8 parallel-by-bit has needs altogether makes
With (8+1) t constant Galois field multiplier, parallel Chien search circuit receives the key equation from SIBM algorithm circuits, just
Intermediate result is stored in register D after the completion of beginningization, whether the Chien_result result mark data bit malfunctions,
By n, (either k) secondary iteration can search for complete code word (or information bit).
Key equation solving-parallel Chien search modular circuit schematic diagram is as shown in figure 5, SIBM algorithms have calculated key side
After journey, the digit h that code shortens is shortened according to BCH, directly calculates the value of the key equation afterwards of iteration h time.To accelerate Qian Shi
The speed of search, the general finite domain multiplier being multiplexed in Chien search circuit module in SIBM circuit modules, completes Qian Shi
The iterative calculation of search, in the embodiment, key equation solving-parallel Chien search block is multiplied altogether using 2t general finite domain
Musical instruments used in a Buddhist or Taoist mass, 6t constant Galois field multiplier, the Chien search circuit compared to discrete SIBM algorithms circuit and 8 parallel-by-bits can subtract
The use of few 3t constant Galois field multiplier.
FIFO memory module, for caching the data read from NAND Flash chips, perform chien search iteration
During algorithm, progressively data in output fifo memory module.
BCH decoding controller modules, for controlling the sub- computing module of parallel correction, key equation solving-parallel Qian Shi to search
Data interaction between rope module and FIFO memory module.According to the characteristics of NAND Flash pages, in a NAND Flash
Multiple Bose-Chaudhuri-Hocquenghem Code code words are generally had in page, the BCH decoding controllers module is used to realize multiple BCH codes in a page
The parallel execution of word two-stage flowing water, wherein parallel correction are calculated as the streamline first order, and key equation calculating-parallel Qian Shi is searched
Rope is the streamline second level, and BCH decodings are shown without flowing water schematic diagram such as Fig. 6 (a), flowing water schematic diagram such as Fig. 6 (b).NAND
When Flash chip reads data, data are written to the sub- computing module of parallel correction and FIFO by BCH decoding controllers module simultaneously
In memory module, corresponding parallel correction as in Fig. 6 (b) calculates, after first code word reading finishes, by syndrome meter
The syndrome that module obtains is calculated to be input in key equation solving-parallel Chien search block, and by the code word of subsequent readout simultaneously
It is written in the sub- computing module of parallel correction and FIFO memory module, starts the decoded operation of next code word, chien search
During module iteration, data in output fifo memory module simultaneously correct wrong data according to search result.
Above content as it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention,
It is not intended to limit the invention, all any modification, equivalent and improvement made within the spirit and principles of the invention etc.,
It should be included in the scope of the protection.
Claims (3)
1. the BCH decoding systems of a kind of flowing structure, it is characterised in that the system includes：
The sub- computing module of parallel correction, for according to the data parallel syndrome received；
Key equation solving-parallel Chien search module, for going out key equation according to syndrome computations, and it is crucial by searching for
Equation root finds out the solution of key equation, and being multiplexed finite field during key equation and search key equation root is calculated multiplies
Musical instruments used in a Buddhist or Taoist mass；
FIFO memory module, for caching the data read from NAND Flash chips, and in the solution for calculating key equation
When, progressively data in output fifo memory module；
BCH decoding controller modules, for realizing that BCH decodes the parallel execution of two level production lines：In the first order of streamline, from
NAND Flash chips read data and are written to simultaneously in the sub- computing module of parallel correction and FIFO memory module；In flowing water
The second level of line, the syndrome obtained in the sub- computing module of parallel correction is input to key equation solving-parallel Chien search
In module, the progressively data in output fifo memory module, and FIFO memory is corrected according to the solution of obtained key equation
The wrong data exported in module.
2. BCH decoding systems according to claim 1, it is characterised in that the sub- computing module of parallel correction is specifically used
In：
Receive to read data from NAND Flash chips, according to the data parallel of reading calculate data corresponding to it is minimum multinomial
The residue of formula, and according to corresponding to calculating residue syndrome value.
3. BCH decoding systems according to claim 1, it is characterised in that the key equation solving-parallel Chien search
Module is specifically used for calculating key equation using SIBM algorithms, uses chien search algorithm search key equation root.
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Cited By (2)
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| CN110875746A (en) * | 2018-08-29 | 2020-03-10 | 南京大学 | Hardware architecture of high-speed GII decoder |
| CN112099986A (en) * | 2020-08-11 | 2020-12-18 | 西安电子科技大学 | ECC decoding system and method of branch pipeline structure |
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