CN107679262B - Modeling method for peripheral parasitic resistance of MOS device substrate - Google Patents

Modeling method for peripheral parasitic resistance of MOS device substrate Download PDF

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CN107679262B
CN107679262B CN201710685114.8A CN201710685114A CN107679262B CN 107679262 B CN107679262 B CN 107679262B CN 201710685114 A CN201710685114 A CN 201710685114A CN 107679262 B CN107679262 B CN 107679262B
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刘林林
王全
郭奥
周伟
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Shanghai IC R&D Center Co Ltd
Chengdu Light Collector Technology Co Ltd
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Abstract

The invention discloses a modeling method of peripheral parasitic resistance of a substrate of an MOS device, which comprises the following steps: s01 building a ring-shaped resistance test structure corresponding to the MOS device, S02 building a terminal resistance auxiliary test structure, S03 building a terminal resistance telescopic model, and S04 testing the resistance R of the ring-shaped resistance test structuretot2And the circumferences of the inner ring and the outer ring are introduced into a telescopic model of the end resistance to obtain R1And R2Of (2) so that Rsti＝Rtot2‑R1‑R2R under different layout sizes can be obtained by changing layout factorsstiValue of (2), analysis of RstiAnd establishing a scalable model of the peripheral parasitic resistance of the substrate of the MOS device according to the change relation of the layout size. According to the modeling method of the peripheral parasitic resistance of the MOS device substrate, the parasitic resistance introduced from the periphery of the active region of the MOS device can be directly represented, and the scalable model of the peripheral parasitic resistance of the MOS device substrate obtained through modeling is suitable for layout modes under different conditions.

Description

Modeling method for peripheral parasitic resistance of MOS device substrate
Technical Field
The invention relates to the field of semiconductor integrated circuit testing and modeling, in particular to a modeling method for peripheral parasitic resistance of a substrate of an MOS (metal oxide semiconductor) device.
Background
In the field of radio frequency integrated circuits, the substrate resistance of a MOS device determines the output characteristics of the device to a large extent, and the influence thereof in the design of a radio frequency integrated circuit is not negligible. The substrate resistor of the MOS device is divided into two parts by taking the active region of the device as a boundary, wherein one part is the active region, namely the substrate part below the source region, the drain region and the channel region of the MOS device, and the other part is the periphery of the active region of the device, namely the substrate part below the STI (shallow trench isolation) region between the substrate leading-out end and the active region.
For the latter, the calculation of the substrate part resistance is related to the layout factor and the arrangement mode of the device, wherein the layout factor corresponds to the layout design size. In the active radio frequency device modeling process in the prior art, a two-port test structure is adopted to carry out modeling representation on the active radio frequency device, but in the two-port test structure, the part is difficult to be accurately defined and represented, so that the precision of a substrate resistance model is insufficient, and the result of circuit design is influenced.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a modeling method of the peripheral parasitic resistance of the substrate of the MOS device, the parasitic resistance introduced at the periphery of the active region of the MOS device can be directly represented by the method, and the scalable model of the peripheral parasitic resistance of the substrate of the MOS device obtained by modeling is suitable for layout modes under different conditions.
In order to achieve the purpose, the invention adopts the following technical scheme: a modeling method for peripheral parasitic resistance of a substrate of an MOS device comprises the following steps:
s01, establishing an annular resistance test structure corresponding to the MOS device, wherein the MOS device comprises an active region positioned in the center of the device, grid electrodes uniformly distributed in the active region, body end annular leading-out electrodes positioned outside the active region and the grid electrodes, and a substrate trap positioned outside the body end annular leading-out electrodes, the width of the body end annular leading-out electrodes is rw, and the substrate trap is used for isolating the MOS device from the outside;
the annular resistance test structure sequentially comprises an inner ring, an outer ring and an annular substrate well from inside to outside, the width of the inner ring and the width of the outer ring are rw, the region between the inner ring and the outer ring and the inner region of the inner ring are STI regions, and the resistance of the inner ring is R2The resistance of the outer ring being R1The resistance of the STI region is RstiThe substrate trap is used for isolating the annular resistance test structure from the outside;
the layout design size of the annular resistance test structure is the same as that of the MOS device;
s02, establishing a terminal resistor auxiliary test structure, wherein the terminal resistor auxiliary test structure comprises rectangular terminals on two opposite sides of a rectangle and a substrate trap on the outer side of the terminals; the widths of the two end heads are rw, the side length of a rectangle in which the end heads are positioned is w, the distance between the two end heads is l, the components of the two end heads are the same as those of the inner ring and the outer ring in the annular resistance test structure, and the layout modes of the contact holes of the two end heads are the same;
s03, establishing a terminal resistance telescopic model: fixing w, changing the value of l, and measuring the resistance value R of a series of corresponding end resistor auxiliary test structurestot1With Rtot1Drawing a curve with the ordinate and the abscissa as l/w, wherein the intercept of the curve on the ordinate is the total resistance of the two terminals, the terminal resistances on the two sides in the terminal resistance auxiliary test structure are the same, and the terminal resistance R isendSelecting multiple groups of w as half of the intercept to obtain R in the end resistor auxiliary test structureendA scalable model of termination resistance between w;
s04, establishing a scalable model of the peripheral parasitic resistance of the substrate of the MOS device: resistance R of test ring-shaped resistance test structuretot2Substituting the circumferences of the inner ring and the outer ring into w in the telescopic termination resistance model to obtain R2And R1Resistance of Rsti＝Rtot2-R1-R2R under different layout sizes can be obtained by changing layout factorsstiValue of (2), analysis of RstiAnd establishing a scalable model of the peripheral parasitic resistance of the substrate of the MOS device according to the change relation of the layout size.
Further, the scalable model of the terminal resistor auxiliary test structure in the step S03 is
Figure GDA0002715592980000021
Wherein R isconIs a resistance of a contact hole, NconThe number of contact holes introduced for the termination at one end, a is the termination resistance scalability model parameter.
Further, the circumference of the inner ring in step S04 is selected as the average of the outer circumference and the inner circumference.
Further, in step S04, the circumference of the outer ring is selected as the average of the outer circumference and the inner circumference.
Furthermore, the active region and the body end annular leading-out electrode of the MOS device are both rectangular, and correspondingly, the inner ring and the outer ring in the annular resistance test structure are both rectangular.
Furthermore, the inner ring and the outer ring in the annular resistance test structure are both rectangular annular structures formed by the injection active region and the contact hole.
Further, the implantation type of the active region in the inner ring and the outer ring in the annular resistance test structure is opposite to that of the active region of the MOS device.
Further, the layout factors of the MOS device are the width waa and the length laa of the active region of the MOS device, and the distances s between the active region and the body end annular leading-out electrode in four directions1、s2、s3And s4Correspondingly, the layout factors in the annular resistance test structure include the width waa and the length laa of the inner ring, and the distances s between the inner ring and the outer ring in four directions1、s2、s3And s4。
Further, the scalable model of the peripheral parasitic resistance of the MOS device substrate in step S04 is:
Figure GDA0002715592980000031
wherein, asti，a1，a2，a3，b1，b2，b3，b4And determining model parameters of a scalable model of the peripheral parasitic resistance of the MOS device substrate by fitting Rsti values under different layout factors.
The invention has the beneficial effects that: the annular resistance test structure in the modeling method can directly represent parasitic resistance introduced at the periphery of the active region of the MOS device, thereby avoiding the problem that the traditional MOS test structure does not represent the information of the part of the MOS device sufficiently. In addition, the modeling method establishes a scalable model of the peripheral parasitic resistance of the MOS device substrate based on the layout factors, so that the model can be suitable for layout modes under different conditions.
Drawings
FIG. 1 is a flow chart of a modeling method of a peripheral parasitic resistance of a substrate of an MOS device according to the present invention.
FIG. 2 is a schematic diagram of a hierarchical structure of an NMOS layout part.
FIG. 3 is a cross-sectional view of an NMOS.
FIG. 4 is a hierarchical diagram of a layout part of a ring resistance test structure.
FIG. 5 is a cross-sectional view of a ring resistance test structure.
Fig. 6 is a hierarchical schematic diagram of a layout part of the termination resistance auxiliary test structure.
FIG. 7 is a diagram showing a layout part hierarchy of different connection modes.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, for the purpose of clearly showing the structure of the present invention for the convenience of explanation, it is to be understood that the structure shown in the drawings is not drawn to scale, and that the partial method, modification and simplification are performed, and therefore, the present invention should not be construed as limited thereto.
The MOS devices are divided into PMOS devices and NMOS devices, and the following drawings and descriptions take NMOS devices as examples, and when the devices are PMIOS, the modeling method adopted is similar to that of the NMOS devices, and only the type of the substrate well and the implantation types of the active regions in the inner ring and the outer ring need to be changed, which is not described herein in detail.
As shown in fig. 1, a method for modeling a peripheral parasitic resistance of a substrate of a MOS device includes the following steps:
s01, establishing an annular resistance test structure corresponding to the MOS device, wherein the MOS device comprises an active region positioned in the center of the device, a grid uniformly distributed in the active region, an end annular leading-out electrode positioned outside the active region and the grid, and a substrate trap positioned outside the end annular leading-out electrode, the width of the end annular leading-out electrode is rw, and the substrate trap NW is used for isolating the MOS device from the outside; the annular resistance test structure comprises an inner ring, an outer ring and an annular substrate well from inside to outside in sequence, the width of the inner ring and the width of the outer ring are rw, the region between the inner ring and the outer ring and the inner region of the inner ring are STI regions, the resistance of the inner ring is R2The resistance of the outer ring being R1The resistance of the STI region is RstiThe substrate trap is used for isolating the annular resistance test structure from the outside; the transformable layout factor of the annular resistance test structure is the same as that of the MOS device.
The shapes of the active region and the body end annular leading-out electrodes of the MOS device can be various in actual production, the shapes of the inner ring and the outer ring in the corresponding annular resistance test structure are consistent with those of the MOS device, corresponding layout factors are set for the MOS devices with different shapes, and a corresponding telescopic model of the substrate peripheral parasitic resistance can be established for the MOS devices with different shapes.
In order to more clearly illustrate the beneficial effects of the invention, the shapes of the active region and the body end annular leading-out electrode in the MOS device are both rectangular to illustrate the invention in detail, and when the shapes of the active region and the body end annular leading-out electrode are other shapes, the methods for establishing the annular resistance test structure and the telescopic model of the substrate peripheral parasitic resistance are similar, and are not illustrated in the invention one by one.
As shown in fig. 2 and fig. 4, the active region and the bulk end ring-shaped extraction electrode of the NMOS device are rectangular, correspondingly, the inner ring and the outer ring in the ring-shaped resistance test structure are rectangular, and the inner ring and the outer ring in the ring-shaped resistance test structure are rectangular ring-shaped structures formed by the implanted active region and the contact hole. The inner ring and the outer ring are respectively led out to the upper layer metal pole through the contact holes to be tested. The width of the body end annular extraction electrode in the MOS device is rw, correspondingly, the widths of the inner ring and the outer ring in the annular resistance test structure are rw, but the width of the implantation region is larger than rw during the ion implantation process of the inner ring and the outer ring. When the active region and the body end annular leading-out electrode of the MOS device are both rectangular, the corresponding layout factors are the width waa and the length laa of the active region, and the distances between the active region and the body end annular leading-out electrode in four directions are s1, s2, s3 and s 4. Correspondingly, the layout factors in the ring-shaped resistance test structure include the width waa and the length laa of the inner ring, and the distances s1, s2, s3 and s4 between the inner ring and the outer ring in four directions. As shown in FIG. 4, the resistance of the inner ring in the ring-shaped resistance test structure is R2The resistance of the outer ring being R1The resistance of the STI region is Rsti. The inner ring is led out to the upper layer metal pole through the contact hole, and the outer ring is led out to the upper layer metal pole through the contact hole.
As shown in FIGS. 3 and 5, the resistance of the NMOS device is represented by STI resistance R introduced between the active region and the body-end annular extraction electrodestiAnd the ring resistance R of the end ring extraction electrode1The resistance of the ring-shaped resistance test structure is composed of an internal ring resistance R2Outer ring resistance R1And a ring-shaped STI resistor between the inner ring and the outer ring.
S02, establishing a terminal resistor auxiliary test structure, wherein the terminal resistor auxiliary test structure comprises rectangular terminals on two opposite sides of a rectangle and a substrate trap on the outer side of the terminals; the width of each end is rw, the side length of the rectangle where the end is located is w, and the distance between the two ends is l.
As shown in fig. 6, which is a hierarchical schematic diagram of a layout part of an end-point resistance auxiliary test structure, components of two end points are the same as those of an inner ring and an outer ring in an annular resistance test structure.
S03, as shown in fig. 6, establishing a termination resistance scalable model: fixing w, changing the value of l, and measuring the resistance value R of a series of corresponding end resistor auxiliary test structurestot1With Rtot1And drawing a curve, wherein the intercept of the curve on the ordinate is the total resistance of the two ends, the resistances of the two ends in the auxiliary end resistance test structure are the same, one half of the intercept is the introduced end resistance Rend, and a plurality of groups of w are selected to obtain an end resistance telescopic model between the Rend and the w in the auxiliary end resistance test structure.
When the scalable model of the end resistance is established, the following formula can be adopted for simulation:
Figure GDA0002715592980000051
wherein R isend is half of the intercept, RconIs a resistance of a contact hole, NconThe number of contact holes introduced for the termination at one end, a is the termination resistance scalability model parameter.
S04, establishing a scalable model of the peripheral parasitic resistance of the substrate of the NMOS device: resistance R of test ring-shaped resistance test structuretot2The perimeter of the inner ring and the outer ring is substituted into w in the scalable termination resistance model to obtain R2And R1Resistance of Rsti＝Rtot2-R1-R2R under different layout sizes can be obtained by changing layout factorsstiValue of (2), analysis of RstiAnd establishing a scalable model of the peripheral parasitic resistance of the substrate of the NMOS device according to the change relation of the layout size.
Wherein the circumference of the inner ring is selected from the average of the outer circumference and the inner circumference, and the circumference of the outer ring is selected from the outer circumference and the inner circumferenceAverage value of the circumference. When the active region and the body end annular leading-out electrode of the NMOS device are both rectangular, and the inner ring and the outer ring in the annular resistance test structure are both rectangular, the perimeter of the central line of the inner ring and the R can be adjustedcon、NconR obtained by calculation is substituted into the telescopic end resistor modelendEquivalent as the resistance of the inner ring is R2The circumference R of the center line of the outer ringcon、NconR obtained by calculation is substituted into the telescopic end resistor modelendEquivalent as the resistance of the outer ring is R1Testing the resistance R of the annular resistance test structuretot2The resistance of the STI region is obtained to be Rsti＝Rtot2-R1-R2。
The layout factors are changed, and R under different layout factors can be obtainedstiAnalysis of RstiAnd providing a fitting model of the substrate peripheral parasitic resistance according to the change relation between the layout factors. In the invention, the layout factors are the width waa and the length laa of the source region, and the distances between the active region and the body end annular leading-out electrode in four directions are s1、s2、s3And s4. The scalable model of the peripheral parasitic resistance of the substrate of the NMOS device is as follows:
Figure GDA0002715592980000061
wherein, asti，a1，a2，a3，b1，b2，b3，b4And determining model parameters of a scalable model of the peripheral parasitic resistance of the MOS device substrate by fitting Rsti values under different layout factors.
The modeling method establishes a scalable model of the peripheral parasitic resistance of the MOS device substrate based on layout factors, and is applicable to layout modes under different conditions, as shown in FIG. 7, the layout modes with different connection modes can adopt the model to calculate the peripheral parasitic resistance.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.

Claims (9)

1. A modeling method for peripheral parasitic resistance of a substrate of an MOS device is characterized by comprising the following steps:
s01, establishing an annular resistance test structure corresponding to the MOS device, wherein the MOS device comprises an active region positioned in the center of the device, grid electrodes uniformly distributed in the active region, body end annular leading-out electrodes positioned outside the active region and the grid electrodes, and a substrate trap positioned outside the body end annular leading-out electrodes, the width of the body end annular leading-out electrodes is rw, and the substrate trap is used for isolating the MOS device from the outside;
the annular resistance test structure sequentially comprises an inner ring, an outer ring and an annular substrate well from inside to outside, the width of the inner ring and the width of the outer ring are rw, the region between the inner ring and the outer ring and the inner region of the inner ring are STI regions, and the resistance of the inner ring is R2The resistance of the outer ring being R1The resistance of the STI region is RstiThe substrate trap is used for isolating the annular resistance test structure from the outside;
the layout design size of the annular resistance test structure is the same as that of the MOS device;
s02, establishing a terminal resistor auxiliary test structure, wherein the terminal resistor auxiliary test structure comprises rectangular terminals on two opposite sides of a rectangle and a substrate trap on the outer side of the terminals; the widths of the two end heads are rw, the side length of a rectangle in which the end heads are positioned is w, the distance between the two end heads is l, the components of the two end heads are the same as those of the inner ring and the outer ring in the annular resistance test structure, and the layout modes of the contact holes of the two end heads are the same;
s03, establishing a terminal resistance telescopic model: fixing w, changing the value of l, and measuring the resistance value R of a series of corresponding end resistor auxiliary test structurestot1With Rtot1Is the ordinate, l/w is the abscissa,drawing a curve, wherein the intercept of the curve on a vertical coordinate is the total resistance of the two ends, the resistances of the two ends in the end resistance auxiliary test structure are the same, and the end resistance R isendSelecting multiple groups of w as half of the intercept to obtain R in the end resistor auxiliary test structureendA scalable model of termination resistance between w;
s04, establishing a scalable model of the peripheral parasitic resistance of the substrate of the MOS device: resistance R of test ring-shaped resistance test structuretot2The perimeter of the inner ring and the outer ring is substituted into w in the scalable termination resistance model to obtain R2And R1Resistance of Rsti＝Rtot2-R1-R2And R under different layout sizes can be obtained by changing layout factors corresponding to the layout design sizesstiValue of (2), analysis of RstiAnd establishing a scalable model of the peripheral parasitic resistance of the substrate of the MOS device according to the change relation of the layout size.
2. The method of claim 1, wherein the scalable model of the termination resistance-aided test structure in step S03 is a scalable model of the parasitic resistance at the periphery of the substrate of the MOS device
Figure FDA0002715592970000011
Wherein R isconIs a resistance of a contact hole, NconThe number of contact holes introduced for the termination at one end, a is the termination resistance scalability model parameter.
3. The method of claim 1, wherein the perimeter of the inner ring in step S04 is the average of the outer perimeter and the inner perimeter.
4. The method of claim 1, wherein the perimeter of the outer ring in step S04 is an average of the outer perimeter and the inner perimeter.
5. The method of claim 1, wherein the MOS device active region and the bulk annular extraction electrode are rectangular, and correspondingly, the inner ring and the outer ring of the annular resistance test structure are rectangular.
6. The method of claim 5, wherein the inner ring and the outer ring of the ring-shaped resistance test structure are rectangular ring-shaped structures formed by the implanted active region and the contact hole.
7. The modeling method of the MOS device substrate peripheral parasitic resistance of claim 6, wherein the implantation type of the inner ring and the outer ring of the ring-shaped resistance test structure for implanting the active region is opposite to that of the active region of the MOS device.
8. The modeling method of the peripheral parasitic resistance of the MOS device substrate according to claim 5, wherein the layout factors of the MOS device are the width waa and the length laa of the active region of the MOS device, and the distances s between the active region and the body end annular leading-out electrode in four directions1、s2、s3And s4Correspondingly, the layout factors in the annular resistance test structure include the width waa and the length laa of the inner ring, and the distances s between the inner ring and the outer ring in four directions1、s2、s3And s4。
9. The method of claim 8, wherein the scalable model of the peripheral parasitic resistance of the MOS device substrate in the step S04 is:
Figure FDA0002715592970000021
wherein, asti，a1，a2，a3，b1，b2，b3，b4And determining model parameters of a scalable model of the peripheral parasitic resistance of the MOS device substrate by fitting Rsti values under different layout factors.
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