CN107665864A - 具有气隙间隔件的finfet及其形成方法 - Google Patents
具有气隙间隔件的finfet及其形成方法 Download PDFInfo
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- CN107665864A CN107665864A CN201710622775.6A CN201710622775A CN107665864A CN 107665864 A CN107665864 A CN 107665864A CN 201710622775 A CN201710622775 A CN 201710622775A CN 107665864 A CN107665864 A CN 107665864A
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Classifications
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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Abstract
本发明涉及具有气隙间隔件的FINFET及其形成方法,鳍式场效应晶体管(FinFET)包括位于相邻的金属接触件之间及/或位于金属接触件与晶体管栅极之间的气隙。该气隙在非共形沉积一隔离介电质结合一先金属工艺以形成该导电结构的期间形成。
Description
技术领域
本申请通常涉及半导体装置的制造,尤指用于电性隔离的气隙的形成以及在先进的FinFET节点(例如相邻的金属接触件之间以及金属接触件与晶体管栅极之间)内的寄生电容和电感耦合的最小化。
背景技术
形成接触金属化(contact metallization)的传统方法是使用连续蚀刻以及沉积步骤以首先在一层间介电质中形成接触通孔。然后用一导电材料填充该接触通孔。然而,这样一个工艺(process)的强健性(robustness)和重复性正受到装置尺寸减小的挑战,例如,在一7纳米节点的小于50纳米的接触件至接触件的间隔处以及小于20纳米的接触件至栅极(contact-to-gate)的间隔处的图案化限制可导致高漏电流及短路,其至少部分归因于相邻的导电结构之间介电质隔离的不足以及桥接导电体之间的间隙的剩余导电材料。而一个或多个金属化材料的一额外的凹槽蚀刻可用于移除表面残留,这种附加工艺不利于增加工艺的额外制造步骤。
发明内容
应该认识到需要一种具有成本效益的集成方法以在先进的节点上提供有效的电性隔离。
根据本申请的各种实施例,揭露了一种于鳍式场效应晶体管的栅极结构周围形成气隙(air-gap)的方法。该气隙可结合于沉积一隔离介电层而形成,并且可以驻留于栅极的顶部及两侧的上方。该气隙提供有效的金属间隔离。
具体而言,所公开的方法包括首先形成例如一钨层的一金属层于被接触的一表面上,蚀刻该金属层以打开隔离孔并定义金属接触件,然而用以介电层回填该隔离孔。该介电层的非共形沉积可用于形成气隙于被接触的该表面的顶部上方及/或暴露侧壁上方。有利的是,先金属(metal-first)方法不涉及额外的掩膜或蚀刻步骤。
一种形成一半导体装置的方法包括:形成一栅极结构于一半导体鳍片的一通道区域的上方,该半导体鳍片具有位于该通道区域的相对侧上的一源极区域与一漏极区域。形成介电间隔件于该栅极结构的侧壁上方以及一介电盖体于该栅极结构的该顶部上方。形成一导电层于该介电盖体的上方以及相邻的介电间隔件之间的该源极区域与漏极区域的上方,以及然后形成通过该导电层的一孔(aperture)以暴露该介电盖体的一表面。形成一共形或非共形介电层于该孔中。
一种半导体装置,例如一鳍式场效应晶体管(FinFET)包括位于一半导体基板上方的一半导体鳍片以及位于该鳍片的一通道区域上方的一栅极结构。源极与漏极区域(source and drain regions)设置于该通道区域的相对两侧上。介电间隔件位于该栅极结构的侧壁上方以及一介电盖***于该栅极结构顶部的上方。一导电层形成于位于相邻的介电间隔件之间的该源极区域与该漏极区域的上方。一隔离介电质具有至少部分位于该栅极结构的上方的一气隙。该隔离介电质可从该栅极与该导电层之间的该侧壁间隔件的上方延伸。
附图说明
通过与下述图式进行结合,以最好地理解下述的本申请的具体实施例的详细描述,其中,相似的结构用相似的元件符号予以表示。
图1为使用一先金属沉积法而形成的具有沟槽硅化物接触件的一FinFET栅极结构的一示意图;
图2为根据各种实施例所示的于制造的一中间阶段的一半导体装置架构的一透视图;
图3A至图3I为根据各种实施例所示的靠近一鳍式场效应晶体管形成气隙的一示例工艺;
图4显示了位于晶体管栅极结构的侧壁上方的具有一介电质绝缘层的一部分的一FinFET栅极结构;
图5为根据一实施例显示FinFET栅极之间的气隙以及靠近该栅极侧壁的沟槽金属化;
图6为根据一实施例显示一FinFET栅极的顶部上方的该绝缘介电质内部的气隙的示意图;
图7为显示具有在该栅极侧壁上方延伸的该绝缘介电质的一FinFET栅极的该顶部上方的该绝缘介电质内部的气隙;
图8为根据各种实施例显示的位于一FinFET栅极的该顶部的上方以及位于该栅极与该沟槽金属化之间的该栅极侧壁上方的该绝缘介电质内部的气隙;以及
图9显示了位于一FinFET栅极堆栈的该顶部上方以及位于该栅极与该沟槽金属化之间的该栅极侧壁上方的合并的气隙。
主要组件符号说明
100 基板或半导体基板
110 支撑基板
120 隔离层或绝缘体层
150 空腔
202 鳍片或半导体鳍片
310a 凸起有源区域或凸起源极区域
310b 凸起有源区域或凸起漏极区域
400 栅极结构、栅极堆栈或栅极
410 栅极电极层
420 金属栅极导电体
510 氮化物间隔件
520 氮化物盖体、覆盖氮化层或氮化层
542 气隙
600 源极/漏极区域、外延源极/漏极区域或外延层
650 牺牲氧化物层
700 金属层
700a、700b、700c 金属接触件
710 硅化物区域或源极/漏极硅化物区域
810 掩膜层
820 光阻层
830 开口
840 隔离孔
842 延伸隔离孔
850、852、854 气隙
900 隔离介电层、隔离介电质、介电材料或介电层
d 深度
H 高度
S 间隔
t 厚度
W、w1、w2 宽度。
具体实施方式
现在将对本申请的主题的各个实施例更详细地进行说明,在附图中说明了其中的一些实施例。同样的元件符号将在整个图式中指代相同或相似的部分。应注意的是,该图示仅为了说明的目的而提供,其并为按照比例予以绘制。
在下面的描述中,所列出的许多具体细节,例如特征的结构、组件、材料、尺寸、处理步骤以及技术,用于提供针对本申请的各种实施例进行理解。然而,本领域的技术人员应当了解本申请的各种实施例可在没有这些具体细节的情况下予以实施。在其他情况下,已知的结构或处理步骤未予以详细的描述以避免模糊本申请。
本申请的各实施例通常涉及半导体装置的制造,尤其是鳍式场效应晶体管(FinFET)的制造。典型地装置包括具有在相邻的金属接触件之间及/或金属接触件与晶体管栅极之间的一个或多个气隙的鳍式场效应晶体管。气隙可在非共形沉积一隔离介电质结合一先金属工艺以形成导电结构的期间形成。如本文所使用的术语“气隙”包括含有空气或含有其他气体介电质(例如惰性气体)的间隙或通孔,以及含有至少一部分真空的间隙。
参考图1,根据各种实施例,一半导体装置包括具有多个晶体管栅极结构400形成于其上的一半导体基板100。该栅极结构400与同样形成于基板上的多个鳍片(未予图示)正交排列。
半导体基板100可以为例如硅或含硅材料的一半导体材料,包括一块体基板。含硅材料包括但不限于单晶硅、多晶硅、单晶硅锗(SiGe)、或多晶硅锗、掺杂碳的硅(Si:C)、非晶硅、以及上述各种材料的组合及多层。本文所使用的术语“单晶”表示一晶体固定,其中整个样品的晶格基本上是连续的,并与基本没有晶粒边界(grain boundaries)的样品的边缘基本上连续。样品硅基板包括绝缘体上硅(silicon-on-insulator;SOI)基板、蓝宝石上硅(silicon-on-sapphire;SOS)基板等。
基板100不限于含硅材料,基板100可以包含其他半导体材料,包括Ge以及化合物半导体,如GaAs、InAs以及其他类似的半导体。在所示的实施例中,基板100为一绝缘体上半导体(SOI)基板,其从底部至顶部具有一支撑基板110、一隔离层120、以及一半导体材料层(未予图示)。
基板100可具有本领域中通常使用的尺寸。基板可以包括一半导体晶圆(wafer)。示例性晶圆直径包括但不限于50,100,150,200,300及450毫米(mm),包括上述任何数值之间的范围。总体的基板厚度的范围可从250微米至1500微米,虽然在具体的实施例中,基板厚度对应于硅CMOS工艺中通常使用的厚度尺寸,在725至775微米的范围内。该支撑基板110可例如包括(100)取向的硅或(111)取向的硅。
隔离层120可包括一绝缘体上半导体(SOI)基板的埋置氧化物(buried oxide;BOX)层,或一块硅基板的一氧化层。隔离层120的厚度范围可从30至300纳米,例如30、50、100、150、200、250或300纳米,包括上述任意数值之间的范围。隔离层120可例如包括二氧化硅(SiO2)。可替换的,隔离层120可包括氮化硅、氮氧化硅、低K材料,或这些材料的任意适合的组合。
典型地低K材料包括但不限于无定形碳(amorphous carbon),氟掺杂氧化物,碳掺杂氧化物,SiCOH或SiBCN。市售的低K介电质产品和材料包括道康宁(Dow Corning)的SiLKTM以及porous SiLKTM,实用材料公司(Applied Materials)的Black DiamondTM,德克萨斯仪器公司(Texas Instrument)的CoralTM以及台湾积体电路制造公司(TSMC)的BlackDiamondTM及CoralTM。如本文所述,低K材料具有小于二氧化硅的介电常数的一介电常数。设置于隔离层120上方的是一半导体材料层,其可被图案化以限定多个鳍片。
设置于隔离层120上方的半导体材料层可以包括与基板100关联的上述任何半导体材料。形成半导体材料层并可用于形成半导体鳍片的示例性半导体材料包括硅(Si)、锗(Ge)、硅锗(SiGe)、第III-V族化合物半导体(如GaAs,GaN,GaP,InAs,InSb,ZnSe与ZnS)、以及第II-VI族化合物半导体(如CdSe,CdS,CdTe,ZnSe,ZnS与ZnTe)。
支撑基板110和绝缘体层120共同作为一基板,其上设置有多个半导体鳍片。在各种实施例中,多个半导体鳍片中的每一个沿着与所示的具有一基本矩形垂直截面形状的一栅极堆栈400正交的一垂直方向延伸。如本文所述,一“基本矩形形状”是一种与一矩形形状不同的一种形状,这仅仅是由于光刻及其工艺不超过3纳米。该基本矩形垂直横截面形状是包括一垂直方向以及一横向方向的一平面内的一形状。多个鳍片可以具有相同或基本相同的尺寸,即高度及/或宽度。如本文所述,基本相同尺寸的变化小于10%,例如小于5%、2%或1%。
如本文所述,一“鳍片”指代具有彼此平行的一对垂直侧壁的一连续的半导体材料。如本文所述,如果存在一个垂直平面,其表面不超过表面的均方根粗糙度三倍以上,则该表面使“垂直”的。多个鳍片中的每一个可以包括沿纵向延伸的一单晶半导体材料。如本文所述,一“纵向”是沿一物体无尽延伸的一水平方向。一“横向”是垂直于该纵向的一水平方向。
各鳍片的该基本矩形垂直的横截面形状平行于绝缘体层120的一顶面的一水平界面。如图1所示,根据某些实施例,鳍片高度用一虚线表示,该虚线低于外延源极/漏极区域(source/drain regions)600的高度。
形成鳍片的半导体材料可以掺杂、未掺杂、或者包含其中的掺杂和未掺杂区域。半导体鳍片中的各掺杂区域可以具有相同或不同的掺杂浓度及/或导电率。存在的掺杂区域可以通过例如离子植入、气相掺杂而形成,或通过存在于用于形成鳍片的材料中的掺杂剂而形成。例如,由半导体材料层所定义的鳍片可以包括于形成鳍片之前的一掺杂剂。举例来说,半导体层及由此形成的鳍片可进行初步且均匀的掺杂,并具有1x1015atoms/cm3(原子/立方厘米)至1x1018atoms/cm3的一掺杂浓度范围。
如本领域技术人员所悉知,一栅极结构400形成于鳍片的顶面及相对侧壁的上方。栅极结构包括一栅极介电质以及一栅极导电体。栅极介电层可通过热氧化而形成,一般在750-800℃,或者,可以通过沉积一共形介电层而形成。术语“共形层”以及“共形沉积层(conformally deposited layer)”表示一个层,其具有不超过该层的一平均厚度的20%(例如小于5%,10%或20%)的一厚度。根据某些实施例中,栅极介电层可以包括二氧化硅、氮化硅、氮氧化硅、高K介电质、及/或其他适合材料。
如本文所述,一高K材料具有大于二氧化硅的介电常数的一介电常数。一高K介电质可以包括二元或三元化合物,例如氧化铪(HfO2)。其他典型地高K介电质包括但不限于ZrO2,La2O3,Al2O3,TiO2,SrTiO3,BaTiO3,LaAlO3,Y2O3,HfOxNy,HfSiOxNy,ZrOxNy,La2OxNy,Al2OxNy,TiOxNy,SrTiOxNy,LaAlOxNy,Y2OxNy,SiOxNy,SiN,及其硅酸盐,或其合金。x的每个值可以独立地从0.5到3不等,y的每个值可以独立地从0到2不等。
栅极介电质可以通过一适当的工艺进行沉积,例如原子层沉积(atomic layerdeposition;ALD)、化学气相沉积(chemical vapor deposition;CVD)、物理气相沉积(physical vapor deposition;PVD)、热氧化、紫外臭氧氧化(UV-ozone oxidation)、或其组合。栅极介电质的厚度范围可从1纳米至10纳米,例如1纳米、2纳米、4纳米、6纳米、8纳米或10纳米,包括上述任意一个数值之间的范围。于各种实施例中,栅极介电质包括二氧化硅的一薄层(例如0.5纳米)或高K介电材料的一上覆层。
一栅极电极形成于一个(或多个)栅极介电层的上方。该栅极电极可包括一导电材料,例如多晶硅,也可以使用非晶硅、非晶硅与多晶硅的一组合,多晶硅锗,或任何其他适合的材料。当该栅极电极层为一硅材料时,其可作为一掺杂层(原位掺杂)予以沉积。
此外,在一些实施例中,其可能有利于采用一金属栅极导电体层,例如Al、W、Cu、Ti、Ta、W、Pt、Ag、Au、Ru、Ir、Rh以及Re,导电材料的合金,例如Al-Cu,一导电材料的硅化物,例如W硅化物、以及Pt硅化物,或其他导电金属化合物,例如TiN、TiC、TiSiN、TiTaN、TaN、TaAlN、TaSiN、TaRuN、WSiN、NiSi、CoSi及其组合。栅极电极可以包括一个或多个这样的材料层,例如,包括一共函数金属层及/或一衬垫层的一金属堆栈。于各种实施例中,功函数金属层的厚度为3至5纳米。在图式中,例如为一钨层的一金属栅极导电体420覆盖统一标识为410的栅极介电质以及功函数金属层。
栅极电极(例如功函数金属层)可以是形成于结构的暴露表面上方的一共形层,然后进行选择性移除以定义所需的几何形状。栅极电极可使用一传统沉积工艺而形成,如ALD、CVD、金属有机化学气相沉积(metalorganic chemical vapor deposition;MOCVD)、分子束外延(molecular beam epitaxy;MBE)、PVD、溅射、电镀、蒸镀、离子束沉积、电子束沉积、激光辅助沉积、或化学溶液沉积。
根据某些实施例,下一步骤是形成一薄的低K介电层于栅极导电体的侧壁上以及形成一介电层于栅极堆栈400的顶部的上方。氮化物间隔件510形成于栅极400的侧壁上,一氮化物盖体520形成于栅极400的顶面的上方。于不同的实施例中,氮化物间隔件510包括硅碳氮化合物(silicon carbon nitride;SiCN),且氮化物盖体520包括氮化硅(例如Si3N4)。非晶氢化硅碳氮化合物膜可由例如硅烷、甲烷和氮气的气体混合物通过RF-PECVD予以制备。
一选择性蚀刻可用于在邻接鳍片、氮化物间隔件510、以及栅极堆栈400的半导体层130内形成空腔150。该空腔形成蚀刻可以是各向同性(isotropic)或各向异性(anisotropic)的蚀刻,其不会完全削低鳍片。在各种实施例中,空腔150通过半导体层130完整地延伸至隔离层120。
然后,使用一选择性外延工艺,使用一半导体材料回填空腔150以形成如图1所示的邻接鳍片的源极与漏极区域600,应当了解的是,当一个区域被定义为一源极区域或一漏极区域时,其仅是为了方便源极区域以及漏极区域可以进行互换,正如本领域技术人员所悉知。
术语“外延”、“外延的”及/或“外延生长及/或沉积”指代一半导体材料的一沉积表面上的一半导体材料层的形成,其中,所生长的半导体材料层与沉积表面的半导体材料具有相同的结晶习性。例如,在一外延沉积工艺中,由源气体提供的化学反应物的控制以及***参数的设置使得沉积原子落至沉积表面上,并保持通过表面扩散的足够的流动性,以根据沉积表面的原子的结晶方向进行自我定向。因此,一外延半导体材料与形成于其上的沉积表面具有相同的结晶特性。例如,沉积于一(100)晶体表面的一外延半导体材料将具有一(100)的取向。源极/漏极区域600可以包括硅、硅锗、或其他适合的半导体材料。
用于形成硅源极(或漏极)区域的一示例性硅外延工艺使用一气体混合物,其在600-800℃的沉积(如基板)温度下包括氢气(H2)和二氯硅烷(SiH2Cl2)。其他用于硅外延的适合的气源包括四氯化硅(SiCl4)、硅烷(SiH4)、三氯氢硅(SiHCl3)、和其他氢还原氯硅烷(SiHxCl4-x)。
在各种实施例中,该选择性外延工艺将一外延层直接沉积在空腔150内暴露的隔离层120上。选择性外岩层可使用适于选择性外延的分子束外延或化学气相沉积工艺而形成。源极与漏极区域600的厚度范围可从15至40纳米,例如15、20、25、30、35、或40纳米,包括上述任意数值之间的范围。
在各种实施例中,源极与漏极区域被掺杂。例如,在外延生长期间可能发生掺杂,即,源极与漏极区域被原位掺杂。正如本领域技术人员所悉知,掺杂改变了一固有半导体在热平衡中的电子和空穴载流子(hole carrier)浓度。一掺杂层或区域可为p型或n型。一p型掺杂用于制造一PFET,以及一n型掺杂用于制造一NFET。
如本文所述,“p型”是指在一本征半导体中加入杂质,从而产生价电子的不足。对于硅,例如p型掺杂剂,及杂质,包括但不限于硼、铝、镓和铟。如本文所述,“n型”指在一本征半导体中加入自由电子的杂质。对于硅,例如n型掺杂剂,即杂质,包括但不限于锑、砷、和磷。掺杂剂可以通过等离子体(plasma)掺杂被引入,或通过例如原位掺杂,即在用于形成该层的工艺序列期间被引入。
例如,一掺杂去,如源极及/或漏极区域,可原位掺杂砷或磷以形成一n型区域。源极与漏极区域600内的掺杂浓度范围可从1×1019atoms/cm3至1×1022atoms/cm3,例如1×1020atoms/cm3至1×1021atoms/cm3。于其他实施例中,一掺杂区域被原位掺杂硼以形成一p型区域。源极与漏极区域内的掺杂浓度范围可从1×1019atoms/cm3至1×1022atoms/cm3,例如1×1020atoms/cm3至1×1021atoms/cm3。
一可选的推进退火(drive-in annealing)可用于扩散掺杂剂种类并生成一期望的掺杂分布。于各种实施例中,源极与漏极区域600内的掺杂原子可以使用一后外延退火(例如在600至1400℃的温度)而扩散到相邻的鳍片中以生成靠近源极与漏极区域600的鳍片内的一掺杂分布。鳍片内的掺杂分布可以是恒定的或可变的。例如,在鳍片内的掺杂浓度可以随着沿鳍片的一中心轴的一最小掺杂浓度(例如1x1019至1x1022atoms/cm3)以及其相对表面上的一最大掺杂浓度(例如1x1019至1x1022atoms/cm3)而横向变化。
参考图2,根据另一实施例中,一半导体结构包括一基板100,其具有形成于该基板的一隔离层120上的多个鳍片202。于所述的实施例中,外延源极与漏极区域包括形成于位于其相对两端的鳍片202上方的凸起(raised)有源区域310a,310b,同时一栅极堆栈400形成于定义源极与漏极区域之间的一通道的鳍片202的上方。
未转换为一源极区域或一漏极区域的各半导体鳍片202的部分构成一通道区域。通道区域整体上作为一场效应晶体管的一通道。源极区域包括整体上作为场效应晶体管的一源极的凸起源极区域310a。漏极区域包括整体上作为场效应晶体管的一漏极的凸起漏极区域310b。
可以形成与源极、漏极以及栅极形成接触的电性接触件。根据各种实施例中,形成接触件的方法参考图3A至图3I予以描述。显示电接触件的典型结构在图1以及图4至图9中予以显示,其为垂直于鳍片的横截面视图。
参考图3A,其为显示制造具有设置于半导体基板100上方的栅极堆栈400以及设置于邻接栅极堆栈400的基板的隔离层120上方的外延源极/漏极区域600的一中间阶段的一后替换金属栅极(post-replacement metal gate;RMG)装置架构的一横截面图,包括栅极电极层410以及金属栅极导电体420的栅极堆栈400在氮化物间隔件510以及一牺牲氧化物层650的顶面下方被凹陷。
如图3B所示,一覆盖氮化层520沉积于图3A的结构的上方,即直接位于牺牲氧化物层650以及凹陷的栅极堆栈400的上方。氮化层520使用一化学机械抛光工艺进行平坦化。化学机械抛光(chemical mechanical polishing;CMP)是同时使用化学反应以及机械力两者以移除材料并平坦化一表面的一材料移除工艺。牺牲氧化物层650可以作为一平坦化蚀刻停止层,其露出牺牲氧化物层650的一顶面。
如图3C所示,牺牲氧化物层650使用一选择性蚀刻予以移除,露出外延层600的顶面。可用于相对于栅极以及源极/漏极区域选择性移除牺牲氧化物层650的典型地蚀刻工艺包括一缓冲氧化物(buffered oxide;HF)湿蚀刻或一SiconiTM等离子体刻蚀。位于相邻的栅极结构之间的间隔(S)的范围从10纳米至50纳米,例如10、20、30、40或50纳米,包括上述任意数值之间的范围。
源极/漏极硅化物区域710形成于源极/漏极区域600上。硅化物区域710的形成可以包括一自对准硅化物(自对准多晶硅化物)工艺。硅化物工艺包括一金属层(未予图示)的覆盖沉积,随后是退火以使金属层与源极/漏极区域600内的底层硅之间发生一反应。可选的,可以移除金属层的未反应部分。金属层可包括钛、镍、钴、氮化钛等,及它们的组合。例如,金属层可以包括一钛层(5纳米)以及一氮化钛层(10纳米)。在退火期间,钛金属与硅反应生成硅化钛。
参考图3D,然后沉积一覆盖金属层700于栅极堆栈400的上方,即与氮化物间隔件510以及氮化物盖体520接触,以及位于接触源极/漏极区域600的上方并接触硅化物区域710。金属层700可通过蒸发、溅射沉积、或其他已知的物理气相沉积(PVD)技术予以沉积,然后使用化学机械抛光进行平坦化。
参考图3E,一掩膜层810以及光阻层820相继沉积于金属层700的上方。掩膜层810可具有10至100纳米的一厚度,并包括例如SiON,SiN或SiO2。光阻层820可包括一正色调光致抗蚀剂组合物、一负色调光致抗蚀剂组合物、或一混合色调光刻抗蚀剂组合物。该层的光阻材料可以通过一沉积工艺(例如旋涂)而形成。
沉积的光阻最后进行一照射图案化,并使用一传统抗蚀显影剂显影曝光的光阻材料。由图案化的光阻材料所提供的开口830的图案随后利用至少一图案转移蚀刻工艺被转移至底层材料层或材料层中。
图案转移蚀刻工艺可以为一各向同性蚀刻或一各向异性蚀刻。在各种实施例中,一干蚀刻工艺,可以使用例如反应离子蚀刻(reactive ion etching;RIE)。于其他实施例中,可以使用一湿化学蚀刻剂。在其他的实施例中,可以使用干蚀刻以及湿蚀刻的组合。如图3F所示,金属层700的一基本各向异性的图案转移蚀刻止于氮化物间隔件510以及氮化物盖体520上以定义隔离孔840。图案化的光阻可在蚀刻工艺期间被消耗,在完成蚀刻金属层之后予以剥离,或通过灰化予以移除。
根据各种实施例,可使用一氮等离子体处理以形成位于金属层700的暴露的表面上方(即隔离孔内部)的一薄(例如2-4纳米)的氮化物钝化层。如图1以及图4至图9所示,然后隔离孔840可至少部分地被填充一共形或非共形隔离介电质900。根据各种实施例,隔离介电质900的共形沉积基本上填充了隔离孔840,而隔离介电质900的非共形沉积将部分填充形成位于其中的一气隙的隔离孔940。
例如,电性稳定的二氧化硅的共形层可在氧化亚氮的高流量下使用硅烷(SiH4)和氧化亚氮(N2O)源气体通过化学气相沉积予以沉积。在图示中,金属层700的剩余部分提供与源极与漏极区域600接触的接触结构。虽然没有说明,但应可理解,金属层700的其他剩余部分可提供与栅极的接触。
于图3E及图3F所示的实施例中,隔离孔840的宽度(w1)小于或等于栅极堆栈400的宽度(W)。于将一介电材料900共形填充隔离孔840之后的一相应结构如图1所示,其中,介电材料900基本填充隔离孔840,并设于栅极堆栈400的上方。一化学机械抛光步骤可相对掩膜层810的一顶面或金属层700的一顶面而平坦化该介电层900。
根据另一实施例中,如图3G至图3I所示,隔离孔840的宽度(w2)大于栅极堆栈400的宽度(W)。因此,如图3H所示,作为一实施例,金属层700的一各向异性图案转移蚀刻可停止于定义栅极堆栈400上方的隔离孔840的氮化物间隔件510与氮化物盖体520上。参考图3I,各向异性图案转移蚀刻也可以选择性移除相邻于栅极堆栈400的金属层700的部分,并使隔离孔840延伸至栅极堆栈400的一顶面下方的一深度(d),其中,假设蚀刻图案与栅极堆栈对齐,延伸隔离孔842的厚度(t)可以表示为(w2-W)/2。然而,用一隔离介电质900填充该隔离孔840与该延伸(extended)隔离孔842。
于共形填充隔离孔840以及延伸隔离孔842之后的一相应结构如图4所示,其中,介电材料900设于栅极堆栈400的上方以及栅极堆栈侧壁的一部分的上方,即直接位于栅极与金属层之间的氮化物间隔件510的上方。应理解的是,延伸隔离孔842自栅极堆栈400的顶面的下方延伸,延伸隔离孔842的深度(d)小于源极/漏极区域600上方的栅极堆栈的高度,使得介电材料900不直接接触源极/漏极区域600或源极/漏极硅化物区域710。
如图5所示,气隙852可以使用一定向沉积工艺相邻于栅极堆栈400形成于延伸隔离孔842内,使得介电材料900填充隔离孔840以及仅该延伸隔离孔842的一上部。在各种实施例中,气隙852的宽度可为1至10纳米。
根据另一实施例,作为设置于栅极400的侧面的上方的气隙的替代品,或除了栅极400的侧面的上方的气隙,气隙可形成于栅极的顶部的上方。具有设置于栅极堆栈的顶部的上方的隔离介电质900内的一气隙的示例性装置结构如图6至图9所示。
图6至图8所示的结构类似于图1、图4及图5所示的结构。然而,一非共形介电层沉积位于栅极400的顶部上方以及金属层700的暴露侧壁上方的隔离孔840内,以代替共形沉积介电层900以基本填充隔离孔840。如图6所示,例如,非共形工艺将形成位于栅极上方的相邻金属接触件700a,700b,700c之间的一气隙850。在不同实施例中,对装置架构进行配置使得金属接触件700a,700b,700c位于栅极的一顶面的上方。
根据不同的实施例中,一非共形介电层可包括一等离子增强化学气相沉积(plasma-enhanced chemical vapor deposited;PECVD)氧化物,其将沉积于氮化物盖体520的顶面上方以及隔离孔840内的金属层700的侧壁上方。可替换的,一非共形介电层可使用一高密度等离子体(high density plasma;HDP)沉积工艺予以沉积。
参考图7及图8,气隙850及852具有一高度H以及一宽度W。气隙的高度范围可例如从15至50纳米。气隙的宽度(W)范围例如从1至50纳米。在各种实施例中,气隙852的高度(H)为栅极堆栈的高度的30%至95%。在不同实施例中,气隙852的宽度(W)是侧壁间隔件510至金属接触件的距离的30%至100%。
参考图9,其显示了另一实施例,其中,介电层900向形成从栅极的上方延伸至栅极侧壁的一互连的气隙542的隔离孔中部分延伸。这样一个合并的气隙854或离散的气隙850,852提供相邻的导电元件之间稳定的电性隔离,以减少中间接触电容从而提高半导体装置(包括FinFET装置)的性能。
本申请的FinFET可以与各种不同的电路结合,例如高性能逻辑、低功耗逻辑或高密度存储装置,包括高密度多千兆位(multi-gigabit)DRAM。此外,基于FinFET的装置可以结合其他元件,例如电容器、电阻器、二极管、记忆单元等。
本申请提供了一种装置架构以及制造方法,克服了传统结构以及方法的许多不足之处。具体而言,该装置结构是通过一个稳定的方法启用的,并提供了形成表现出最小信号路径电容的先进节点的FinFET装置的能力。
文本描述了与一FinFET装置有关的涉及形成气隙的各种实施例,应了解的是,先金属工艺及其相应结构可与其他逻辑平台(包括平面(二维)晶体管结构)的制造一起使用。
如本文所述,单数形式的“一”、“一个”以及“该”包括复数指代,除非上下文另有明确规定。因此,例如,一“介电层”包括具有两个或多个这样的“介电层”的示例,除非上下文另有清楚的指示。
除非另有明确说明,否则本文所阐述的任何方法绝不意味着要求以特定顺序执行其步骤。因此,如果一方法权利要求实际上没有按照其步骤进行说明,或者在权利要求或者说明书中没有具体说明步骤仅限于一特定顺序,则不意味着任何特定的顺序。任何一个权利要求中任何列举的单个或多个特征或方面可以与任何其他权利要求中的任何其他列列举的特征或方便进行组合或置换。
如本文所述,一元件例如位于一基板或其他层“上”或“上方”或“上方所设置”的一层或区域是指形成该基板或层的一表面的上方、或接触该基板或层的一表面。例如,当被记载或描述为一层设置于一基板或其他的上方,应该设想在该层与该基板之间可选择地存在中间结构层。相反,当一元件被称为“直接位于另一元件上”,或“直接位于另一元件的上方”则没有中间元件的存在。还应了解的是,当一元件被称为“位于另一元件之下”或“另一元件的下方”,其可以是直接位于另一元件之下或另一元件的下方,或可能存在中间元件。相仿,当一元件被称为“直接位于另一元件之下”或“直接位于另一元件的下方”,则没有中间元件的存在。
虽然实施方案的各种特征、元件、或步骤是通过使用替换短语“包括”予以揭露,应理解的是,其也意味着包括在替换性实施例中,上述各种特征、元件、或步骤可以通过使用替换短语“主要由”或“组成”予以描述。因此,在例如在替换实施方案中,由二氧化硅和一高K介电质组成的一栅极介电质意味着包括主要由二氧化硅以及一高K介电质所组成的一栅极介电质的实施例,以及由二氧化硅以及一高K介电质所组成的一栅极介电质的实施例。
对于本领域技术人员显而易见的是,在不脱离所示实施例的精神或范围的情况下,可以进行各种修改和变化。通过所公开的结合本发明的精神和实质的各具体实施例的组合,子组合和变形,本领域技术人员可以想到,本发明应被解释为包括在所附权利要求范围及其等价范围内的所有内容。
Claims (16)
1.一种形成半导体装置的方法,其特征为,该方法包括:
形成一栅极结构于一半导体鳍片的一通道区域的上方,其中,一源极区域与一漏极区域位于该通道区域的相对侧上;
形成介电间隔件于该栅极结构的侧壁上方以及一介电盖体于该栅极结构的一顶部上方;
形成一导电层于该介电盖体的上方以及位于相邻的栅极结构的该介电间隔件之间的该源极区域与该漏极区域的上方;
形成通过该导电层至该介电盖体的一顶面的一隔离孔;以及
形成一介电层于该隔离孔内。
2.根据权利要求1所述的方法,其特征为,形成该介电层包括非共形沉积该介电层于该隔离孔内以及形成一气隙于该栅极结构的该顶部上方的该介电层内。
3.根据权利要求1所述的方法,其特征为,该隔离孔从该介电间隔件的侧壁上方延伸。
4.根据权利要求3所述的方法,其特征为,形成该介电层包括向该隔离孔中非共形沉积该介电层,并形成一气隙于位于该介电间隔件的侧壁上方的该介电层中。
5.根据权利要求3所述的方法,其特征为,形成该介电层包括向该隔离孔中非共形沉积该介电层,并形成一气隙于位于该栅极结构的该顶部上方以及该介电间隔件的侧壁上方的该介电层中。
6.根据权利要求5所述的方法,其特征为,该栅极结构的该顶部上方的该气隙与该介电间隔件的该侧壁上方的该气隙合并。
7.一种半导体装置,其特征为,该半导体装置包括:
一半导体鳍片,其位于一半导体基板的上方;
一栅极结构,其位于该半导体鳍片的一通道区域的上方;
源极区域与漏极区域,其位于该通道区域的相对侧上;
介电间隔件,其位于该栅极结构的侧壁上方,及一介电盖体,其位于该栅极结构的该顶部上方;
一导电层,其位于相邻的栅极结构的该介电间隔件之间的该源极区域与该漏极区域的上方;以及
一隔离介电质,其位于该栅极结构的顶部的上方,其中,该隔离介电质包括一气隙。
8.根据权利要求7所述的半导体装置,其特征为,该气隙的一宽度的范围为该栅极结构的一宽度的30%至95%。
9.根据权利要求7所述的半导体装置,其特征为,该隔离介电质从该介电间隔件的侧壁上方延伸。
10.根据权利要求9所述的半导体装置,其特征为,从该介电间隔件的该侧壁上方延伸的该隔离介电质包括一气隙。
11.根据权利要求10所述的半导体装置,其特征为,位于该栅极结构的该顶部上方的该气隙与位于该介电间隔件的该侧壁上方的该气隙合并。
12.根据权利要求10所述的半导体装置,其特征为,从该介电间隔件的该侧壁上方延伸的该隔离介电质不接触该源极区域与漏极区域。
13.根据权利要求10所述的半导体装置,其特征为,位于该介电间隔件的该侧壁上方的该气隙的该高度的范围为该栅极结构的一高度的30%至95%。
14.根据权利要求7所述的半导体装置,其特征为,该导电层的一顶面位于该栅极结构的一顶面的上方。
15.根据权利要求7所述的半导体装置,其特征为,该介电间隔件包括硅碳氮化合物以及该介电盖体包括氮化硅。
16.根据权利要求7所述的半导体装置,其特征为,该隔离介电质包括二氧化硅。
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