CN107658341B - Groove type power MOSFET and preparation method thereof - Google Patents
Groove type power MOSFET and preparation method thereof Download PDFInfo
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- CN107658341B CN107658341B CN201710891945.0A CN201710891945A CN107658341B CN 107658341 B CN107658341 B CN 107658341B CN 201710891945 A CN201710891945 A CN 201710891945A CN 107658341 B CN107658341 B CN 107658341B
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- 238000002360 preparation method Methods 0.000 title claims description 6
- 238000002347 injection Methods 0.000 claims abstract description 37
- 239000007924 injection Substances 0.000 claims abstract description 37
- 239000007943 implant Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000011065 in-situ storage Methods 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 16
- 150000002500 ions Chemical class 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention discloses a groove type power MOSFET, which comprises an N + substrate, an N-epitaxial layer, a P-body injection layer and a P + injection layer which are sequentially arranged from bottom to top, wherein a plurality of shallow grooves which are distributed at intervals and penetrate through the P + injection layer are etched on the P-body injection layer; a metal layer is deposited over the P + implant layer, filling each shallow trench and connecting the N + source layer to the P + implant layer. Its preparing process is also disclosed. The invention effectively reduces the space width of the device and reduces the on-resistance of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor device structures, in particular to a trench type power MOSFET and a preparation method thereof.
Background
MOSFET (Power Metal Oxide Semiconductor Field-effect Transistor) is widely applied in the fields of 4C (Communication, Computer, Consumer, automobile) and the like due to the advantages of high switching speed, good frequency performance, high input impedance, small driving Power, good temperature characteristic, no secondary breakdown problem and the like.
The trench power MOSFET device is formed by a plurality of MOSFET cells, each MOSFET cell is called a cell, and the pitch (pitch) between cells directly affects the important electrical parameter of the power MOSFET, i.e., the drain-source on-state resistance Rdson. The drain-source on-state resistance Rdson is the total resistance between the drain and the source per unit area of the device in an on state, and determines the maximum rated current and power loss of the device, especially in medium-low power MOSFET products.
The pitch width on the surface of a trench power MOSFET is limited by two dimensions, one is the width of the gate trench itself, and the other is the Source contact hole and the pitch of the contact hole to the gate trench. Since the reduction of the on-resistance of the device can be facilitated by reducing the pitch (pitch) width of the device, how to reduce the pitch (pitch) width of the device to achieve the purpose of reducing the on-resistance of the device is a technical problem that needs to be solved urgently by those skilled in the art.
The applicant has therefore made an advantageous search and attempt to solve the above-mentioned problems, in the context of which the technical solutions to be described below have been created.
Disclosure of Invention
The invention aims to solve one of the technical problems that: provided is a trench power MOSFET capable of reducing the pitch (pitch) width of a device.
The second technical problem to be solved by the present invention is: a preparation method for preparing the groove type power MOSFET is provided.
The trench power MOSFET as the first aspect of the present invention comprises an N + substrate, an N-epitaxial layer, a P-body injection layer and a P + injection layer sequentially arranged from bottom to top, it is characterized in that a plurality of shallow grooves which are distributed at intervals and penetrate through the P + injection layer are etched on the P-body injection layer, the bottom of each shallow groove is provided with an N + source electrode layer, etching a grid groove which sequentially penetrates through an N + source electrode layer and a P-body injection layer from top to bottom at the middle position of each shallow groove on the N-epitaxial layer, wherein a grid oxygen layer is arranged on the bottom surface and the peripheral side surface of each grid groove, in-situ doped polysilicon is filled in each grid groove, the top surface of the in-situ doped polysilicon filled in the grid groove is flush with the upper surface of the N + source electrode layer, and a silicon dioxide layer is attached to the top surface of the in-situ doped polysilicon; depositing a metal layer on the P + implant layer, the metal layer filling each shallow trench and connecting the N + source layer and the P + implant layer.
In a preferred embodiment of the present invention, the metal layer is a metal aluminum layer.
The manufacturing method for manufacturing the trench power MOSFET as the second invention of the present invention includes the steps of:
(1) preparing an N + substrate, and extending an N-epitaxial layer outside the upper surface of the N + substrate;
(2) injecting P-body ions into the upper surface of the N-epitaxial layer to form a P-body injection layer, and injecting P + ions into the upper surface of the P-body injection layer to form a P + injection layer;
(3) depositing a layer of Si on the upper surface of the P + injection layer3N4Dielectric layer；
(4) In the presence of Si3N4A plurality of photoresists are adhered to the upper surface of the dielectric layer at intervals;
(5) etching the position of the P + injection layer between two adjacent photoresists to the P-body layer to form a plurality of shallow grooves, wherein the depth of each shallow groove is less than that of the Si3N4The sum of the thicknesses of the dielectric layer, the P + injection layer and the P-body injection layer;
(6) injecting N + ions into the bottom of each shallow groove, forming an N + source electrode layer at the bottom of the shallow groove, and adhering the N + source electrode layer on the Si3N4Removing the photoresist on the dielectric layer;
(7) depositing a layer of Si on the N + source layer in each shallow trench3N4Layer of and to said Si3N4Etching the central part of the layer to the upper surface of the N + source electrode layer to ensure that the etched Si layer3N4Forming a grid groove etching window;
(8) etching the N + source electrode layer in each shallow groove by using the grid groove etching window, and etching the N + source electrode layer into the N-epitaxial layer to form a plurality of grid grooves;
(9) oxidizing each grid groove to form a grid oxide layer on the bottom surface and the peripheral side surfaces of the grid groove, and depositing in-situ doped polycrystalline silicon on the upper surface of the P + injection layer and in each grid groove;
(10) etching the in-situ doped polysilicon on the upper surface of the P + injection layer and in the gate trench etching window to make the top surface of the remaining in-situ doped polysilicon flush with the upper surface of the N + source layer;
(11) depositing a silicon dioxide layer on the top surface of the remaining in-situ doped polysilicon;
(12) removing Si on the P + implantation layer3N4Dielectric layer and Si in each shallow trench3N4A layer;
(13) depositing a metal layer on the P + implant layer, the metal layer filling each shallow trench and connecting the N + source layer and the P + implant layer.
In a preferred embodiment of the present invention, the metal layer is a metal aluminum layer.
Due to the adoption of the technical scheme, the invention has the beneficial effects that: the space width of the device is effectively reduced, the on-resistance of the device is reduced, and the on-performance of the device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic view of an N-epitaxial layer of the present invention formed on an N + substrate.
Fig. 2 is a schematic diagram of the present invention forming a P-body layer and a P + implant layer on an N-epitaxial layer.
FIG. 3 is a process of depositing a layer of Si over the P + implant layer in accordance with the present invention3N4Schematic illustration of a dielectric layer.
FIG. 4 shows the present invention on Si3N4And sticking photoresist on the dielectric layer.
FIG. 5 is a schematic diagram of the present invention for forming shallow trenches by etching the P + implantation layer, the P-body implantation layer and the N-epitaxial layer.
FIG. 6 is a schematic diagram of the present invention in which N + ions are implanted into each shallow trench to form an N + source layer.
FIG. 7 shows the deposition of Si on the N + source layer according to the present invention3N4Layer of and to the Si3N4The layer is etched to form a schematic diagram of a gate trench etch window.
FIG. 8 is a schematic diagram of the present invention using a gate trench etch window to etch the N + source layer in each shallow trench to form a gate trench.
Figure 9 is a schematic diagram of the present invention oxidizing each gate trench and depositing in-situ doped polysilicon.
Fig. 10 is a schematic diagram of the present invention after etching the in-situ doped polysilicon.
Fig. 11 is a schematic illustration of the present invention depositing a silicon dioxide layer on the remaining in situ doped polysilicon.
FIG. 12 shows Si removal according to the present invention3N4Dielectric layer and Si3N4Schematic after layer.
Fig. 13 is a schematic diagram of the structure of a finished trench power MOSFET of the present invention.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.
Referring to fig. 13, the trench power MOSFET is shown, which includes an N + substrate 100, an N-epitaxial layer 200, a P-body implant layer 300 and a P + implant layer 400 arranged in sequence from bottom to top, a plurality of shallow trenches 310 are etched on the P-body implantation layer 300, the shallow trenches 310 are distributed at intervals and penetrate through the P + implantation layer 400, an N + source layer 500 is arranged at the bottom of each shallow trench 310, etching a gate trench 210 which sequentially penetrates through the N + source layer 500 and the P-body injection layer 300 from top to bottom at the middle position of each shallow trench 310 on the N-epitaxial layer 200, wherein a gate oxide layer 211 is arranged on the bottom surface and the peripheral side surface of each gate trench 210, each gate trench 210 is filled with in-situ doped polysilicon 600, the top surface of the in-situ doped polysilicon 600 filled in the gate trench 210 is flush with the upper surface of the N + source layer 500, and a silicon dioxide layer 700 is attached to the top surface of the in-situ doped polysilicon 600; a metal layer 800 is deposited on the P + implant layer 400, and the metal layer 800 fills each shallow trench 310 and connects the N + source layer 500 and the P + implant layer 400, wherein the metal layer 800 is a metal aluminum layer in this embodiment.
The preparation method for preparing the groove type power MOSFET comprises the following steps:
(1) referring to fig. 1, an N + substrate 100 is prepared, and an N-epitaxial layer 200 is extended outside an upper surface of the N + substrate 100;
(2) referring to fig. 2, P-body ions are implanted on the upper surface of the N-epitaxial layer 200 to form a P-body implant layer 300, and P + ions are implanted on the upper surface of the P-body implant layer 300 to form a P + implant layer 400;
(3) referring to fig. 3, a layer of Si is deposited on the upper surface of the P + implant layer 4003N4A dielectric layer 910;
(4) see FIG. 4 at Si3N4A plurality of photoresists 920 are uniformly adhered on the upper surface of the dielectric layer 910 at intervals;
(5) referring to fig. 5, the P + implantation layer 400 is etched between two adjacent photoresists 920, and the P + implantation layer 400 is etched into the P-body implantation layer 300 to form a plurality of shallow trenches 310, wherein the depth of each shallow trench 310 is less than that of the Si3N4The sum of the thicknesses of the dielectric layer 910, the P + injection layer 400, and the P-body injection layer 300;
(6) referring to fig. 6, N + ions are implanted into the bottom of each shallow trench 310, so that an N + source layer 500 is formed at the bottom of the shallow trench 310 and is attached to Si3N4Removing the photoresist 920 on the dielectric layer 910;
(7) referring to fig. 7, a layer of Si is deposited in each shallow trench 310 on the N + source layer 5003N4Layer 930 and p-Si3N4The central portion of layer 930 is etched to the upper surface of N + source layer 500, resulting in etched Si3N4Forming a gate trench etch window 311;
(8) referring to fig. 8, the gate trench etching window 311 is used to etch the N + source layer 500 in each shallow trench 310 into the N-epitaxial layer 200, so as to form a plurality of gate trenches 210, wherein the bottom of each gate trench 210 does not penetrate through the N-epitaxial layer 200 and is located in the N-epitaxial layer 200;
(9) referring to fig. 9, each gate trench 210 is oxidized such that a gate oxide layer 211 is formed on the bottom surface and the peripheral side surface of the gate trench 210, and in-situ doped polysilicon 600 is deposited on the upper surface of the P + implant layer 400 and in the gate trench 210;
(10) referring to fig. 10, the in-situ doped polysilicon 600 on the upper surface of the P + implant layer 400 and in the gate trench etch window 311 is etched away, such that the top surface of the remaining in-situ doped polysilicon 600 is flush with the upper surface of the N + source layer 500;
(11) referring to fig. 11, a silicon dioxide layer 700 is deposited on the top surface of the remaining in-situ doped polysilicon 600, the silicon dioxide layer 700 being located within the gate trench etch window 311;
(12) referring to fig. 12, Si on the P + implant layer 400 is removed3N4 Dielectric layer 910 and the Si in each shallow trench 3103N4The layers 930;
(13) referring to fig. 13, a layer of metallic aluminum 800 is deposited over the P + implant layer 400, the metallic aluminum 800 filling each shallow trench 310 and connecting the N + source layer 500 to the P + implant layer 400.
The foregoing shows and describes the general principles and broad features of the present invention and advantages thereof. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (1)
1. A trench type power MOSFET comprises an N + substrate, an N-epitaxial layer, a P-body injection layer and a P + injection layer which are arranged from bottom to top in sequence, it is characterized in that a plurality of shallow grooves which are distributed at intervals and penetrate through the P + injection layer are etched on the P-body injection layer, the bottom of each shallow groove is provided with an N + source electrode layer, etching a grid groove which sequentially penetrates through an N + source electrode layer and a P-body injection layer from top to bottom at the middle position of each shallow groove on the N-epitaxial layer, wherein a grid oxygen layer is arranged on the bottom surface and the peripheral side surface of each grid groove, in-situ doped polysilicon is filled in each grid groove, the top surface of the in-situ doped polysilicon filled in the grid groove is flush with the upper surface of the N + source electrode layer, and a silicon dioxide layer is attached to the top surface of the in-situ doped polysilicon; depositing a metal layer on the P + injection layer, wherein the metal layer fills each shallow groove and connects the N + source electrode layer with the P + injection layer; the metal layer is a metal aluminum layer;
the preparation method for preparing the groove type power MOSFET comprises the following steps:
(1) preparing an N + substrate, and extending an N-epitaxial layer outside the upper surface of the N + substrate;
(2) injecting P-body ions into the upper surface of the N-epitaxial layer to form a P-body injection layer, and injecting P + ions into the upper surface of the P-body injection layer to form a P + injection layer;
(3) depositing a layer of Si on the upper surface of the P + injection layer3N4A dielectric layer;
(4) in the presence of Si3N4A plurality of photoresists are adhered to the upper surface of the dielectric layer at intervals;
(5) etching the position of the P + injection layer between two adjacent photoresists to the P-body layer to form a plurality of shallow grooves, wherein the depth of each shallow groove is less than that of the Si3N4The sum of the thicknesses of the dielectric layer, the P + injection layer and the P-body injection layer;
(6) injecting N + ions into the bottom of each shallow groove, forming an N + source electrode layer at the bottom of the shallow groove, and adhering the N + source electrode layer on the Si3N4Removing the photoresist on the dielectric layer;
(7) depositing a layer of Si on the N + source layer in each shallow trench3N4Layer of and to said Si3N4Etching the central part of the layer to the upper surface of the N + source electrode layer to ensure that the etched Si layer3N4Forming a grid groove etching window;
(8) etching the N + source electrode layer in each shallow groove by using the grid groove etching window, and etching the N + source electrode layer into the N-epitaxial layer to form a plurality of grid grooves;
(9) oxidizing each grid groove to form a grid oxide layer on the bottom surface and the peripheral side surfaces of the grid groove, and depositing in-situ doped polycrystalline silicon on the upper surface of the P + injection layer and in each grid groove;
(10) etching the in-situ doped polysilicon on the upper surface of the P + injection layer and in the gate trench etching window to make the top surface of the remaining in-situ doped polysilicon flush with the upper surface of the N + source layer;
(11) depositing a silicon dioxide layer on the top surface of the remaining in-situ doped polysilicon;
(12) removing Si on the P + implantation layer3N4Dielectric layer and Si in each shallow trench3N4A layer;
(13) depositing a metal layer on the P + implant layer, the metal layer filling each shallow trench and connecting the N + source layer and the P + implant layer.
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|---|---|---|---|---|
| CN102569166A (en) * | 2012-03-09 | 2012-07-11 | 上海宏力半导体制造有限公司 | Shallow groove isolation manufacturing method capable of improving stress and semiconductor device manufacturing method |
| CN103295908A (en) * | 2012-02-28 | 2013-09-11 | 万国半导体股份有限公司 | Method for making gate-oxide with step-graded thickness in trenched DMOS device |
| CN104103523A (en) * | 2014-07-25 | 2014-10-15 | 苏州东微半导体有限公司 | Method for manufacturing power device with U-shaped grooves |
| CN105225957A (en) * | 2014-06-26 | 2016-01-06 | 北大方正集团有限公司 | Slot type power device manufacture method and slot type power device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7217976B2 (en) * | 2004-02-09 | 2007-05-15 | International Rectifier Corporation | Low temperature process and structures for polycide power MOSFET with ultra-shallow source |
| JP5588670B2 (en) * | 2008-12-25 | 2014-09-10 | ローム株式会社 | Semiconductor device |
| JP2015056486A (en) * | 2013-09-11 | 2015-03-23 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
| JP6214680B2 (en) * | 2014-01-10 | 2017-10-18 | 三菱電機株式会社 | Silicon carbide semiconductor device |
| JP6354525B2 (en) * | 2014-11-06 | 2018-07-11 | 株式会社デンソー | Method for manufacturing silicon carbide semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103295908A (en) * | 2012-02-28 | 2013-09-11 | 万国半导体股份有限公司 | Method for making gate-oxide with step-graded thickness in trenched DMOS device |
| CN102569166A (en) * | 2012-03-09 | 2012-07-11 | 上海宏力半导体制造有限公司 | Shallow groove isolation manufacturing method capable of improving stress and semiconductor device manufacturing method |
| CN105225957A (en) * | 2014-06-26 | 2016-01-06 | 北大方正集团有限公司 | Slot type power device manufacture method and slot type power device |
| CN104103523A (en) * | 2014-07-25 | 2014-10-15 | 苏州东微半导体有限公司 | Method for manufacturing power device with U-shaped grooves |
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