CN107645300B - Current multiplexing low-power consumption radio frequency receiver - Google Patents
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Abstract
The invention discloses a current multiplexing low-power consumption radio frequency receiver, which comprises: the transformer converts the single-ended radio frequency signal or the external differential signal received by the antenna into a differential signal through primary-secondary conversion and outputs the differential signal from the first differential voltage node and the second differential voltage node; the common-gate input stage is used for performing capacitive cross-coupling amplification on the output of the transformer and outputting differential amplification signals from the third differential voltage node and the fourth differential voltage node; the common-source amplifying circuit is used for carrying out transconductance amplification on the output of the transformer under the condition of not increasing current consumption and outputting differential amplification signals from a third differential voltage node and a fourth differential voltage node; the common-mode voltage stabilizing circuit stabilizes the common-mode voltage of the third differential voltage node and the fourth differential voltage node; the down-conversion switch circuit is used for performing down-conversion on the differential amplification signal under the control of the local oscillator signal to obtain an intermediate frequency signal and outputting a differential intermediate frequency current signal from a fifth differential voltage node and a sixth differential voltage node; and the trans-impedance amplifier is used for converting the differential intermediate-frequency current signal into a voltage signal and amplifying and outputting the voltage signal.
Description
Technical Field
The invention relates to a radio frequency receiver, in particular to a transformer-based current multiplexing low-power-consumption radio frequency receiver.
Background
With the continuous promotion of radio frequency technology, low-power-consumption radio frequency receivers are widely applied to more and more occasions, such as implantable medical equipment, wearable equipment, narrow-band internet of things and the like. The traditional receiver front-end design is generally formed by cascading separate radio frequency modules, and generally comprises: the design of the single-end to differential transformer (usually welded at the external board level of the chip), the low noise amplifier, the mixer and the like occupies more area and consumes more power.
In addition, to improve the sensitivity of the key indicators of the receiver, it is generally necessary to reduce the noise figure of the receiver. The main source of the noise coefficient of the receiver is transconductance thermal noise of a first-stage (usually, a low noise amplifier) input tube, and the contribution of the transconductance thermal noise is inversely proportional to the consumed current, so that the existing method for reducing the transconductance thermal noise of the input tube usually needs to consume more current, so that the design difficulty is realized by taking low noise and low power consumption into consideration.
Fig. 6 shows a conventional single-tube common-gate amplifying structure, which usually needs to add Zs at the source level of the MOS tube for biasing, where Zs may be an inductor, a resistor, or a current mirror structure, however, Zs is located at the input port, which has a large noise contribution and needs to reduce noise as much as possible.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a current multiplexing low-power consumption radio frequency receiver so as to obtain low noise coefficient and high sensitivity while reducing the current consumption of the receiver.
To achieve the above and other objects, the present invention provides a current-multiplexing low-power rf receiver, comprising:
the transformer is used for converting a single-ended radio frequency signal or an external differential signal received by the antenna into a differential signal through primary-secondary conversion of the transformer and outputting the differential signal from a first differential voltage node P1 and a second differential voltage node P2;
a common gate input stage for capacitively cross-coupled amplifying the differential signal output by the transformer and outputting a differential amplified signal from a third differential voltage node P3 and a fourth differential voltage node P4;
a common source amplifying circuit for performing additional transconductance amplification on the differential signal output from the transformer without increasing current consumption and outputting a differential amplified signal from a third differential voltage node P3 and a fourth differential voltage node P4;
a common mode voltage stabilizing circuit for stabilizing the common mode voltage of the third and fourth differential voltage nodes P3 and P4 by using a negative feedback principle;
the down-conversion switch circuit is used for down-converting the differential amplification signals output by the common gate input stage and the common source amplification circuit under the control of a local oscillator signal to obtain an intermediate frequency signal and outputting a differential intermediate frequency current signal from a fifth differential voltage node P5 and a sixth differential voltage node P6;
and the trans-impedance amplifier is used for converting the differential intermediate-frequency current signal output by the down-conversion switch circuit into a voltage signal and amplifying and outputting the voltage signal.
Furthermore, the current multiplexing low-power consumption radio frequency receiver further comprises a down-conversion switching tube bias generating circuit, which is used for generating a direct current bias voltage for a switching MOS tube of the down-conversion switching circuit and coupling a differential local oscillator signal from a phase-locked loop PLL to a gate of the switching MOS tube of the down-conversion switching circuit.
Furthermore, the common-gate input stage and the common-source amplifying circuit adopt a current multiplexing structure.
Further, the common-gate input stage includes a first NMOS transistor, a second NMOS transistor, a first coupling capacitor, a second coupling capacitor, a first bias resistor, and a second bias resistor, a non-inverting terminal of the secondary winding of the transformer is connected to one terminal of the first coupling capacitor and a source of the first NMOS transistor to form the first differential voltage node P1, a non-inverting terminal of the secondary winding of the transformer is connected to one terminal of the second coupling capacitor and a source of the second NMOS transistor to form the second differential voltage node P2, the other terminal of the first coupling capacitor is connected to a gate of the second NMOS transistor and one terminal of the second bias resistor, the other terminal of the second coupling capacitor is connected to the gate of the first NMOS transistor and one terminal of the first bias resistor, the other terminal of the first bias resistor and the other terminal of the second bias resistor are connected to a first bias voltage, the first NMOS transistor is connected to the third differential voltage node P3, the drain electrode of the second NMOS tube is connected with the fourth differential voltage node P4.
Further, the common-source amplifying circuit comprises a third PMOS tube, a fourth PMOS tube, a third coupling capacitor, a fourth coupling capacitor, a third bias resistor and a fourth bias resistor, one end of the third coupling capacitor is connected to the first differential voltage node P1, one end of the fourth coupling capacitor is connected to the second differential voltage node P2, the other end of the third coupling capacitor is connected with the grid electrode of the fourth PMOS tube and one end of the fourth bias resistor, one end of the fourth coupling capacitor is connected with the grid electrode of the third PMOS tube and one end of the third bias resistor, the other end of the third bias resistor and the other end of the fourth bias resistor are connected to a second bias voltage, the drain of the third PMOS tube is connected with a third differential voltage node P3, the drain of the fourth PMOS tube is connected with the fourth differential voltage node P4, and the source electrodes of the third PMOS tube and the fourth PMOS tube are connected with the common-mode voltage stabilizing circuit.
Further, the common mode voltage stabilizing circuit comprises a fifth PMOS transistor, a fifth resistor, a sixth resistor and a first operational amplifier, a source electrode of the third PMOS transistor and a source electrode of the fourth PMOS transistor are connected to a drain electrode of the fifth PMOS transistor, a reference common mode voltage is connected to an inverting input end of the first operational amplifier, an output end of the first operational amplifier is connected to a gate electrode of the fifth PMOS transistor, a source electrode of the fifth PMOS transistor is connected to a power supply voltage, one end of the fifth resistor is connected to the third differential voltage node P3, the other end of the fifth resistor and one end of the sixth resistor are connected to a non-inverting input end of the first operational amplifier, and the other end of the sixth resistor is connected to the fourth differential voltage node P4.
Further, the down-conversion switch circuit includes a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor, where a source of the sixth NMOS transistor and a source of the seventh NMOS transistor are connected to the fourth differential voltage node P4, a source of the eighth NMOS transistor and a source of the ninth NMOS transistor are connected to the third differential voltage node P3, drains of the sixth NMOS transistor and the eighth NMOS transistor are connected to the transimpedance amplifier to form the sixth differential voltage node P6, drains of the seventh NMOS transistor and the ninth NMOS transistor are connected to the transimpedance amplifier to form a fifth differential voltage node P5, a gate of the seventh NMOS transistor and a gate of the eighth NMOS transistor are connected to an inverted local oscillator signal, and a gate of the sixth NMOS transistor and a gate of the ninth NMOS transistor are connected to an in-phase local oscillator signal.
Further, the transimpedance amplifier comprises an intermediate frequency amplifier, a seventh resistor and an eighth resistor, the drain electrodes of the seventh NMOS transistor and the ninth NMOS transistor are connected with the non-inverting input terminal of the intermediate frequency amplifier and one end of the seventh resistor to form the fifth differential voltage node P5, the drain of the sixth NMOS transistor and the drain of the eighth NMOS transistor are connected to the inverting input terminal of the if amplifier and one end of the eighth resistor to form the sixth differential voltage node P6, the inverting output end of the intermediate frequency amplifier is connected with the other end of the seventh resistor, the non-inverting output end of the intermediate frequency amplifier is connected with the other end of the eighth resistor, the reference common mode voltage is connected to the common mode voltage input terminal of the IF amplifier, and the third differential voltage node P3, the fourth differential voltage node P4, the fifth differential voltage node P5, the sixth differential voltage node P6 and the IF amplifier output terminal IF all have the same reference common mode voltage.
Further, the down-conversion switch circuit comprises 8 switch MOS tubes, and the trans-group amplifier comprises two groups of trans-impedance amplifiers to form a quadrature mixer with the 8 switch MOS tubes and provide 4 paths of in-phase-quadrature differential outputs.
Further, the down-conversion switching tube bias generating circuit comprises an eleventh NMOS tube, a twelfth NMOS tube, a second operational amplifier, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, an eleventh coupling capacitor and a twelfth coupling capacitor, the reference common-mode voltage is connected to an inverting input terminal of the second operational amplifier, an output terminal of the second operational amplifier is connected to a gate of the eleventh NMOS tube, a source of the eleventh NMOS tube is grounded, a drain of the eleventh NMOS tube is connected to one end of the eleventh resistor, the other end of the eleventh resistor is connected to a non-inverting input terminal of the second operational amplifier and a source of the twelfth NMOS tube, a gate and a drain of the twelfth NMOS tube are connected to one end of the twelfth resistor, one end of the thirteenth resistor and one end of the fourteenth resistor to form a third bias voltage, and the other end of the twelfth resistor is connected to the power supply voltage, the other end of the thirteenth resistor, one end of the eleventh coupling capacitor, the grid of the sixth NMOS tube and the grid of the ninth NMOS tube are connected to form an in-phase local oscillation signal, the other end of the fourteenth resistor, one end of the twelfth coupling capacitor, the grid of the seventh NMOS tube and the grid of the eighth NMOS tube are connected to form an anti-phase local oscillation signal, and the other end of the eleventh coupling capacitor and the other end of the twelfth coupling capacitor are connected to a differential local oscillation signal output end of the phase-locked loop.
Compared with the prior art, the current multiplexing low-power consumption radio frequency receiver provided by the invention has the advantages that the current consumption of the receiver is reduced, the low noise coefficient and high sensitivity are obtained, and the area of a chip is saved.
Drawings
FIG. 1 is a circuit diagram of a current multiplexing low power consumption RF receiver according to the present invention;
FIG. 2 is a circuit diagram of a down-conversion switch tube bias generating circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a transformer 101 according to an embodiment of the present invention;
FIG. 4 shows an integrated turn ratio on a silicon substrate of 2: 6, a schematic structural diagram of the transformer;
FIG. 5 is a circuit diagram of another embodiment of a current multiplexing low power RF receiver of the present invention;
fig. 6 is a conventional single-tube common-gate amplifying structure.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Fig. 1 is a circuit structure diagram of a current multiplexing low power consumption rf receiver according to the present invention. As shown in fig. 1, the present invention provides a current multiplexing low power consumption rf receiver, which includes: the circuit comprises a transformer 101, a common-gate input stage 102, a common-source amplifying circuit 103, a common-mode voltage stabilizing circuit 104, a down-conversion switch circuit 105, a trans-impedance amplifier 106 and a down-conversion switch tube bias generating circuit 401.
The transformer 101 is a transformer integrated on a silicon substrate or an off-chip discrete transformer, and is configured to convert a single-ended radio frequency signal or an external differential signal received by an antenna into a differential signal through primary-secondary conversion thereof, and output the differential signal from a first differential voltage node P1 and a second differential voltage node P2; the common-gate input stage 102 comprises a first NMOS transistor M1, a second NMOS transistor M2, a first coupling capacitor C1, a second coupling capacitor C2, a first bias resistor R1 and a second bias resistor R2, and is configured to perform capacitive cross-coupling amplification on the differential signal output by the transformer 101 and output a differential amplified signal from a third differential voltage node P3 and a fourth differential voltage node P4; the common-source amplifying circuit 103 comprises a third PMOS transistor M3, a fourth PMOS transistor M4, a third coupling capacitor C3, a fourth coupling capacitor C4, a third bias resistor R3 and a fourth bias resistor R4, and is configured to perform additional transconductance amplification on the differential signal output by the transformer 101 without increasing current consumption and output a differential amplified signal from a third differential voltage node P3 and a fourth differential voltage node P4; the common-mode voltage stabilizing circuit 104 comprises a fifth PMOS transistor M5, a fifth resistor R5, a sixth resistor R6 and a first operational amplifier AMP1, and is used for stabilizing the common-mode voltage of the third differential voltage node P3 and the fourth differential voltage node P4 by using a negative feedback principle; the down-conversion switch circuit 105 comprises a sixth NMOS transistor M6, a seventh NMOS transistor M7, an eighth NMOS transistor M8, and a ninth NMOS transistor M9, and is configured to down-convert (mix) the differential amplified signals output by the common-gate input stage 102 and the common-source amplifying circuit 103 under the control of a local oscillator signal (LO +/LO-) to obtain an intermediate-frequency signal, and output the differential intermediate-frequency current signal from a fifth differential voltage node P5 and a sixth differential voltage node P6; the transimpedance amplifier 106 includes an intermediate frequency amplifier IFAMP1, a seventh resistor R7, and an eighth resistor R8, and is configured to convert the differential intermediate frequency current signal output from the down-conversion switching circuit 105 into a voltage signal and amplify the output intermediate frequency signal IF; the down-conversion switch tube bias generating circuit 401, as shown in fig. 2, includes an eleventh NMOS tube M41, a twelfth NMOS tube M42, a second operational amplifier AMP2, an eleventh resistor R41, a twelfth resistor R42, a thirteenth resistor R43, a fourteenth resistor R44, an eleventh coupling capacitor C41, and a twelfth coupling capacitor C42, and is configured to generate a dc bias voltage for the switch MOS of the down-conversion switch circuit 105 and couple the differential local oscillation signal from the phase-locked loop PLL to the gate of the switch MOS of the down-conversion switch circuit 105.
Specifically, the antenna is connected to one end of the primary coil of the transformer 101, the other end of the primary coil of the transformer 101 is grounded, the in-phase end of the secondary coil of the transformer 101 is connected to one end of the first coupling capacitor C1, the source of the first NMOS transistor M1, and one end of the third coupling capacitor C3 to form a first differential voltage node P1, the inverting end of the secondary coil of the transformer 101 is connected to one end of the second coupling capacitor C2, the source of the second NMOS transistor M2 and one end of the fourth coupling capacitor C4 are connected to form a second differential voltage node P2, the center tap of the secondary winding of the transformer 101 is grounded, the other end of the first coupling capacitor C1 is connected to the gate of the second NMOS transistor M2 and one end of the second bias resistor R2, the other end of the second coupling capacitor C2 is connected to the gate of the first NMOS transistor M1 and one end of the first bias resistor R1, and the other end of the first bias resistor R1 and the other end of the second bias resistor R2 are connected to the first bias voltage Vbn.
A drain of the first NMOS transistor M1 is connected to a drain of the third PMOS transistor M3, a terminal of the fifth resistor R5, a source of the eighth NMOS transistor M8, and a source of the ninth NMOS transistor M9 to form a third differential voltage node P3, a drain of the second NMOS transistor M2 is connected to a drain of the fourth PMOS transistor M4, a terminal of the sixth resistor R6, a source of the sixth NMOS transistor M6, and a source of the seventh NMOS transistor M7 to form a fourth differential voltage node P4, another terminals of the fifth resistor R5 and the sixth resistor R6 are connected to a non-inverting input terminal of the first operational amplifier AMP1, one terminal of a third coupling capacitor C3 is connected to a gate of the fourth PMOS transistor M4 and a terminal of the fourth bias resistor R4, one terminal of a fourth coupling capacitor C4 is connected to a gate of the third PMOS transistor M3 and a terminal of the third bias resistor R3, another terminal of the third bias resistor R3 and the other terminal of the fourth bias resistor R3 are connected to a drain of the fourth PMOS transistor M3, and the other terminal of the fourth bias transistor M3, the reference common-mode voltage Vcm is connected to the inverting input end of the first operational amplifier AMP1, the output end of the first operational amplifier AMP1 is connected to the grid electrode of the fifth PMOS transistor M5, and the source electrode of the fifth PMOS transistor M5 is connected with the power supply VDD;
a drain of the seventh NMOS transistor M7, a drain of the ninth NMOS transistor M9, a non-inverting input terminal of the if amplifier IFAMP1 and one end of the seventh resistor R7 are connected to form a fifth differential voltage node P5, a drain of the eighth resistor R8, a drain of the sixth NMOS transistor M6, a drain of the eighth NMOS transistor M8 is connected to an inverting input terminal of the if amplifier IFAMP1 to form a sixth differential voltage node P6, an inverting output terminal of the if amplifier IFAMP1 is connected to the other end of the seventh resistor R7, a non-inverting output terminal of the if amplifier IFAMP1 is connected to the other end of the eighth resistor R8, and a reference common mode voltage Vcm is connected to a common mode voltage input terminal of the if amplifier IFAMP 1;
a reference common mode voltage Vcm is connected to an inverting input terminal of the second operational amplifier AMP2, an output terminal of the second operational amplifier AMP2 is connected to a gate of an eleventh NMOS transistor M41, a source of the eleventh NMOS transistor M41 is grounded, a drain of the eleventh NMOS transistor M41 is connected to one end of an eleventh resistor R41, another end of the eleventh resistor R41 is connected to a non-inverting input terminal of the second operational amplifier AMP2 and a source of the twelfth NMOS transistor M42, a gate and a drain of the twelfth NMOS transistor M42 are connected to one end of the twelfth resistor R42, one end of a thirteenth resistor R43 and one end of a fourteenth resistor R44 to form a third bias voltage Vlo, another end of the twelfth resistor R42 is connected to the power supply VDD, another end of the thirteenth resistor R43 is connected to one end of the eleventh coupling capacitor C41 and a gate of the sixth NMOS transistor M6, a gate of the ninth NMOS transistor M9 to form a local oscillator signal LO +, and another end of the fourteenth local oscillator LO 44 is connected to one end of the twelfth coupling capacitor C42 and a gate of the seventh NMOS transistor M7, The grid electrode of the eighth NMOS tube M8 is connected to form an inverted local oscillator signal LO-, and the other end of the eleventh coupling capacitor C41 and the other end of the twelfth coupling capacitor C42 are connected to a differential local oscillator signal output end of the phase-locked loop PLL.
The principle of the invention will be further explained below with reference to fig. 1:
the radio frequency signal is connected to the RF input interface via an antenna or by wire. The RF input interface is connected to the primary coil of the transformer 101, and the port P1/P2 of the secondary coil of the transformer 101 is DC-connected to the common-gate input stage 102. The common-gate input stage 102 partially adopts a capacitive cross-coupling structure and has common-gate and common-source amplification characteristics. The P1/P2 are connected to the common source amplifying circuit 103 at the same time. The common-source amplifying circuit 103 and the common-gate input stage 102 are in a current multiplexing structure, i.e., do not consume additional dc current. The transconductance stage output P3/P4 is connected to a switch MOS transistor of the down-conversion switch circuit 105, the grid of the switch MOS transistor is connected with a local oscillator signal (LO +/LO-) to realize a frequency mixing function, and the output end of the switch MOS transistor is connected to the transimpedance amplifier 106 and converted into an intermediate frequency output voltage IF to realize a frequency mixing function of the receiver.
The rf antenna or the wired cable is directly connected to the primary coil of the transformer 101 without an additional ac coupling capacitor. The other end of the primary coil is connected to the ground terminal GND. Generally, the RF input terminal can achieve good impedance matching, and no additional matching circuit is needed, but an on-board impedance matching circuit can be formed by connecting RLC elements in series according to application requirements. The two ends of the primary coil of the transformer can also be connected with differential input signals, and the invention is not limited to this.
In a specific embodiment of the present invention, the transformer 101 is a 5-port device, as shown in FIG. 3. Ports 1 and 2 are connected with the primary coil inductor, ports 3 and 4 are connected with the secondary coil inductor, and port 5 is the center tap end of the secondary coil and is connected to the ground end GND to provide an electric path from direct current to ground for the circuit. In addition, ports 3 and 4 are the in-phase and anti-phase terminals of the transformer, respectively, with the same mutual inductance M and opposite phase (180 ° out of phase) with respect to port 1. There is also mutual inductance, a mutual inductance factor M', between port 3 and port 4. The primary and secondary windings of the transformer may have various turns ratios (or turn ratios) 1: n, the speed of primary and secondary impedance transformation of the transformer is proportional to the square of the turns ratio, i.e. Z3，4And Z1，2Referring to the impedance between ports 3, 4 and ports 1, 2, respectively. The larger the turn ratio is, the larger the impedance conversion speed of the primary coil and the secondary coil of the transformer is.
Since the RF port RF is usually 50 Ω standard impedance, the primary coil end of the transformer needs to be satisfied for input impedance matching
Z1，2＝50Ω
The secondary coil of the transformer also needs to satisfy the impedance matching condition:
wherein g ism1，2Is the transconductance of the first NMOS transistor M1/the second NMOS transistor M2. It can be seen that the larger the turns ratio of the transformer, the higher the impedance transformation ratio, g needed for realizing impedance matchingm1，2The smaller will be. Due to the transistor gmAnd the current consumed, and thus power consumption is reduced.
Fig. 4 shows an integrated turns ratio of 2: 6, it can also be modified into various other turns ratio and other winding mode.
The transformer 101 may also be implemented as a non-integrated off-chip discrete component connection. In the form of discrete components, the first and second differential voltage nodes P1 and P2 are input differential pair pins of the chip, and provide both DC to ground paths and differential signal input functions. When in discrete component form, the discrete transformer may take a variety of forms of manufacture, such as an inductor, a transmission line, and the like. A common point of transformers using integrated transformers on silicon substrates and discrete components is that both require the secondary winding to have a center tapped port 5 to provide access to ground.
In fig. 1, 102 is a capacitively cross-coupled common-gate input stage. The cross coupling capacitor first coupling capacitor C1/second coupling capacitor C2 provide an additional signal path to the gates of the transconductance tube first NMOS tube M1/second NMOS tube M2, which can improve the current utilization rate of the transconductance tube and provide 2 times of transconductance under the same current. The first bias resistor R1/the second bias resistor R2 are connected to the first bias voltage Vbn terminal to provide DC bias voltage for the transconductance transistor M1/M2.
The thermal noise contribution of the transconductance tube first NMOS tube M1/second NMOS tube M2 is reduced by half due to the fact that the effective transconductance is doubled.
Further, due to the mutual inductance of the transformer secondary winding ports 3 and 4, the noise contribution of the transconductance tube M1/M2 can realize an additional cancellation path, for a turns ratio of 1: 1, the noise coefficient contributed by the transconductance tube is about 0.2 gamma, while the noise contribution of the transconductance tube in the common-gate input structure is gamma, so that the noise coefficient is reduced under the condition of consuming the same current.
Because the tail current source or the tail inductor is not needed to carry out direct current bias on the common-gate input tube, the design process is simplified, and the chip area is saved. While eliminating the noise contribution of the tail current source or tail inductance.
Compared with the traditional common source input structure, the common gate input structure adopted by the invention can provide better linearity.
Furthermore, to achieve the gain adjustment function, the size of the cross-conduit may be varied, or an attenuation network may be connected in parallel across the first/second differential voltage nodes P1, P2. The gain adjustment should maintain port impedance matching.
The portion of the common source amplifier circuit 103 in fig. 1 provides additional transconductance without increasing current. The total transconductance is therefore:
Gm,total＝2×gm1,2+gm3,4
in fig. 1, the fifth resistor R5/the sixth resistor R6, the first operational amplifier AMP1, and the fifth PMOS transistor M5, i.e., the common mode voltage stabilizing circuit 104, together form a common mode feedback structure. The purpose of this is to stabilize the dc voltages at the third and fourth differential voltage nodes P3 and P4 as the reference common mode voltage Vcm. Because the same reference common-mode voltage Vcm is adopted in the transimpedance amplifier 106, the third differential voltage node P3/the fourth differential voltage node P4, the fifth differential voltage node P5/the sixth differential voltage node P6 and the intermediate frequency amplifier at the front and rear nodes of the down-conversion switch circuit 105 have a common dc potential Vcm, so that the dc blocking capacitors connected in series due to different dc potentials at the front and rear stages in the conventional method can be omitted, the chip area is saved, and the NMOS transistors M6 to M9 of the down-conversion switch circuit do not consume dc current any more, thereby reducing flicker noise (flicker noise).
It should be noted that the down-conversion switch circuit 105 can also be extended to 8 MOS transistors and two sets of transimpedance amplifiers to form a quadrature mixer, providing I-Q (in-phase-quadrature) 4-way differential output, as shown in fig. 5. By adding a group of additional switching tubes M10-M13 and a transimpedance amplifier controlled by the quadrature intrinsic signal LOQ, a quadrature output Q path with a phase difference of 90 degrees with the I path at the in-phase end is obtained, which is not described herein again.
The down-converter switch bias generation circuit 401 of the down-converter switch circuit 105 of fig. 2 is designed to generate a dc voltage Vlo that varies with the reference common mode voltage Vcm. The values are:
Vlo＝Vcm+VGs42
i.e., Vlo clamped at a fixed value Vgs4 (the threshold voltage of the twelfth NMOS transistor M42) above the reference common mode voltage Vcm. Thus, when the common-mode voltage changes, the gate-source voltage Vgs of the switching tube can be always kept constant. On one hand, DC coupling of the NMOS transistors M6-M9 in the switch tube NMOS transistor in the figure 1 is possible, and on the other hand, the working states of the NMOS transistors M6-M9 are guaranteed to be unchanged.
Therefore, the current multiplexing low-power consumption radio frequency receiver provided by the invention has the advantages that the current consumption of the receiver is reduced, the low noise coefficient and the high sensitivity are obtained, and the area of a chip is saved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (8)
1. A current multiplexed low power radio frequency receiver comprising:
the transformer is used for converting a single-ended radio frequency signal or an external differential signal received by the antenna into a differential signal through primary-secondary conversion of the transformer and outputting the differential signal from a first differential voltage node P1 and a second differential voltage node P2;
a common gate input stage for capacitively cross-coupled amplifying the differential signal output by the transformer and outputting a differential amplified signal from a third differential voltage node P3 and a fourth differential voltage node P4;
a common-source amplifying circuit, configured to perform additional transconductance amplification on a differential signal output by the transformer without increasing current consumption and output a differential amplified signal from a third differential voltage node P3 and a fourth differential voltage node P4, where the common-source amplifying circuit includes a third PMOS transistor, a fourth PMOS transistor, a third coupling capacitor, a fourth coupling capacitor, a third bias resistor, and a fourth bias resistor, one end of the third coupling capacitor is connected to the first differential voltage node P1, one end of the fourth coupling capacitor is connected to the second differential voltage node P2, the other end of the third coupling capacitor is connected to a gate of the fourth PMOS transistor and one end of the fourth bias resistor, one end of the fourth coupling capacitor is connected to a gate of the third PMOS transistor and one end of the third bias resistor, and the other ends of the third bias resistor and the fourth bias resistor are connected to a second bias voltage, the drain electrode of the third PMOS tube is connected with a third differential voltage node P3, the drain electrode of the fourth PMOS tube is connected with a fourth differential voltage node P4, and the source electrodes of the third PMOS tube and the fourth PMOS tube are connected with a common-mode voltage stabilizing circuit;
the common-mode voltage stabilizing circuit is used for stabilizing the common-mode voltage of the third differential voltage node P3 and the fourth differential voltage node P4 by using a negative feedback principle, and comprises a fifth PMOS (P-channel metal oxide semiconductor) transistor, a fifth resistor, a sixth resistor and a first operational amplifier, wherein the source electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected to the drain electrode of the fifth PMOS transistor, a reference common-mode voltage is connected to the inverting input end of the first operational amplifier, the output end of the first operational amplifier is connected to the grid electrode of the fifth PMOS transistor, the source electrode of the fifth PMOS transistor is connected with a power supply voltage, one end of the fifth resistor is connected with the third differential voltage node P3, the other end of the fifth resistor and one end of the sixth resistor are connected to the non-inverting input end of the first operational amplifier, and the other end of the sixth resistor is connected with the fourth differential voltage node P4;
the down-conversion switch circuit is used for down-converting the differential amplification signals output by the common gate input stage and the common source amplification circuit under the control of a local oscillator signal to obtain an intermediate frequency signal and outputting a differential intermediate frequency current signal from a fifth differential voltage node P5 and a sixth differential voltage node P6;
and the trans-impedance amplifier is used for converting the differential intermediate-frequency current signal output by the down-conversion switch circuit into a voltage signal and amplifying and outputting the voltage signal.
2. A current multiplexed low power rf receiver according to claim 1, wherein: the current multiplexing low-power-consumption radio frequency receiver also comprises a down-conversion switching tube bias generating circuit which is used for generating direct-current bias voltage for a switching MOS tube of the down-conversion switching circuit and coupling a differential local oscillator signal from a phase-locked loop PLL to a grid electrode of the switching MOS tube of the down-conversion switching circuit.
3. A current multiplexed low power rf receiver according to claim 2, wherein: the common-gate input stage and the common-source amplifying circuit adopt a current multiplexing structure.
4. A current multiplexed low power rf receiver according to claim 3, wherein: the common-gate input stage comprises a first NMOS transistor, a second NMOS transistor, a first coupling capacitor, a second coupling capacitor, a first bias resistor and a second bias resistor, wherein the in-phase end of the secondary coil of the transformer is connected with one end of the first coupling capacitor and the source electrode of the first NMOS transistor to form a first differential voltage node P1, the inverting end of the secondary coil of the transformer is connected with one end of the second coupling capacitor and the source electrode of the second NMOS transistor to form a second differential voltage node P2, the other end of the first coupling capacitor is connected with the gate of the second NMOS transistor and one end of the second bias resistor, the other end of the second coupling capacitor is connected with the gate of the first NMOS transistor and one end of the first bias resistor, the other end of the first bias resistor and the other end of the second bias resistor are connected with a first bias voltage, the first NMOS transistor is connected with a third differential voltage node P3, the drain electrode of the second NMOS tube is connected with the fourth differential voltage node P4.
5. A current multiplexed low power rf receiver according to claim 4, wherein: the down-conversion switch circuit comprises a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube and a ninth NMOS tube, wherein the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are connected with the fourth differential voltage node P4, the source electrode of the eighth NMOS tube and the source electrode of the ninth NMOS tube are connected with the third differential voltage node P3, the drain electrodes of the sixth NMOS tube and the eighth NMOS tube are connected with the transimpedance amplifier to form the sixth differential voltage node P6, the drain electrodes of the seventh NMOS tube and the ninth NMOS tube are connected with the transimpedance amplifier to form the fifth differential voltage node P5, the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube are connected with a local oscillation signal in opposite phase, and the grid electrode of the sixth NMOS tube and the grid electrode of the ninth NMOS tube are connected with an in-phase local oscillation signal in phase.
6. A current multiplexed low power rf receiver according to claim 5, wherein: the transimpedance amplifier comprises an intermediate frequency amplifier, a seventh resistor and an eighth resistor, the drain electrodes of the seventh NMOS tube and the ninth NMOS tube are connected with the non-inverting input end of the intermediate frequency amplifier and one end of the seventh resistor to form a fifth differential voltage node P5, the drain of the sixth NMOS transistor and the drain of the eighth NMOS transistor are connected to the inverting input terminal of the if amplifier and one end of the eighth resistor to form the sixth differential voltage node P6, the inverting output end of the intermediate frequency amplifier is connected with the other end of the seventh resistor, the non-inverting output end of the intermediate frequency amplifier is connected with the other end of the eighth resistor, the reference common mode voltage is connected to the common mode voltage input terminal of the IF amplifier, and the third differential voltage node P3, the fourth differential voltage node P4, the fifth differential voltage node P5, the sixth differential voltage node P6 and the IF amplifier output terminal IF all have the same reference common mode voltage.
7. A current multiplexed low power rf receiver according to claim 1, wherein: the down-conversion switching circuit comprises 8 switching MOS tubes, and the trans-impedance amplifier comprises two groups of trans-impedance amplifiers to form a quadrature mixer with the 8 switching MOS tubes and provide 4 paths of in-phase-quadrature differential outputs.
8. A current multiplexed low power rf receiver according to claim 2, wherein: the down-conversion switching tube bias generating circuit comprises an eleventh NMOS tube, a twelfth NMOS tube, a second operational amplifier, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, an eleventh coupling capacitor and a twelfth coupling capacitor, wherein the reference common-mode voltage is connected to the inverting input end of the second operational amplifier, the output end of the second operational amplifier is connected to the grid electrode of the eleventh NMOS tube, the source electrode of the eleventh NMOS tube is grounded, the drain electrode of the eleventh NMOS tube is connected to one end of the eleventh resistor, the other end of the eleventh resistor is connected to the non-inverting input end of the second operational amplifier and the source electrode of the twelfth NMOS tube, the grid electrode and the drain electrode of the twelfth NMOS tube are connected with one end of the twelfth resistor, one end of the thirteenth resistor and one end of the fourteenth resistor to form a third bias voltage, and the other end of the twelfth resistor is connected to the power supply voltage, the other end of the thirteenth resistor, one end of the eleventh coupling capacitor, the grid of the sixth NMOS tube and the grid of the ninth NMOS tube are connected to form an in-phase local oscillation signal, the other end of the fourteenth resistor, one end of the twelfth coupling capacitor, the grid of the seventh NMOS tube and the grid of the eighth NMOS tube are connected to form an anti-phase local oscillation signal, and the other end of the eleventh coupling capacitor and the other end of the twelfth coupling capacitor are connected to a differential local oscillation signal output end of the phase-locked loop.
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| CN113114131B (en) * | 2021-04-22 | 2022-06-17 | 浙江大学 | Current multiplexing radio frequency amplifier circuit |
| CN114268340A (en) * | 2022-01-26 | 2022-04-01 | 北京奕斯伟计算技术有限公司 | Transmitter, transceiver and signal transmission method thereof |
| WO2023155070A1 (en) * | 2022-02-16 | 2023-08-24 | 中国科学技术大学 | Isolated power chip based on deadband control symmetrical class d oscillator |
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