CN107634760B - Adaptive digital reset device for phase-locked loop - Google Patents

Abstract

The invention discloses a self-adaptive digital reset device for a phase-locked loop, which comprises: the system reset detection logic circuit is used for detecting whether system reset is kept effective and reaches an expected width through a plurality of registers, and if so, effective reset pulses are generated to the monostable circuit; the monostable circuit is used for outputting effective pulses to the power-on delay logic circuit after receiving the effective reset pulses and being in a stable state through a plurality of registers; the power-on delay logic circuit is used for counting after receiving the effective pulse output by the monostable circuit, keeping the effective pulse unchanged until reaching a preset threshold value, and outputting a trigger pulse to the PLL reset generation logic circuit; and the PLL reset generation logic circuit is used for generating a reset pulse with a required width after receiving the trigger pulse output by the power-on delay logic circuit. The invention realizes the reset of the phase-locked loop based on digital logic, and has the advantages of simple structure principle, capability of realizing self-adaptive reset, high reset efficiency and reliability and the like.

Description

Adaptive digital reset device for phase-locked loop

Technical Field

The invention relates to the technical field of Phase Locked Loops (PLLs), in particular to a self-adaptive digital reset device for a Phase Locked Loop.

Background

The phase-locked loop PLL is used to generate a stable high frequency clock output, which is the heart of a large scale integrated circuit, particularly a microprocessor. With the progress of the integrated circuit technology and the improvement of the target main frequency of the processor, the design of the PLL becomes more and more refined, and the stable, reliable and reasonable reset logic becomes an essential component of the phase-locked loop. The reset signal of the phase-locked loop usually needs to generate a positive pulse with a certain width after the system is powered on and stable, and at present, the pulse is usually realized by an analog circuit, is in a 0 state before the system is powered on and forms a 1 with a fixed width after the system is powered on and stable, and then returns to a zero state.

The phase-locked loop adopts the reset mode realized by the analog circuit, and has the following problems:

1) because analog circuits are usually process-related and have a much lower success rate of one-time design than digital circuits, once process migration is required, the circuits need to be completely redesigned, and the risk is high;

2) the analog circuit is usually a monostable circuit, namely, only one reset can be generated after power-on, and if the phase-locked loop is unlocked in the working process of the system, the logic can be triggered only in a mode of powering off the system and then powering on again. In order to solve the problem, some practitioners propose a mode of adopting a system reset signal of a processor as a reset signal of a PLL, but the locking delay of the PLL is displayed in front of a user program after the mode is reset and exited, so that a clock of the user program changes from slow to fast during work, the design of the user program, particularly a real-time program is complex, and meanwhile, the mode triggers the PLL reset every time the system is reset, so that unreasonable reset is generated; however, if the user program is controlled, the whole PLL reset process can be displayed, but the difficulty of user program development is still significantly increased.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the self-adaptive digital reset device for the phase-locked loop, which is based on digital logic to realize the reset of the phase-locked loop, has simple structure principle, can realize self-adaptive reset and has high reset efficiency and reliability.

In order to solve the technical problems, the technical scheme provided by the invention is as follows:

an adaptive digital reset apparatus for a phase locked loop, comprising:

the system reset detection logic circuit is used for detecting whether system reset is kept effective and reaches an expected width through a plurality of registers, and if so, effective reset pulses are generated to the monostable circuit;

the monostable circuit is used for outputting an effective pulse corresponding to a stable state to the power-on delay logic circuit after receiving the effective reset pulse and being in the stable state through a plurality of registers;

the power-on delay logic circuit is used for counting after receiving the effective pulse output by the monostable circuit, keeping the effective pulse unchanged until reaching a preset threshold value, and outputting a trigger pulse to the PLL reset generation logic circuit;

and the PLL reset generation logic circuit is used for generating a reset pulse with a required width after receiving the trigger pulse output by the power-on delay logic circuit.

As a further improvement of the present invention, the system reset detection logic circuit includes a register chain for detecting a system reset signal and a first determination logic unit for determining a system reset continuation state, the register chain is formed by sequentially connecting a plurality of first registers, an input end of the register chain is connected to the system reset signal as a chain head, an output end of each of the first registers in the register chain is respectively connected to an input end of the first determination logic unit, and an output end of the first determination logic unit outputs an effective reset pulse or an ineffective reset pulse.

As a further improvement of the present invention, the determination logic unit specifically determines a continuous state of the system reset signal from the output state of each of the first registers, and outputs a valid reset pulse if it is determined that the system reset signal is continuously valid for a specified number of beats in the register chain, otherwise outputs an invalid pulse.

As a further improvement of the present invention, the monostable circuit includes a register group and a second judgment logic unit for judging a stable state of the register group, the register group is formed by connecting a plurality of second registers, an output end of each of the second registers and an output end of the system reset detection logic circuit are connected to an input end of the corresponding second register after passing through a logic gate circuit, an output end of each of the second registers is respectively connected to an input end of the second judgment logic unit, and an output end of the second judgment logic unit outputs a valid pulse or an invalid pulse.

As a further improvement of the present invention, the register set keeps an output stable value after receiving the effective reset pulse output by the system reset detection logic circuit, and outputs the effective pulse through the second judgment logic unit.

As a further improvement of the present invention, the power-on delay logic circuit includes a third register, and a first 1-adding logic unit and a third judgment logic respectively connected to the third register, where the third register is accessed to the output pulse of the monostable circuit, if the third register is an effective pulse, the third register performs 1-adding counting through the first 1-adding logic unit, and the third judgment logic judges whether the counting reaches a preset threshold, if so, the current count value is kept unchanged, and a trigger pulse is output to the PLL reset pulse generation logic circuit.

As a further improvement of the present invention, the third register is in a reset state when receiving that the output pulse of the monostable circuit is an invalid pulse, and starts to count up by 1 when receiving that the output pulse of the monostable circuit changes from the invalid pulse to a valid pulse.

As a further improvement of the present invention, the PLL reset pulse generation logic circuit includes a fourth register, a second plus 1 logic unit, a fifth register, a fourth judgment logic, and a sixth register, which are connected in sequence, after the output of the system reset detection logic circuit and the PLL unlock signal undergo a first logic operation, the obtained signal undergoes a second logic operation with the output of the power-on delay logic circuit and is then accessed to the input end of the fourth register, when the output of the fourth register is valid, the fifth register counts through the second plus 1 logic unit, when the fourth judgment logic judges that the count reaches a preset threshold, the current count value is kept unchanged, and an effective signal is output through the sixth register to exit the reset state.

In a further improvement of the present invention, when the output of the fourth register is invalid, the fifth register is in a reset state, and when the output is changed from invalid to valid, the count of 1 is started.

Compared with the prior art, the invention has the advantages that:

1) the invention relates to a self-adaptive digital reset device for a phase-locked loop, which utilizes the randomness of the power-on values of different physical registers to realize the continuous state discrimination and the monostable state of system reset sequentially through a plurality of registers, triggers the steady counting logic to obtain the power-on initial state and control the power-on steady time, and finally generates the reset pulse meeting the PLL requirement.

2) The self-adaptive digital reset device for the phase-locked loop further comprises a reset register chain, wherein the reset register chain is used for judging whether the system reset is effective and reaches the expected width by using the state randomness of a plurality of triggers after the system reset detection logic circuit is powered on, so that the identification precision of the reset edge can be improved, the self-adaptive detection function of the power-on process can be realized, and burrs and unexpected jitters can be filtered in the thermal reset process.

3) The invention relates to a self-adaptive digital reset device for a phase-locked loop, which is characterized in that a monostable circuit further utilizes the randomness of the states of a plurality of triggers after power-on to judge the monostable state through a parallel multi-bit register group.

4) The self-adaptive digital reset device for the phase-locked loop further can ensure that the power-on process is completed by configuring the power-on delay logic circuit, the effective initial circuit of the system reset detection logic circuit and the monostable circuit is only in a workable state, but the power-on is not completely completed, and the steady counting logic is triggered, so that the power-on initial state is obtained, the power-on stabilization time is controlled, and the power-on completion and the stability of the whole chip are ensured when the counting is stabilized.

5) The invention relates to a self-adaptive digital reset device for a phase-locked loop, further a PLL reset pulse generation logic circuit integrates two conditions of power-on reset detection and thermal reset PLL unlocking by integrating two conditions of power-on reset detection and thermal reset PLL unlocking, eliminates reset burrs by reusing a reset register chain, utilizes PLL unlocking monitoring logic, can realize anti-jitter self-adaptive PLL reset, and can adjust reset pulse width according to specific requirements of PLL in the realization process, thereby realizing reset signal burr filtration and anti-jitter functions.

Drawings

Fig. 1 is a schematic structural diagram of an adaptive digital reset apparatus for a phase-locked loop according to the present embodiment.

FIG. 2 is a timing diagram of registers during reset signal generation during power-on reset according to an embodiment of the present invention.

FIG. 3 is a timing diagram of registers during reset signal generation during a thermal reset according to an embodiment of the present invention.

Illustration of the drawings: 1. a system reset detection logic circuit; 11. a chain of registers; 111. a first register; 12. a first judgment logic unit; 2. a monostable circuit; 21. a register group; 211. a second register; 22. a second judgment logic unit; 3. a power-on delay logic circuit; 31. a third register; 32. a first plus 1 logic unit; 33. a third judgment logic; 4. a PLL reset generation logic circuit; 41. a fourth register; 42. a second plus 1 logic unit; 43. a fifth register; 44. a fourth judgment logic unit; 45. and a sixth register.

Detailed Description

The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.

As shown in fig. 1, the adaptive digital reset apparatus for a phase-locked loop in this embodiment includes:

the system reset detection logic circuit 1 is used for detecting whether system reset is kept effective and reaches a desired width through a plurality of registers, and if the system reset is kept effective, effective reset pulses are generated to the monostable circuit 2;

the monostable circuit 2 is used for receiving the effective reset pulse, is in a stable state through a plurality of registers, and outputs the effective pulse corresponding to the stable state to the power-on delay logic circuit 3;

the power-on delay logic circuit 3 is used for counting after receiving the effective pulse output by the monostable circuit 2, keeping the effective pulse unchanged until reaching a preset threshold value, and outputting a trigger pulse to the PLL reset generation logic circuit 4;

and the PLL reset generation logic circuit 4 is used for generating a reset pulse with a required width after receiving the trigger pulse output by the power-on delay logic circuit 3.

In the embodiment, the randomness of the power-on values of different physical registers is utilized, the judgment of the system reset continuous state and the monostable state are realized through a plurality of registers in sequence, the steady counting logic is triggered again, the power-on initial state is obtained, the power-on stabilization time is controlled, finally, the reset pulse meeting the PLL requirement is generated, the reliable reset of the PLL after the power-on stabilization can be realized based on complete digital logic, the randomness of the power-on states of a plurality of units is utilized, the misjudgment can be effectively reduced, and the reliable reset is realized.

Compared with the traditional method for realizing PLL reset through an analog circuit, the digital logic circuit generates the PLL reset signal, a monostable signal can be generated after power-on, a positive pulse with fixed width is further generated to trigger PLL reset, and the monostable signal can be used independently or can be used in combination with the analog circuit to improve the reliability of PLL reset after power-on; in this embodiment, by using the digital logic circuit, the PLL can be Reset for multiple times by using a system Reset signal (Reset) according to the working state of the PLL, that is, in the case that the PLL is out of lock, the system Reset triggers the PLL to Reset, and in the case that the PLL is not out of lock, the PLL Reset is not triggered, so that a user can obtain a stable high-frequency system clock after the Reset is completed and perform a fast Reset when the PLL is not out of lock by adjusting the width of a system Reset pulse.

In this embodiment, the system reset detection logic circuit 1 specifically includes a register chain 11 for detecting a system reset signal and a first determination logic unit 12 for determining a system reset continuation state, the register chain 11 is formed by sequentially connecting first registers 111, an input end of the register chain 11 is connected to the system reset signal as a chain head, an output end of each first register 111 in the register chain 11 is connected to an input end of the first determination logic unit 12, and an output end of the first determination logic unit 12 outputs an effective reset pulse or an invalid reset pulse. The first register 111 may specifically adopt a plurality of D registers without a reset terminal, and may also adopt other types of registers without a reset terminal, and the number of the first registers 111 in the register chain 11 may be configured according to specific requirements.

In the embodiment, the randomness of the states of a plurality of triggers after power-on is utilized, and the judgment on whether the system reset is effective and reaches the expected width is realized by adopting the reset register chain, and the identification precision of the reset edge can be improved by the mode of resetting the register chain because the probability of mistakenly identifying the reset state after the power-on is finished is small; at the beginning of power-on, a plurality of triggers can reach an expected value and also indicate that the whole power-on is at a relatively stable stage, so that the self-adaptive detection function of the power-on process can be realized by adopting a register chain structure, burrs and unexpected jitter can be filtered in the thermal reset process in a reset chain mode, the reset jitter and the burrs can be effectively eliminated, and the condition that the MRegs of the register group is changed from an unstable value to a stable value after being reset stably is ensured.

In this embodiment, the determination logic unit 12 specifically determines the continuous state of the system reset signal according to the output state of each first register 111, and outputs an effective reset pulse if it is determined that the system reset signal in the register chain 11 is continuously valid for a specified number of beats, or outputs an invalid pulse, that is, determines how many beats the system reset continues through the determination logic unit 12, such as N beats or N/2 beats, where N is the number of the first registers 111.

As shown in fig. 2, in this embodiment, a reset detection register chain RstChain with a length of N is first constructed by a first register 111 without a reset end, where the register chain RstChain uses a system clock input by a chip as a clock, uses a system reset signal of the chip as a chain head, and the value transmission of the chain may be an original value or an inverse of the original value, that is, some connects a Q end of the register to a D end of a next register, and some connects a-Q end to a D end of the next register; then, a judgment logic unit 12 is constructed through a combinational logic ncyclerrt, and the combinational logic ncyclerrt is input to the Q end or the NQ end of each first register 111 in the register chain RstChain, so that the following judgment on the register chain RstChain is realized: if the whole chain is '0', NCyceRst outputs 1, otherwise 0 is output; if the first half chain is '0' and the second half chain is '1', outputting a whole pulse with a clock period width, namely judging whether the system reset is continuously effective for N beats or N/2, wherein the states corresponding to '0' and '1' can be configured according to actual requirements, and the configuration is different according to different conditions of adopting original values or negating the connection register chain.

In this embodiment, the monostable circuit 2 includes a register group 21 and a second judgment logic unit 22 for judging a steady state, the register group 21 is formed by connecting a plurality of second registers 211, an output end of each second register 211 and an output end of the system reset detection logic circuit 1 are connected to an input end of the corresponding second register 211 after passing through a logic gate circuit, an input end of the second judgment logic unit 22 is connected to an output end of each second register 211, and an output end of the second judgment logic unit 22 outputs a valid pulse or an invalid pulse. The second register 211 specifically uses a D register without a reset terminal, and may also use other types of registers without a reset terminal.

In the embodiment, the monostable state is judged by the parallel multi-bit register group by utilizing the randomness of the states of the plurality of triggers after power-on, and because the probability of the monostable state is low, the triggering of the subsequent delay circuit counting process after resetting (basically completing power-on) can be ensured by the structure of the parallel multi-bit register group, and meanwhile, the self-adaptive detection function of the power-on process can be realized.

In this embodiment, the register group 21 keeps as an output stable value after receiving the effective reset pulse output by the system reset detection logic circuit 1, and outputs the effective pulse through the second judgment logic unit 22, that is, the second judgment logic unit 12 detects whether the reset edge is in a stable state.

As shown in fig. 2, in this embodiment, a monostable register group MRegs is specifically formed by M second registers 211 without a reset terminal, the register group takes a system clock input by a chip as a clock, and a D terminal of each second register 211 may adopt the following two logic types: taking the 'OR' of the Q end of the current register and the NCyceRst as the input of a D end; and of the Q end of the current register and the NCyclerst is used as D end input. When the register of the first input is adopted, the register is kept in a state of '1' after NCyceRst is 1; when the register of the second input is used, the state is maintained as "0" after ncyclerrst is 1. The register set MRegs is at a random value at the beginning of power-up, but is in a fixed state after ncycerst is 1, i.e., each register maintains a fixed value and is no longer affected by ncycerst.

A second judgment logic unit 22 is constructed through a combinational logic MRegFix, and the input of the MRegFix is the Q end of M registers in the register group MRegs; when all M registers are at a stable value, MRegFix outputs 1, otherwise 0 is output.

In this embodiment, the power-on delay logic circuit 3 specifically includes a third register 31, and a first 1-adding logic unit 32 and a third judgment logic 33 respectively connected to the third register 31, where the third register 31 is accessed to the output pulse of the monostable 2, if the third register is an effective pulse, the third register 31 performs 1-adding counting through the first 1-adding logic unit 32, and the third judgment logic 33 judges whether the counting reaches a preset threshold, if so, the current counting value is kept unchanged, and a trigger pulse is output to the PLL reset generation logic circuit.

In this embodiment, by configuring the power-on delay logic circuit 3, it can be ensured that the power-on process is completed, and the circuit is only in a workable state at the beginning (starting to count) when the system reset detection logic circuit 1 and the monostable circuit 2 are effective, but the power-on is not completely completed, that is, the counting process of the power-on delay logic circuit 3 works in a state where "power is available and can work but is not fully powered on", and the stable counting logic is triggered, so that the power-on initial state is obtained and the power-on stable time is controlled, that is, the power-on of the whole chip is completed and stabilized when the counting is ensured by proper counting. The count width in the power-on delay logic circuit 3 can be adjusted according to actual requirements.

In this embodiment, the third register 31 is in a reset state when receiving that the output pulse of the monostable 2 is an invalid pulse, and starts to count up by 1 when receiving that the output pulse of the monostable 2 changes from the invalid pulse to a valid pulse.

As shown in fig. 2, in this embodiment, the third register 31 is specifically composed of a set of StableCntRegs with a reset terminal, and when the MRegFix output is 0, the StableCntRegs is in a reset state; when the MRegFix output changes from 0 to 1, the StableCntRegs starts to count up by 1; after the StableCntRegs count to the expected value, StableValue, the value is kept unchanged.

In this embodiment, the PLL reset pulse generating logic circuit 4 includes a fourth register 41, a second 1-adding logic unit 42, a fifth register 43, a fourth judging logic 44, and a sixth register 45, which are connected in sequence, after the output of the system reset detecting logic circuit 1 and the PLL unlock signal are subjected to a first logic operation, the obtained signal is subjected to a second logic operation with the output of the power-on delay logic circuit 3 and then is accessed to the input end of the fourth register 41, when the output of the fourth register 41 is valid, the fifth register 43 counts through the second 1-adding logic unit 42, when the fourth judging logic 43 judges that the count reaches a preset threshold, the current count value is kept unchanged, and an output valid signal is output through the sixth register 45 to exit the reset state.

In the embodiment, the PLL reset pulse generation logic circuit 4 with the above structure is adopted, two conditions of power-on reset detection and thermal reset PLL lock loss are combined, reset burrs are eliminated by reusing a reset register chain, PLL lock loss monitoring logic is utilized, anti-jitter self-adaptive PLL reset can be realized, the reset pulse width can be adjusted according to specific requirements of PLL in the realization process, and thus the reset signal burr filtering and anti-jitter functions are realized.

In this embodiment, the first logic operation is a logical and operation, the second logic operation is a logical or parameter, when the output of the fourth register 41 is invalid, the fifth register 43 is in a reset state, and when the output is changed from invalid to valid, the count of 1 is started.

As shown in fig. 2, the PLL reset pulse generation logic circuit 4 of the present embodiment is specifically composed of a set of registers RstCntRegs with reset terminals, plus 1 logic, decision logic, and two registers without reset terminals (CntRst, PLLRst), where the register CntRst is used as a fourth register 41 for latching "or" of the power-on PLL reset from the system reset detection logic circuit output and the adaptive reset from the power-on delay logic circuit 3 output, and when CntRst is 1, RstCntRegs is in a reset state; the register RstCntregs is a fifth register 43, the register PLLRst is a sixth register 45, and after the CntRst is changed from 1 to 0, the RstCntregs starts to count by adding 1; after the RstCntregs counts to the expected value RstCycles, the value is kept unchanged, the register PLLRst latches the comparison result of the RstCntregs and the RstCycles, and the PLL exits the reset state when the two are equal.

By adopting the self-adaptive digital reset device with the structure, the specific value discrimination and the monostable state are realized through the register chain and the parallel multi-bit register group, the steady counting logic is triggered, the power-on initial state and the power-on stabilization time are obtained, the reset pulse meeting the PLL requirement is generated finally, the reliable reset of the PLL after the power-on stabilization can be realized, meanwhile, in the subsequent reset process of the system, the reset burr is eliminated through reusing the reset register chain, the self-adaptive PLL reset with anti-jitter can be realized by utilizing the PLL unlocking monitoring logic, and the reset L of the secondary system can be ensured to be certainly reset through the thermal reset design.

In the specific embodiment of the present invention, the timing sequence of each register in the power-on reset process using the adaptive digital reset apparatus is shown in fig. 3, and includes the following 6 stages:

stage 1: power-up begins until the reset signal is pulled low.

At this stage, as the IO interface and the core system of the chip are powered on, the reset and the clock of the system enter the chip, and each device/circuit starts to charge and discharge to perform logic operation (at the initial stage of power on, the signal swing may be low, and even the lower level logic may not be triggered to complete normal flip). The end of the present phase can be divided into two cases by the different hopping modes of the system reset signal: firstly, if the system reset signal is kept to be 0 all the time from the beginning of power-on, the clock of each trigger in the logic can be stably turned over, namely the stage is finished; if the reset signal is initially pulled up to high and then forms a negative pulse, the reset is changed from high to low for the first time, namely the phase is ended.

The logic states of the registers at this stage are as follows:

resetting the detection register chain RstChain: for the above-mentioned situation (i), every register is in the initial random value, for the above-mentioned situation (ii), will change into all "1" from the random value while powering on with the clock, but no matter situation (i) or (ii), RstChain powers on and is all "0", thus make NCyceRst be the probability of 1 very small;

the MRegs with the very small probability of NCyceRst being 1 can keep the initial power-on value, so that the probability of MRegfix being 1 is very small, and only when the initial power-on value is a monostable fixed value or NCyceRst being 1 triggers the MRegs to be converted into the monostable fixed value;

the stableCntRegs is controlled by the MRegFix to keep a preset fixed initial value, so that a reset register CntRSt of the phase-locked loop reset counting device is set to be 1, the reset counting register is an initial value, and the PLL is in a reset state.

Stage 2: the first N cycles that the reset signal is low.

The reset detection register chain RstChain changes from all '1' or the random value (for the situation of (r)) to all '0' when being powered on with the clock beat by beat, and NCyceRst changes to the determined 0 value;

the other register sets and control signals will hold or assume phase 1 (if there is no phase 1) state.

Stage 3: and (5) electrifying to stabilize.

Resetting the detection register chain RstChain to be all '0', and NCyceRst jumping to be 1;

the monostable register group MRegs is set to a preset fixed position, and MRegFix jumps to 1;

StableCntRegs start counting until StableValue is fixed;

CntRst is determined to be 1, the reset counter RstCntRegs is set to an initial value, and the output PLLRst is determined to be high.

The power-up voltage rise can be tolerated until the end of this phase, and the output of the various signals does not necessarily reach full amplitude, i.e., the lowest or highest voltage expected by the design is reached when one logic signal is 0 or 1.

And 4, stage: the phase locked loop active reset time.

The system reset signal, ncyclerrst, MRegFix remain unchanged;

StableCntRegs are stabilized at a fixed value of StableValue;

CntRst jumps to 0, the reset counter (RstCntRegs) starts counting, and the output PLLRst is determined to be high.

The PLLRst is set to have completed power-on at this stage, and effectively resets the PLL.

Stage 5: a phase-locked loop locking phase.

The system reset signal, ncyclerrst, MRegFix, CntRst remain unchanged;

the reset counter (RstCntRegs) reaches RstCycles, PLLRst jumps to 0;

the PLL output frequency gradually changes to the desired frequency.

Stage 6: and resetting and exiting to normally work.

The phase-locked loop is successfully locked, and the PLL _ Lock signal jumps to 1;

the system reset signal jumps to 1, and the system starts to work normally;

ncycerrest becomes 0 but has no effect on MReg, MRegFix, CntRst, PLLRst remain unchanged.

In the specific embodiment of the present invention, the timing sequence of each register in the thermal reset working process after the phase-locked loop is unlocked by using the adaptive digital reset device is shown in fig. 3, and the power-on reset process can be divided into 4 stages:

stage 1: hot reset detection and phase locked loop reset triggering.

The system reset signal becomes low, the reset detection register chain RstChain gradually changes from full '1' to full '0' along with the beat-by-beat of the clock, and after [ N/2] beats, the system is judged to be effective reset and outputs a single-beat high pulse;

checking whether the PLL is out-of-lock or not during the single-beat high pulse, if so, setting CntRSt to be 1, and setting a reset counter to be an initial value;

if the detection finds that the PLL is not unlocked, the phase-locked loop reset related logic is not activated, and then the system works normally only after the system reset jump is changed into 1.

Stage 2: the phase locked loop active reset time.

The reset counter (RstCntRegs) counts and the output PLLRst is determined to be high.

The voltage is set to be stable in this stage, and PLLRst effectively resets the PLL.

Stage 3: a phase-locked loop locking phase.

The reset counter (RstCntRegs) reaches RstCycles, PLLRst jumps to 0;

the PLL output frequency gradually changes to the desired frequency.

And 4, stage: and resetting and exiting to normally work.

The phase-locked loop is successfully locked, and the PLL _ Lock signal jumps to 1;

the system reset signal jumps to 1 and the system starts to work normally.

That is, by using the adaptive digital reset apparatus of this embodiment, the PLL may not be always in the reset mode, and during the power-on reset, the monostable circuit 2 is determined to be in the stable state (MRegFix jumps to 1) after the system is reset to the low N CLKIN periods, so as to release the reset of stablecrtregs, which releases the control of RstCntRegs after reaching StableValue, and RstCntRegs only generates the reset pulse with a fixed width; in the process of system thermal reset, the system can be triggered only under the condition that PLL is unlocked, and the generated pulse width is fixed to Rstcycles;

in addition, with the adaptive digital reset device of the present embodiment, an effective PLL reset can be obtained, and an invalid reset can be caused when the PLL reset is started before power-on is stable and the reset pulse width is insufficient, whereas with the adaptive digital reset device of the present embodiment, the PLL reset pulse may occur only when the initial value of power-on MRegs is a stable value (MRegFix ═ 1) and the initial value of stablecrntregs is StableValue, the probability of premature reset pulse generation and insufficient width is only 1/(2M StableValue) according to the 0/1 average distribution, and the probability can be further reduced by adjusting the specific data of the flip-flop and StableValue.

The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.

Claims (9)

1. An adaptive digital reset apparatus for a phase locked loop, comprising:

the system reset detection logic circuit (1) is used for detecting whether the system reset is kept effective and reaches a desired width through a plurality of registers, and if so, an effective reset pulse is generated to the one-shot circuit (2);

the monostable circuit (2) is used for receiving the effective reset pulse, then being in a stable state through a plurality of registers and outputting the effective pulse corresponding to the stable state to the power-on delay logic circuit (3);

the power-on delay logic circuit (3) is used for counting after receiving the effective pulse output by the monostable circuit (2), keeping the effective pulse unchanged until reaching a preset threshold value, and outputting a trigger pulse to the PLL reset generation logic circuit (4);

and the PLL reset generation logic circuit (4) is used for generating a reset pulse with a required width after receiving the trigger pulse output by the power-on delay logic circuit (3).

2. The adaptive digital reset device for the phase-locked loop according to claim 1, wherein the system reset detection logic circuit (1) comprises a register chain (11) for detecting a system reset signal and a first determination logic unit (12) for determining a system reset persistent state, the register chain (11) is formed by sequentially connecting a plurality of first registers (111), an input end of the register chain (11) is connected with the system reset signal as a chain head, an output end of each first register (111) in the register chain (11) is respectively connected to an input end of the first determination logic unit (12), and an output end of the first determination logic unit (12) outputs an active reset pulse or an inactive reset pulse.

3. An adaptive digital reset device for a phase locked loop according to claim 2, wherein: the judging logic unit (12) specifically judges the continuous state of the system reset signal according to the output state of each first register (111), and outputs an effective reset pulse if the system reset signal in the register chain (11) is judged to be continuously effective for a specified number of beats, otherwise, outputs an ineffective pulse.

4. An adaptive digital reset device for a phase locked loop according to claim 1, 2 or 3, wherein: the monostable circuit (2) comprises a register group (21) and a second judgment logic unit (22) used for judging the stable state of the register group (21), the register group (21) is formed by connecting a plurality of second registers (211), the output end of each second register (211) and the output end of the system reset detection logic circuit (1) are connected to the input end of the corresponding second register (211) after passing through a logic gate circuit, the output end of each second register (211) is respectively connected to the input end of the second judgment logic unit (22), and the output end of the second judgment logic unit (22) outputs a valid pulse or an invalid pulse.

5. An adaptive digital reset device for a phase locked loop according to claim 4, wherein: the register group (21) keeps as an output stable value after receiving the effective reset pulse output by the system reset detection logic circuit (1), and the effective pulse is output through the second judgment logic unit (22).

6. An adaptive digital reset device for a phase locked loop according to claim 1, 2 or 3, wherein: the power-on delay logic circuit (3) comprises a third register (31), and a first 1 adding logic unit (32) and a third judging logic (33) which are respectively connected with the third register (31), wherein the third register (31) is accessed to the output pulse of the monostable circuit (2), if the output pulse is an effective pulse, the third register (31) performs 1 adding counting through the first 1 adding logic unit (32), the third judging logic (33) judges whether the counting reaches a preset threshold value, if the counting reaches the preset threshold value, the current counting value is kept unchanged, and a trigger pulse is output to the PLL reset generation logic circuit (4).

7. An adaptive digital reset device for a phase locked loop according to claim 6, wherein: and the third register (31) is in a reset state when receiving that the output pulse of the monostable circuit (2) is an invalid pulse, and starts to count by 1 when receiving that the output pulse of the monostable circuit (2) is changed from the invalid pulse to a valid pulse.

8. An adaptive digital reset device for a phase locked loop according to claim 1, 2 or 3, wherein: the PLL reset generation logic circuit (4) comprises a fourth register (41), a second 1 adding logic unit (42), a fifth register (43), a fourth judgment logic unit (44) and a sixth register (45) which are connected in sequence, after the output of the system reset detection logic circuit (1) and a PLL loss-of-lock signal are subjected to first logic operation, the obtained signal and the output of the power-on delay logic circuit (3) are subjected to second logic operation and then are accessed to the input end of a fourth register (41), when the output of the fourth register (41) is valid, the fifth register (43) counts through the second 1 adding logic unit (42), when the fourth judging logic unit (44) judges that the count reaches a preset threshold value, the current count value is kept unchanged, and a valid signal is output through the sixth register (45) to exit a reset state.

9. An adaptive digital reset device for a phase locked loop according to claim 8, wherein: when the output of the fourth register (41) is invalid, the fifth register (43) is in a reset state, and when the output is changed from invalid to valid, 1-up counting is started.

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