CN107610631B

CN107610631B - Scanning driving unit, circuit and method and display panel

Info

Publication number: CN107610631B
Application number: CN201710819177.8A
Authority: CN
Inventors: 伍黄尧; 赖青俊
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2017-09-12
Filing date: 2017-09-12
Publication date: 2020-08-25
Anticipated expiration: 2037-09-12
Also published as: CN107610631A

Abstract

The application discloses a scanning driving unit, a circuit, a method and a display panel. Wherein the scan driving unit includes: the device comprises a scanning control module, a signal transmission module, a first control end, a second control end, a first input end, a second input end, a fourth input end, a reset signal control end and a scanning signal output end; during scanning, the signal transmission module provides a scanning driving signal for the scanning signal output end under the combined action of a first input signal or a second input signal received by the third input end, a fourth input signal received by the fourth input end, a first level signal received by the first level signal input end and a second level signal received by the second level signal input end; during the reset period, a reset signal is provided to the scan signal output terminal under the control of a reset control signal received at the reset signal control terminal. The embodiment can reduce the number of transistors forming the reset control signal, and is beneficial to realizing the design of a narrow frame.

Description

Scanning driving unit, circuit and method and display panel

Technical Field

The present disclosure relates generally to the field of display technologies, and in particular, to a scan driving unit, a scan driving circuit, a scan driving method, and a display panel.

Background

With the development of display technologies, people tend to favor display panels with narrow frames and high definition. In order to meet the market demand, display devices are gradually developing towards narrow-frame and high-definition.

In a conventional display device, a scanning signal line is generally provided in a display region of the display device, and a scanning drive circuit for supplying a scanning signal to the scanning signal line is generally provided in a frame region of the display device. In order to make the scan driving signal provided by the scan driving circuit received by each scan signal line more stable, the scan signal lines are usually scanned in both forward and reverse directions, i.e. first scanning from the first scan signal line to the last scan signal line, and then scanning from the last scan signal line to the first scan signal line.

Therefore, the reset module is required to be arranged in each scanning driving unit in the scanning driving circuit to realize two-end scanning, and the reset module usually comprises a plurality of transistors and a plurality of input ends, so that the layout area of the frame area of the display device is occupied, and the narrow-frame design is not facilitated.

Disclosure of Invention

In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a scan driving unit, a scan driving circuit, a scan driving method and a display panel, so as to solve the technical problems in the prior art.

In a first aspect, an embodiment of the present application provides a scan driving unit, including: the device comprises a scanning control module, a signal transmission module, a first level signal input end, a second level signal input end, a first control end, a second control end, a first input end, a second input end, a fourth input end, a reset signal control end and a scanning signal output end; wherein: the scanning control module comprises an output end, and under the action of a first control signal received by the first control end and a second control signal received by the second control end, the scanning control module provides a first input signal received by the first input end or a second input signal received by the second input end to the output end; the signal transmission module comprises a third input end, the third input end is electrically connected with the output end, and the third input end receives the first input signal or the second input signal provided by the output end; during scanning, the signal transmission module provides a scanning driving signal to the scanning signal output end under the combined action of a first input signal or a second input signal received by the third input end, a fourth input signal received by the fourth input end, a first level signal received by the first level signal input end and a second level signal received by the second level signal input end; during the reset period, a reset signal is provided to the scan signal output terminal under the control of a reset control signal received at the reset signal control terminal.

In a second aspect, an embodiment of the present application provides a scan driving circuit, where the scan driving circuit includes N stages of scan driving units as above, where N is a positive integer; wherein: the first control ends of the second-level to Nth-level scanning driving units are connected to the scanning signal output end of the previous-level scanning driving unit; the second control ends of the first-stage to the N-1-stage scanning driving units are connected to the scanning signal output end of the next-stage scanning driving unit; the scanning drive circuit also comprises a first start signal end, a second start signal end, a first clock signal end, a second clock signal end, a third clock signal end, a fourth clock signal end, a first signal input end, a second signal input end, a first level signal end, a second level signal end and a plurality of signal output ends, wherein the scanning signal output end of each scanning drive unit is correspondingly connected with the signal output ends; the first control end of the first-stage scanning driving unit is connected to the first starting signal end; the second control end of the Nth scanning driving unit is connected to the second starting signal end; the scanning driving unit comprises a first scanning driving unit and a second scanning driving unit, wherein the first scanning driving unit is an odd-numbered scanning driving unit in the N-level cascaded scanning driving units, and the second scanning driving unit is an even-numbered scanning driving unit in the N-level cascaded scanning driving units; the reset signal control end of the first scanning driving unit is connected to the second clock signal end, the fourth input end of the first scanning driving unit is connected to the third clock signal end, the first input end of the first scanning driving unit is connected to the first signal input end, the second input end of the first scanning driving unit is connected to the second signal input end, the first level signal input end of the first scanning driving unit is connected to the first level signal end, and the second level signal input end of the first scanning driving unit is connected to the second level signal end; the reset signal control end of the second scanning driving unit is connected to the second clock signal end, the fourth signal input end of the second scanning driving unit is connected to the first clock signal end, the first input end of the second scanning driving unit is connected to the first signal input end, the second input end of the second scanning driving unit is connected to the second signal input end, the first level signal input end of the second scanning driving unit is connected to the first level signal end, and the second level signal input end of the second scanning driving unit is connected to the second level signal end.

In a third aspect, an embodiment of the present application further provides a display panel, where the display panel includes the above scan driving circuit; the display panel also comprises a plurality of scanning signal lines, and the signal output end of the scanning driving circuit is correspondingly connected with the scanning signal lines.

In a fourth aspect, an embodiment of the present application further provides a driving method for driving the scan driving circuit, where the method includes: providing a first start signal to a first-stage scanning driving unit, providing a first clock signal to a first clock signal end, providing a second clock signal to a second clock signal end, providing a third clock signal to a third clock signal end, providing a fourth clock signal to a fourth clock signal end, providing a first level signal to a first signal input end, providing a second level signal to a second signal input end, providing a first level signal to the first level signal end, providing a second level signal to the second level signal end, and outputting a scanning signal to a signal output end step by step from the first-stage scanning driving unit to an Nth-stage scanning driving unit by a scanning driving circuit; the scanning driving circuit provides a second starting signal for the Nth-stage scanning driving unit, provides a first clock signal for the first clock signal end, provides a second clock signal for the second clock signal end, provides a third clock signal for the third clock signal end, provides a fourth clock signal for the fourth clock signal end, provides a second level signal for the first signal input end, provides a first level signal for the second signal input end, provides a first level signal for the first level signal end, provides a second level signal for the second level signal end, and outputs a scanning signal to the signal output end step by step from the Nth-stage scanning driving unit to the first-stage scanning driving unit.

According to the scanning drive unit and the scanning drive circuit of the application, through setting up scanning control module and signal transmission module at the scanning drive unit, scanning control module provides the signal of first input or the signal of second input to signal transmission module under the control of first control end, second control end simultaneously, it can provide scanning signal to each scanning signal line on the display panel in proper order to realize that scanning drive circuit can follow two directions of display panel, thereby improve the stability of display panel display picture.

The reset signal control end of the signal transmission module is directly and electrically connected with the time sequence generating circuit of the display panel through the reset signal line, and the time sequence signal provided by the time sequence generating circuit is directly received, so that the number of ports of the reset signal control end on the display panel and the number of driving transistors on the display panel can be reduced, the layout area of the scanning driving circuit is saved, and the design of a narrow frame is facilitated.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram illustrating an embodiment of a scan driving unit provided in the present application;

FIG. 2 is a schematic diagram illustrating a detailed structure of an embodiment of a scan driving unit provided in the present application;

FIG. 3 is a schematic diagram showing a detailed structure of another embodiment of a scan driving unit provided in the present application;

FIG. 4 is a schematic diagram showing a detailed structure of still another embodiment of a scan driving unit provided in the present application;

fig. 5 is a schematic structural diagram illustrating a specific structure of an embodiment of a power fail safe module provided in the present application;

FIG. 6 is a schematic diagram illustrating an embodiment of a scan driver circuit provided herein;

FIG. 7 is a timing diagram illustrating an operation of a driving method of a scan driving circuit provided in the present application;

FIG. 8 is a schematic diagram showing a timing sequence of a driving method of the scan driving circuit provided in the present application;

FIG. 9 is a schematic diagram illustrating the structure of one embodiment of a display panel provided herein;

FIG. 10 is a schematic diagram illustrating a structure of another embodiment of a display panel provided by the present application;

fig. 11 shows a flowchart of a driving method for driving a scan circuit provided in the present application.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Please refer to fig. 1, which shows a schematic structural diagram of a scan driving unit provided in the present application.

As shown IN fig. 1, the scan driving unit 100 includes a scan control module 11, a signal transmission module 12, a first level signal input terminal VGH, a second level signal input terminal VGL, a first control terminal CK1, a second control terminal CK2, a first input terminal IN1, a second input terminal IN2, a fourth input terminal IN4, and a scan signal output terminal Gout.

The scan control module 11 is electrically connected to the first control terminal CK1, the second control terminal CK2, the first input terminal IN1 and the second input terminal IN 2. The scan control module 11 further includes an output terminal Sout. The scan control module 11 is configured to provide the first input signal received by the first input terminal IN1 or the second input signal received by the second input terminal IN2 to the output terminal Sout under the actions of the first control signal received by the first control terminal CK1 and the second control signal received by the second control terminal CK 2. Here, the first input signal and the second input signal are provided to the output terminal Sout in a time-sharing manner under the control of the first control terminal CK1 and the second control terminal CK 2. For example, in the period T1, the output terminal Sout receives the first input signal; the output terminal Sout receives the second output signal during the period T2.

The signal transmission module 12 is electrically connected to the first level signal input terminal VGH, the second level signal input terminal VGL, the reset signal control terminal RST, the fourth input terminal IN4 and the output terminal Gout. The signal transmission module 12 further includes a third input terminal IN3, wherein the third input terminal IN3 of the signal transmission module 12 is electrically connected to the output terminal Sout of the scan control module. The third input terminal IN3 of the signal transmission module 12 is used for receiving the first input signal or the second input signal provided by the output terminal Sout of the scan control module.

During the scan period, the signal transmission module 12 provides the scan driving signal to the scan signal output terminal Gout under the action of the first input signal or the second input signal received by the third input terminal IN3, the fourth input signal received by the fourth output terminal IN4, the first level signal received by the first level signal input terminal VGH, and the second level signal received by the second level signal input terminal VGL. Here, the first level signal may be a high level signal or a low level signal, and the second level signal may be a high level signal or a low level signal. When the first level signal is a high level signal, the second level signal is a low level signal; when the first level signal is a low level signal, the second level signal is a high level signal.

The scan driving unit 100 further includes a reset signal control terminal RST. During the reset period, the signal transmission module 12 provides the reset signal to the scan signal output terminal Gout under the control of the reset control signal received by the reset signal control terminal RST.

The scan signal output terminal Gout may be electrically connected to a scan signal line on the display panel. One scan driving unit 100 may correspond to one scan signal line on the display panel, and different scan signal lines may correspond to different scan driving units 100. That is, each of the scan driving units 100 may be respectively used to supply a signal to one scan signal line, and the scan signal output terminal Gout of the scan driving unit 100 may be connected to one scan signal line of the display panel.

Alternatively, the scan driving unit 100 is applied to a display panel, which further includes a timing generation circuit and a reset signal line. The reset signal control end RST is directly and electrically connected with the time sequence generating circuit through a reset signal wire. During the reset period, the timing generation circuit supplies the generated reset timing signal to the reset signal control terminal RST through the reset signal line. The reset signal control end RST of the scanning driving unit 100 is directly and electrically connected with the time sequence generating circuit of the display panel through the reset signal line, and the time sequence signal provided by the time sequence generating circuit is directly received, so that the number of ports of the reset signal control end RST and the number of driving transistors in the scanning driving unit 100 can be reduced, and the layout area of the display panel occupied by the scanning driving unit is saved.

Referring to fig. 2, a schematic circuit diagram of an embodiment of a scan driving unit provided in the present application is shown.

As shown IN fig. 2, the scan driving unit 200 includes a scan control module 21, a signal transmission module 22, a first level signal input terminal VGH, a second level signal input terminal VGL, a first control terminal CK1, a second control terminal CK2, a first input terminal IN1, a second input terminal IN2, a fourth input terminal IN4, a reset signal control terminal RST and a scan signal output terminal Gout.

The scan control module 21 includes a first transistor M1, a second transistor M2, and an output terminal Sout.

The gate of the first transistor M1 is connected to the first control terminal CK1, the first pole of the first transistor M1 is connected to the first input terminal IN1, and the second pole of the first transistor M1 is connected to the output terminal Sout. The gate of the second transistor M2 is connected to the second control terminal CK2, the first pole of the second transistor M2 is connected to the second input terminal IN2, and the second pole of the second transistor M2 is connected to the output terminal Sout.

The signal transmission module 22 includes a third input terminal IN3, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a first capacitor C1, and a second capacitor C2.

A gate of the third transistor M3 is connected to a second pole of the fourth transistor M4, a first pole of the third transistor M3 is connected to the third input terminal IN3, and a second pole of the third transistor M3 is connected to the second level signal input terminal VGL. The gate of the fourth transistor M4 is connected to the reset signal control terminal RST, and the first pole of the fourth transistor M4 is connected to the first level signal input terminal VGH. A gate of the fifth transistor M5 is connected to the third input terminal IN3, a first pole of the fifth transistor M5 is connected to the second level signal input terminal VGL, and a second pole of the fifth transistor M5 is connected to the second pole of the fourth transistor M4. A gate of the sixth transistor M6 is connected to the second pole of the fourth transistor M4, a first pole of the sixth transistor M6 is connected to the second level signal input terminal VGL, and a second pole of the sixth transistor M6 is connected to the scan signal output terminal Gout. A gate of the seventh transistor M7 is connected to the third input terminal IN3, a first pole of the seventh transistor M7 is connected to the fourth input terminal IN4, and a second pole of the seventh transistor M7 is connected to the scan signal output terminal Gout. One end of the first capacitor C1 is connected to the second level signal input terminal VGL, and the other end of the first capacitor C1 is connected to the gate of the sixth transistor M6. One end of the second capacitor C2 is connected to the third input terminal IN3, and the other end of the second capacitor C2 is connected to the scan signal output terminal Gout.

In the scan driving unit 200 shown in fig. 2, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 have the same channel type. For example, each of the transistors may be a P-type transistor or an N-type transistor.

In the present embodiment, the first transistor M1 and the second transistor M2 are turned on at different times under the control of the first control terminal CK1 and the second control terminal CK 2. When the first transistor M1 is turned on or the second transistor M2 is turned on, the first input signal received by the first input terminal IN1 or the second input signal received by the second input terminal IN2 is provided to the third input terminal IN3 of the signal transmission module 22.

The sixth transistor M6 and the seventh transistor M7 are enabled during the reset period and the scan period, respectively. During scanning, when a certain scanning signal line on the display panel electrically connected to the scanning driving unit 200 needs to receive a scanning signal, the seventh transistor M7 is turned on under the control of a signal provided by the first input terminal IN1 or the second input terminal IN2, and the fourth input terminal IN4 provides the scanning signal to the scanning signal output terminal Gout. During the reset period, the fourth transistor M4 is turned on under the control of the reset signal control terminal RST, the first level signal received by the first level signal input terminal VGH is provided to the gate of the sixth transistor M6 through the fourth transistor M4, at which time the sixth transistor M6 is turned on, and the second level signal input terminal VGL provides the second level signal to the scan signal output terminal Gout.

Here, the first capacitor C1 and the second capacitor C2 are both storage capacitors. The first capacitor C1 is used for potential holding of the N1 node, and the second capacitor C2 is used for potential holding of the N2 node.

As can be seen from fig. 2, the signal transmission module 22 of the scan driving unit 200 provided in this embodiment only provides the reset control signal from the reset signal control terminal RST, and the reset control signal can be directly provided by the timing generation circuit on the display panel, so that the number of components and ports in the scan driving unit 200 is reduced, thereby simplifying the scan driving unit and reducing the process complexity.

Please refer to fig. 3, which is a schematic circuit diagram of a scan driving unit according to another embodiment of the present application.

As shown IN fig. 3, the scan driving unit 300 includes a scan control module 31, a signal transmission module 32, a first level signal input VGH, a second level signal input VGL, a first control terminal CK1, a second control terminal CK2, a first input terminal IN1, a second input terminal IN2, a fourth input terminal IN4, a reset signal control terminal RST and a scan signal output terminal Gout.

The scan control module 31 includes a first transistor M1, a second transistor M2, and an output terminal Sout. The structure of the scan control module 31 in this embodiment is the same as the structure of the scan control module 21 shown in fig. 2, and the specific structure and connection relationship thereof can refer to fig. 2, which is not described herein again.

The signal transmission module 32 includes a third input terminal IN3, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a first capacitor C1, and a second capacitor C2.

Unlike the scan driving unit 200 shown in fig. 2, in the present embodiment, the signal transmission module 32 of the scan driving unit 200 further includes a third control terminal SET, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.

A gate of the eighth transistor M8 is connected to the third control terminal SET, a first pole of the eighth transistor M8 is connected to the third input terminal IN3, and a second pole of the eighth transistor M8 is connected to the first pole of the third transistor M3. A gate of the ninth transistor M9 is connected to the third input terminal IN3, a first pole of the ninth transistor M9 is connected to the second level signal input terminal VGL, and a second pole of the ninth transistor M9 is connected to the second pole of the fourth transistor M4. A gate of the tenth transistor M10 is connected to the reset signal control terminal RST, a first pole of the tenth transistor M10 is connected to the third input terminal IN3, and a second pole of the tenth transistor M10 is connected to the first pole of the third transistor M3.

Here, each of the transistors described above has a conduction channel of the same type. For example, both P-type transistors and N-type transistors may be used. When the transistors are P-type transistors, the first level signal received by the first level signal input terminal VGH is a low level signal, and the second level signal received by the second level signal input terminal VGL is a high level signal; when the transistors are N-type transistors, the first level signal received by the first level signal input terminal VGH is a high level signal, and the signal received by the second level signal input terminal VGL is a low level signal. In a specific application, each of the transistors is an N-type transistor.

IN the present embodiment, when the third input terminal IN3 transmits a signal to the N2 node, although the fourth transistor M4 is turned off, the N1 node still keeps the first level signal received by the first level signal input terminal VGH unchanged due to the presence of the first capacitor C1, and the third transistor M3 is still IN a conducting state. In this way, the second level signal provided by the second level signal input terminal VGL is transmitted to the second node N2 through the third transistor M3, resulting in the second node N2 being interfered by the second level signal when receiving signals provided by other input terminals. As shown IN fig. 3, by adding the eighth transistor M8 and the tenth transistor M10, the node N2 can receive the signal provided from the third input terminal IN3 only under the control of the third control terminal SET and the reset signal control terminal RST. Meanwhile, the ninth transistor M9 is added, so that the third transistor M3 is turned off before the signal is provided to the second node N2, thereby improving the stability of the scan driving circuit.

Please refer to fig. 4, which is a schematic circuit diagram of a scan driving unit according to still another embodiment of the present disclosure.

As shown IN fig. 4, the scan driving unit 400 includes a scan control module 41, a signal transmission module 42, a first level signal input VGH, a second level signal input VGL, a first control terminal CK1, a second control terminal CK2, a first input terminal IN1, a second input terminal IN2, a fourth input terminal IN4, a reset signal control terminal RST, and a scan signal output terminal Gout.

The scan control module 41 includes a first transistor M1, a second transistor M2, and an output terminal Sout. The structure of the scan control module 41 in this embodiment is the same as the structure of the scan driving module 21 shown in fig. 2, and the specific structure and connection relationship thereof can refer to fig. 2, which is not repeated herein.

The signal transmission module 42 includes a third input terminal IN3, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a first capacitor C1, and a second capacitor C2.

Unlike the scan driving unit shown in the other embodiments, in the present embodiment, the signal transmission module 42 further includes an eleventh transistor M11. A gate of the eleventh transistor M11 is connected to the first level signal input terminal VGH, a first pole of the eleventh transistor M11 is connected to the first pole of the third transistor M3, and a second pole of the eleventh transistor M11 is connected to the gate of the seventh transistor M7. The connection relationship of the other transistors is shown in fig. 2 and 3, and will not be described herein.

During the scan phase, the scan signal provided from the fourth input terminal IN4 has a high amplitude, which is far higher than the amplitude of the first level signal input terminal VGH. When the amplitude is applied to the first terminal of the third transistor M3, a high voltage difference is formed between the first terminal of the third transistor M3578 and the second terminal of the third transistor M3, and the voltage difference far exceeds the tolerance range of the third transistor M3, which may cause the third transistor M3 to be damaged. IN this embodiment, by adding the eleventh transistor M11, when a signal with a higher amplitude is inputted to the fourth input terminal IN4, the eleventh transistor M11 is turned off because the signal has a higher amplitude than the first level signal input terminal VGH, so as to protect the third transistor M3.

Continuing to refer to fig. 5, a schematic diagram of a circuit structure of the power down protection module provided in the present application is shown.

As shown IN fig. 5, the scan driving unit further includes a power down protection module 500, and the power down protection module 500 includes a fifth input terminal IN5, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14.

A gate of the twelfth transistor M12 is connected to the fifth input terminal IN5, a first pole of the twelfth transistor M12 is connected to the second level signal input terminal VGL of any one of the scan driving units shown IN fig. 2 to 4, and a second pole of the twelfth transistor is connected to a gate of the sixth transistor M6 of any one of the scan driving units shown IN fig. 2 to 4. A gate of the thirteenth transistor M13 is connected to the fifth input terminal IN5, a first pole of the thirteenth transistor M13 is connected to the second level signal input terminal VGL of any one of the scan driving units shown IN fig. 2 to 4, and a second pole of the thirteenth transistor M13 is connected to a gate of the seventh transistor M7 of any one of the scan driving units shown IN fig. 2 to 4. A gate of the fourteenth transistor M14 is connected to the fifth input terminal IN5, a first pole of the fourteenth transistor M14 is connected to the first level signal input terminal VGH of any one of the scan driving units shown IN fig. 2-4, and a second pole of the fourteenth transistor is connected to the scan signal output terminal Gout of any one of the scan driving units shown IN fig. 2-4.

It should be noted that the power down protection module 500 shown in fig. 5 needs to be added to any one of the scan driving units shown in fig. 2-4 for use. When each scan driving unit completes the transmission of the scan signal, each transistor IN the power down protection module 500 is turned on under the control of the signal provided by the fifth input terminal IN5, and provides the first level signal to the output terminal of the scan driving unit to eliminate the residual charge on each scan signal line, thereby improving the stability of the next picture display.

Please refer to fig. 6, which shows a schematic structural diagram of an embodiment of the scan driving circuit provided in the present application.

As shown in fig. 6, the scan driving circuit 600 includes N stages of cascaded

scan driving units

61, 62 … 6N, wherein each stage of the

scan driving units

61, 62 … 6N may be the scan driving unit shown in one of fig. 2-4. Wherein N is a positive integer.

In the scan driving circuit 600 shown in fig. 6, the first control terminal CK1 of the second to nth stage scan driving units 62.. 6N is connected to the scan signal output terminal Gout of the previous stage

scan driving units

61, 62.. hi, the scan signal output terminal Gout is connected to the second to nth stage scan driving units 62.. 6N. The second control terminal CK2 of the first to N-1 th stage

scan driving units

61, 62 is connected to the scan signal output terminal Gout of the next stage scan driving unit 62.

The scan driving circuit 61 further includes a first start signal terminal ck1, a second start signal terminal ck2, a first clock signal terminal ck3, a second clock signal terminal ck4, a third clock signal terminal ck5, a fourth clock signal terminal ck6, a first signal input terminal in1, a second signal input terminal in2, a first level signal terminal vgh, a second level signal terminal vgl, and a plurality of signal output terminals, wherein the scan signal output terminals Gout of the

scan driving units

61, 62. The first control terminal CK1 of the first stage scan driving unit 61 is connected to the first start signal terminal CK 1; the second control terminal CK2 of the Nth scan driving unit 6N is connected to the second start signal terminal CK 2.

In the present embodiment, each of the

scan driving units

61, 62.. 6N may include a first scan driving unit 61, 63 … and a second scan driving unit 62, 64.. the first scan driving unit is an odd-numbered scan driving unit 61, 63 … of the N-numbered

scan driving units

61, 62.. 6N, and the second scan driving unit is an even-numbered scan driving unit 62, 64.. 6N of the N-numbered

scan driving units

61, 62.. 6N.

The reset signal control terminal RST of the first scan driving unit 61, 63 … is connected to the fourth clock signal terminal ck6, the fourth input terminal IN4 of the first scan driving unit 61, 63 … is connected to the third clock signal terminal ck5, the first input terminal IN1 of the first scan driving unit 61, 63 … is connected to the first signal input terminal IN1, the second input terminal IN2 of the first scan driving unit 61, 63 … is connected to the second signal input terminal IN2, the first level signal input terminal VGH of the first scan driving unit 61, 63 … is connected to the first level signal terminal VGH, and the second level signal input terminal VGL of the first scan driving unit 61, 63 … is connected to the second level signal terminal VGL.

A reset signal control terminal RST of the second scan driving unit 62, 64.. is connected to the second clock signal terminal ck4, a fourth input terminal IN4 of the second scan driving unit 62, 64.. is connected to the first clock signal terminal ck3, a first input terminal IN1 of the second scan driving unit 62, 64.. is connected to the first signal input terminal IN1, a second input terminal IN2 of the second scan driving unit 62, 64.. is connected to the second signal input terminal IN2, a first level signal input terminal VGH of the second scan driving unit 62, 64.. is connected to the first level signal terminal VGH, and a second level signal input terminal VGL of the second scan driving unit 62, 64.. is connected to the second level signal terminal VGL.

In the scan driving circuit 600 shown in this embodiment, the scan driving unit is divided into the first scan driving unit and the second scan driving unit, so that during the scanning period, the scan driving circuit 600 can sequentially output the scan signals from the first stage to the nth stage, and also sequentially output the scan signals from the nth stage to the first stage, that is, the scan driving circuit 600 can provide the scan signals to the scan signal lines from different terminals. Due to the effects of aging, signal delay and the like of the scanning driving circuit after long-time working, errors exist in the scanning signals received by the first-stage scanning signal line and the last-stage scanning signal line, so that the scanning signals received by the scanning signal lines on the display panel can be more uniform by providing the scanning signals to the scanning signal lines from different ends, and the picture display effect of the display panel is improved.

In some optional implementations of the present embodiment, the third control terminal SET of the first scan driving unit 61, 63 … is connected to the first clock signal terminal ck3, and the third control terminal SET of the second scan driving unit is connected to the third clock signal terminal ck 5. In this embodiment, each stage of the scan driving unit in the scan driving circuit may be the scan driving unit shown in any of the embodiments of fig. 3 to 4.

IN some optional implementations of the present embodiment, the scan driving circuit 600 further includes a fifth clock signal terminal ck7, and the fifth input terminal IN5 of each scan driving unit is connected to the fifth clock signal terminal ck 7.

With reference to fig. 7, which shows a driving sequence for driving the scan driving circuit 600 shown in fig. 6 according to the present application, in conjunction with the scan driving unit 400 shown in fig. 4 and the scan driving circuit 600 shown in fig. 6, the operation principle of the scan driving circuit is explained in detail by taking the first level signal as a high level signal and the second level signal as a low level signal, where the transistors shown in fig. 4 are all NMOS transistors as examples.

In fig. 7, in the first stage T1:

first, a high level signal is supplied to the first signal input terminal in1, and at this time, no signal is inputted to the second signal input terminal in2, a high level signal is supplied to the first enable signal terminal ck1 or the second enable signal terminal ck2, a high level signal is supplied to the first clock signal terminal ck3, a low level signal is supplied to the second clock signal terminal ck4, a low level signal is supplied to the fifth clock signal terminal ck5, and a low level signal is supplied to the sixth clock signal terminal ck 6. At this time, the first stage scan driving unit operates under the control of the first start signal terminal ck 1. The first transistor M1, the second transistor M2, the eighth transistor M8, and the eleventh transistor M11 of the first scan driving unit are turned on, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off, the first input terminal IN1 provides the received high level signal to the node N2 through the first transistor M1, the eighth transistor M8, and the eleventh transistor M11, i.e., the gate of the seventh transistor M7, at which time the seventh transistor M7 is turned on, and the capacitor C2 is charged. It should be noted that at this stage, the fifth transistor M5 and the ninth transistor M9 are turned on, and the low level signal provided by the second level new signal terminal VGL is provided to the gate of the third transistor M3 through the fifth transistor M5 and the ninth transistor M9, so that the third transistor M3 is IN a deep off state, and when the third transistor M3 is IN an on state, the low level signal of the second level signal input terminal VGL is provided to the node N2 through the third transistor M3, which causes the high level signal provided by the first input terminal IN1 to the node N2 to be interfered, thereby affecting the potential of the node N2.

Then, a low level signal is provided to the first start signal terminal ck1 or the second start signal terminal ck2, a low level signal is provided to the first clock signal terminal ck3, a high level signal is provided to the second clock signal terminal ck4, a low level signal is provided to the third clock signal terminal ck5, and a low level signal is provided to the sixth clock signal terminal ck 2. For the first stage scan driving unit, except for the seventh transistor M7 and the eleventh transistor M11, the other transistors are turned off, the node N2 maintains the high level potential at the previous moment under the action of the capacitor C2, and at this time, the seventh transistor M7 maintains the on state. For the second stage scan driving unit, the fourth transistor M4 and the tenth transistor M10 are turned on by the high level signal received by the reset signal control terminal RST, the high level signal received by the first level signal input terminal VGH is provided to the gates of the third transistor M3 and the sixth transistor M6, the third transistor M3 and the sixth transistor M6 are turned on, the low level signal received by the second level signal input terminal VGL is provided to the scan signal output terminal Gout, and the second stage scan driving unit is in a reset state at this time.

Then, a low level signal is provided to the first start signal terminal ck1 or the second start signal terminal ck2, a low level signal is provided to the first clock signal terminal ck3, a low level signal is provided to the second clock signal terminal ck4, a high level signal is provided to the third clock signal terminal ck5, and a low level signal is provided to the sixth clock signal terminal ck 2. At this time, for the first stage scan driving unit, the seventh transistor M7 is turned on, the node N2 maintains the high level potential at the previous time under the action of the capacitor C2, at this time, the other transistors except the seventh transistor M7 and the eleventh transistor M11 are turned off, the fourth signal terminal IN4 provides the received high level signal to the output terminal Gout through the seventh transistor M7, that is, the scan signal line electrically connected to the first stage scan driving unit receives the scan signal, and at the same time, the signal is provided to the first control terminal CK1 of the second stage scan driving unit as the start signal of the second stage scan driving unit, and at this time, the second stage scan driving unit starts to operate. For the second stage scan driving unit, the first transistor M1, the second transistor M2, the eighth transistor M8, and the eleventh transistor M11 are turned on, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off, and the high level signal received by the first input terminal IN1 is provided to the node N2 and the control terminal of the seventh transistor M7 through the first transistor M1, the eighth transistor M8, and the eleventh transistor M11, at which time the seventh transistor M7 is turned on.

Finally, a low level signal is provided to the first start signal terminal ck1 or the second start signal terminal ck2, a low level signal is provided to the first clock signal terminal ck3, a low level signal is provided to the second clock signal terminal ck4, a low level signal is provided to the third clock signal terminal ck5, and a high level signal is provided to the sixth clock signal terminal. For the first stage scan driving unit, the fourth transistor M4 and the tenth transistor M10 are turned on by the high level signal received by the reset signal control terminal RST, the high level signal received by the first level signal input terminal VGH is provided to the gates of the third transistor M3 and the sixth transistor M6, the third transistor M3 and the sixth transistor M6 are turned on, the low level signal received by the second level signal input terminal VGL is provided to the scan signal output terminal Gout, and the first stage scan driving unit is in the reset state at this stage. At this point, the first-stage scan driving unit completes the scan driving. For the second stage scan driving unit, the node N2 is kept at the high level potential at the previous moment by the capacitor C2, and at this time, the seventh transistor M7 and the eleventh transistor M11 are kept in the on state, and the rest transistors are all turned off.

In the second stage T2:

first, a low signal is provided to the first start signal terminal ck1 or the second start signal terminal ck2, a low signal is provided to the first clock signal terminal ck3, a low signal is provided to the second clock signal terminal ck4, a low signal is provided to the third clock signal terminal ck5, and a low signal is provided to the sixth clock signal terminal. At this time, for the second stage scan driving unit, the seventh transistor M7 is turned on, the node N2 maintains the high level potential at the previous time under the action of the capacitor C2, at this time, the other transistors except the seventh transistor M7 and the eleventh transistor M11 are turned off, the fourth signal terminal IN4 provides the received high level signal to the output terminal Gout through the seventh transistor M7, that is, the scan signal line electrically connected to the second stage scan driving unit receives the scan signal, and at the same time, the signal is provided to the first control terminal CK1 of the third stage scan driving unit as the start signal of the third stage scan driving unit, and at this time, the third stage scan driving unit starts to operate. For the third-stage scan driving unit, the first transistor M1, the second transistor M2, the eighth transistor M8, and the eleventh transistor M11 are turned on, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off, a high level signal received by the first input terminal IN1 is provided to the node N2 and the control terminal of the seventh transistor M7 through the first transistor M1, the eighth transistor M8, and the eleventh transistor M11, and at this time, the seventh transistor M7 is turned on.

Then, a low signal is supplied to the first start signal terminal ck1 or the second start signal terminal ck2, a low signal is supplied to the first clock signal terminal ck3, a high signal is supplied to the second clock signal terminal ck4, a low signal is supplied to the third clock signal terminal ck5, and a low signal is supplied to the sixth clock signal terminal ck 6. At this time, for the second stage scan driving unit, the fourth transistor M4 and the tenth transistor M10 are turned on by the high level signal received by the reset signal control terminal RST, the high level signal received by the first level signal input terminal VGH is provided to the gates of the third transistor M3 and the sixth transistor M6, the third transistor M3 and the sixth transistor M6 are turned on, the low level signal received by the second level signal input terminal VGL is provided to the scan signal output terminal Gout, and the second stage scan driving unit is in the reset state at this stage. At this point, the second-stage scan driving unit completes the scan driving. For the third stage scan driving unit, except for the seventh transistor M7 and the eleventh transistor M11, the other transistors are turned off, the node N2 maintains the high level potential at the previous moment under the action of the capacitor C2, and at this time, the seventh transistor M7 maintains the on state.

In the third stage T3:

first, a low signal is provided to the first start signal terminal ck1 or the second start signal terminal ck2, a low signal is provided to the first clock signal terminal ck3, a low signal is provided to the second clock signal terminal ck4, a high signal is provided to the third clock signal terminal ck5, and a low signal is provided to the sixth clock signal terminal ck 6. At this time, for the third stage scan driving unit, the seventh transistor M7 is turned on, the node N2 maintains the high level potential at the previous moment under the action of the capacitor C2, at this time, the other transistors except the seventh transistor M7 and the eleventh transistor M11 are turned off, the fourth signal terminal IN4 provides the received high level signal to the output terminal Gout through the seventh transistor M7, that is, the scan signal line electrically connected to the third stage scan driving unit receives the scan signal, and at the same time, the signal is provided to the first control terminal CK1 of the fourth stage scan driving unit as the start signal of the fourth stage scan driving unit, and at this time, the fourth stage scan driving unit starts to operate.

Then, a low signal is provided to the first start signal terminal ck1 or the second start signal terminal ck2, a low signal is provided to the first clock signal terminal ck3, a low signal is provided to the second clock signal terminal ck4, a low signal is provided to the third clock signal terminal ck5, and a high signal is provided to the sixth clock signal terminal ck 6. At this time, for the second stage scan driving unit, the fourth transistor M4 and the tenth transistor M10 are turned on by the high level signal received by the reset signal control terminal RST, the high level signal received by the first level signal input terminal VGH is provided to the gates of the third transistor M3 and the sixth transistor M6, the third transistor M3 and the sixth transistor M6 are turned on, the low level signal received by the second level signal input terminal VGL is provided to the scan signal output terminal Gout, and the third stage scan driving unit is in the reset state at this stage. Therefore, the third-stage scanning driving unit completes scanning driving.

In the fourth to nth scan driving units, the working mode of the odd scan driving unit may refer to the working mode of the first or third scan driving unit, and the working mode of the even scan driving unit may refer to the working mode of the second scan driving unit, which is not described herein again.

With continued reference to fig. 8, which shows another driving sequence provided by the present application for driving the scan driving circuit 600 shown in fig. 6, in conjunction with the scan driving unit 400 shown in fig. 4 and the scan driving circuit 600 shown in fig. 6, the operation principle of the scan driving circuit is explained in detail by taking the first level signal as a high level signal and the second level signal as a low level signal, where the transistors shown in fig. 4 are all NMOS transistors, and the last stage of the scan driving unit in the scan driving circuit 600 shown in fig. 6 is an even-numbered stage of the scan driving unit as an example.

In fig. 8, in the first stage T1:

first, a high signal is supplied to the second signal input terminal in2, and at this time, the first signal input terminal in1 does not receive a signal, a high signal is supplied to the first start signal terminal ck1 or the second start signal terminal ck2, a low signal is supplied to the first clock signal terminal ck3, a low signal is supplied to the second clock signal terminal ck4, a high signal is supplied to the third clock signal terminal ck5, and a low signal is supplied to the fourth clock signal terminal ck 6. At this time, the nth stage scan driving unit operates under the control of the second start signal terminal ck 2. The first transistor M1, the second transistor M2, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9 and the eleventh transistor M11 of the nth-pole scan driving unit are turned on, the third transistor M3, the fourth transistor M4 and the sixth transistor M6 are turned off, the second input terminal IN2 provides the received high-level signal to the node N2 through the first transistor M1, the eighth transistor M8 and the eleventh transistor M11, that is, the gate of the seventh transistor M7, at this time, the seventh transistor M7 is turned on, and the capacitor C2 is charged.

Then, a low signal is provided to the first start signal terminal ck1 or the second start signal terminal ck2, a low signal is provided to the first clock signal terminal ck3, a low signal is provided to the second clock signal terminal ck4, a low signal is provided to the third clock signal terminal ck5, and a high signal is provided to the sixth clock signal terminal ck 6. For the nth-stage scan driving unit, since the point N2 maintains the high-level potential at the previous time by the capacitor C2, the seventh transistor M7 and the eleventh transistor M11 maintain the on state at this time, and the remaining transistors are all turned off. For the N-1 stage scan driving unit, the fourth transistor M4 and the tenth transistor M10 are turned on by the high level signal received by the reset signal control terminal, the high level signal received by the first level signal input terminal VGH is provided to the third transistor M3 and the sixth transistor M6, the third transistor M3 and the sixth transistor M6 are turned on, the low level signal received by the second level signal input terminal VGL is provided to the scan signal output terminal Gout, and the N-1 stage scan driving unit is in the reset state.

Then, a low level signal is provided to the first start signal terminal ck1 or the second start signal terminal ck2, a high level signal is provided to the first clock signal terminal ck3, a low level signal is provided to the second clock signal terminal ck4, a low level signal is provided to the third clock signal terminal ck5, and a low level signal is provided to the sixth clock signal terminal ck 2. At this time, for the nth stage scan driving unit, the seventh transistor M7 is turned on, the node N2 maintains the high level potential at the previous time under the action of the capacitor C2, at this time, the other transistors except the seventh transistor M7 and the eleventh transistor M11 are turned off, the fourth signal terminal IN4 provides the received high level signal to the output terminal Gout through the seventh transistor M7, that is, the scan signal line electrically connected to the nth stage scan driving circuit receives the scan signal, and at the same time, the signal is provided to the second control terminal CK2 of the nth-1 stage scan driving unit as the start signal of the nth-1 stage scan driving unit, and at this time, the nth-1 stage scan driving unit starts to operate. For the N-1 th scan driving unit, the first transistor M1, the second transistor M2, the eighth transistor M8, and the eleventh transistor M11 are turned on, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off, and the high level signal received at the second input terminal IN2 is provided to the node N2 and the control terminal of the seventh transistor M7 through the first transistor M1, the eighth transistor M8, and the eleventh transistor M11, at which time the seventh transistor M7 is turned on.

Finally, a low level signal is provided to the first start signal terminal ck1 or the second start signal terminal ck2, a low level signal is provided to the first clock signal terminal ck3, a high level signal is provided to the second clock signal terminal ck4, a low level signal is provided to the third clock signal terminal ck5, and a low level signal is provided to the sixth clock signal terminal. For the nth scan driving unit, the fourth transistor M4 and the tenth transistor M10 are turned on by the high level signal received by the reset signal control terminal RST, the high level signal received by the first level signal input terminal VGH is provided to the gates of the third transistor M3 and the sixth transistor M6, the third transistor M3 and the sixth transistor M6 are turned on, the low level signal received by the second level signal input terminal VGL is provided to the scan signal output terminal Gout, and the nth scan driving unit is in the reset state at this stage. At this point, the nth scan driving unit completes the scan driving. For the N-1 st scan driving unit, the node N2 is kept at the high level potential at the previous moment by the capacitor C2, and at this time, the seventh transistor M7 and the eleventh transistor M11 are kept in the on state, and the rest transistors are all turned off.

In the second stage T2:

first, a low signal is provided to the first start signal terminal ck1 or the second start signal terminal ck2, a low signal is provided to the first clock signal terminal ck3, a low signal is provided to the second clock signal terminal ck4, a high signal is provided to the third clock signal terminal ck5, and a low signal is provided to the sixth clock signal terminal. At this time, for the N-1 th scan driving unit, the seventh transistor M7 is turned on, the node N2 maintains the high level potential at the previous time under the action of the capacitor C2, at this time, the other transistors except the seventh transistor M7 and the eleventh transistor M11 are turned off, the fourth signal terminal IN4 provides the received high level signal to the output terminal Gout through the seventh transistor M7, that is, the scan signal line electrically connected to the N-1 th scan driving circuit receives the scan signal, and at the same time, the signal is provided to the second control terminal CK2 of the N-2 th scan driving unit as the start signal of the N-2 th scan driving unit, and at this time, the N-2 th scan driving unit starts to operate. For the N-2 th scan driving unit, the first transistor M1, the second transistor M2, the eighth transistor M8, and the eleventh transistor M11 are turned on, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off, a high level signal received by the first input terminal IN1 is provided to the node N2 and the control terminal of the seventh transistor M7 through the first transistor M1, the eighth transistor M8, and the eleventh transistor M11, and at this time, the seventh transistor M7 is turned on.

Then, a low signal is provided to the first start signal terminal ck1 or the second start signal terminal ck2, a low signal is provided to the first clock signal terminal ck3, a low signal is provided to the second clock signal terminal ck4, a low signal is provided to the third clock signal terminal ck5, and a high signal is provided to the sixth clock signal terminal ck 6. At this time, for the N-1 th scan driving unit, the fourth transistor M4 and the tenth transistor M10 are turned on by the high level signal received by the reset signal control terminal RST, the high level signal received by the first level signal input terminal VGH is provided to the gates of the third transistor M3 and the sixth transistor M6, the third transistor M3 and the sixth transistor M6 are turned on, the low level signal received by the second level signal input terminal VGL is provided to the scan signal output terminal Gout, and the N-1 th scan driving unit is in the reset state at this stage. At this point, the N-1 st stage scan driving unit completes the scan driving. For the N-2 th scan driving unit, except for the seventh transistor M7 and the eleventh transistor M11, the other transistors are turned off, the node N2 maintains the high level potential at the previous moment under the action of the capacitor C2, and at this time, the seventh transistor M7 maintains the on state.

In the fourth to nth scan driving units, the working mode of the odd scan driving unit may refer to the working mode of the N-1 st scan driving unit, and the working mode of the even scan driving unit may refer to the working mode of the nth scan driving unit, which is not described herein again.

As can be seen from fig. 8, unlike the driving timing shown in fig. 7, the signal received at the first signal input terminal in1 is a low level signal, and the signal received at the second signal input terminal in2 is a high level signal in this embodiment. Thus, when the scan driving circuit shown in fig. 6 is driven with the driving timing shown in fig. 7, the scan driving circuit 600 outputs the scan driving signal step by step from the output terminal of the first-stage scan driving unit to the output terminal of the nth-stage scan driving unit. When the scan driving circuit shown in fig. 6 is driven by the driving timing shown in this embodiment, the scan driving circuit 600 outputs the scan driving signal from the output terminal of the nth stage scan driving unit to the output terminal of the first stage scan driving unit in a stepwise manner. Thus, when the scan driving circuit shown in fig. 6 is driven by the driving timing shown in fig. 7 and the driving timing shown in fig. 8, the forward scanning and the reverse scanning of the scan lines on the display panel can be realized, so that when the scan signal is supplied to the scan signal lines only from one side, the signal supplied to the scan output terminal by the last stage of scan driving unit due to the overlong working time of the scan driving circuit is prevented from being delayed or distorted, thereby improving the display effect of the display panel.

In some alternative implementations, the driving timing shown in fig. 7 or fig. 8 further includes a driving signal provided to the fifth clock signal terminal ck7 of the scan driving circuit shown in fig. 6. After the display of the image on the display panel is completed, a high level signal is provided to the fifth clock signal terminal ck7, and at this time, the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14 are all turned on, and the other transistors in each scan driving unit are all turned off. In the same time, the first level signal input terminal in each scan driving unit provides a high level signal to the scan signal output terminal Gout of each scan driving unit through the fourteenth transistor M14, and each scan signal line receives the high level signal provided by the first level signal input terminal VGH, so that the residual signal on each scan signal line can be eliminated, and the stability of next image display can be improved.

Please refer to fig. 9, which shows a schematic structural diagram of a display panel provided in the present application.

As shown in fig. 9, the display panel 900 includes a scan driving circuit 91, wherein the scan driving circuit 91 includes a plurality of output terminals S1, S2, S3 … Sn-1, Sn +1, and a scan signal line 92 electrically connected to each of the output terminals in the scan driving circuit 91. Here, the output terminals of the scan driving circuit 91 are connected to the scan signal lines 92 in a one-to-one correspondence.

Here, one scanning signal line is electrically connected to one row of pixel units 93 on the display panel 900. During display, the scanning signal line 93 is used to supply a scanning signal to each pixel unit.

Please refer to fig. 10, which shows a schematic structural diagram of another display panel provided in the present application.

As shown in fig. 10, unlike the display panel shown in fig. 9, in the present embodiment, the display panel 1000 includes two scan driving circuits, namely a first scan driving circuit 101 and a second scan driving circuit 102, wherein the first scan driving circuit 101 is electrically connected to the odd-numbered row scan signal lines 103 on the display panel 1000, and the second scan driving circuit 102 is electrically connected to the even-numbered row scan signal lines 103 on the display panel 1000.

During the display period, the first scan driver circuit 101 and the second scan driver circuit 102 alternately supply scan signals to scan signal lines of the display panel. For example, the output terminal S1 of the first scan driving circuit 101 supplies a scan driving signal to a scan signal line electrically connected thereto; next, the output terminal S2 of the second scan driving circuit 102 provides a scan driving signal to the scan signal line electrically connected thereto; then, the output terminal S3 of the first scan drive circuit 101 supplies a scan drive signal to the scan signal line electrically connected thereto, and so on.

During display, each scanning signal line 103 supplies a scanning signal to each pixel unit 104 electrically connected thereto.

It should be noted that although the last row of the scan signal lines of the display panel 1000 is connected to the second scan driving circuit 102, the present application is not limited thereto, and the last row of the scan signal lines can be connected to the first scan driving circuit or the second scan driving circuit according to the requirements of the application scenario.

By providing two scan driving circuits on the display panel 1000, the display panel 1000 can perform bilateral driving, thereby enhancing the driving capability of the display panel 1000.

As shown in fig. 11, the present application also discloses a driving method of the scan driving circuit, which is used for driving the scan driving circuit of each of the above embodiments.

And step 111, providing a first start signal to the first-stage scanning driving unit, providing a first clock signal to the first clock signal terminal, providing a second clock signal to the second clock signal terminal, providing a third clock signal to the third clock signal terminal, providing a fourth clock signal to the fourth clock signal terminal, providing a first level signal to the first signal input terminal, providing a second level signal to the second signal input terminal, providing a first level signal to the first level signal terminal, providing a second level signal to the second level signal terminal, and outputting a scanning signal to the signal output terminal step by step from the first-stage scanning driving unit to the nth-stage scanning driving unit by the scanning driving circuit.

Step 112, providing a second start signal to the nth stage scan driving unit, providing a first clock signal to the first clock signal terminal, providing a second clock signal to the second clock signal terminal, providing a third clock signal to the third clock signal terminal, providing a fourth clock signal to the fourth clock signal terminal, providing a second level signal to the first signal input terminal, providing a first level signal to the second signal input terminal, providing a first level signal to the first level signal terminal, providing a second level signal to the second level signal terminal, and outputting a scan signal to the signal output terminal step by step from the nth stage scan driving unit to the first stage scan driving unit by the scan driving circuit.

The specific working principle of the driving method shown in this embodiment can refer to the working timing sequence shown in fig. 7 and 8, and is not described herein again.

It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A scan drive unit, comprising: the scanning circuit comprises a scanning control module, a signal transmission module, a first level signal input end VGH, a second level signal input end VGL, a first control end CK1, a second control end CK2, a first input end IN1, a second input end IN2, a fourth input end IN4, a reset signal control end RST and a scanning signal output end Gout; wherein:

the scan control module comprises an output terminal Sout, and the scan control module provides a first input signal received by the first input terminal IN1 or a second input signal received by the second input terminal IN2 to the output terminal Sout under the action of a first control signal received by the first control terminal CK1 and a second control signal received by the second control terminal CK 2;

the signal transmission module comprises a third input terminal IN3, the third input terminal IN3 is electrically connected with the output terminal Sout, the third input terminal IN3 receives the first input signal or the second input signal provided by the output terminal Sout;

during scanning, the signal transmission module provides a scanning driving signal to the scanning signal output terminal Gout under the combined action of the first input signal or the second input signal received by the third input terminal IN3, the fourth input signal received by the fourth input terminal IN4, the first level signal received by the first level signal input terminal VGH, and the second level signal received by the second level signal input terminal VGL; during the reset period, the signal transmission module provides a reset signal to the scanning signal output end Gout under the control of a reset control signal received by the reset signal control end RST;

the signal transmission module further includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a first capacitor C1, a second capacitor C2, a third control terminal SET, and an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10; wherein:

a gate of the third transistor M3 is connected to a second pole of the fourth transistor, a first pole of the third transistor M3 is connected to the third input terminal IN3, and a second pole of the third transistor M3 is connected to the second level signal input terminal VGL;

the gate of the fourth transistor M4 is connected to the reset signal control terminal RST, and the first pole of the fourth transistor M4 is connected to the first level signal input terminal VGH;

a gate of the fifth transistor M5 is connected to the third input terminal IN3, a first pole of the fifth transistor M5 is connected to the second level signal input terminal VGL, and a second pole of the fifth transistor M5 is connected to a second pole of the fourth transistor M4;

a gate of the sixth transistor M6 is connected to the second pole of the fourth transistor M4, a first pole of the sixth transistor M6 is connected to the second level signal input terminal VGL, and a second pole of the sixth transistor M6 is connected to the scan signal output terminal Gout;

a gate of the seventh transistor M7 is connected to the third input terminal IN3, a first pole of the seventh transistor M7 is connected to the fourth input terminal IN4, and a second pole of the seventh transistor M7 is connected to the scan signal output terminal Gout;

one end of the first capacitor is connected to the second level signal input terminal VGL, and the other end of the first capacitor is connected to the gate of the sixth transistor M6;

one end of the second capacitor is connected to the third input terminal IN3, and the other end of the second capacitor C2 is connected to the scan signal output terminal Gout;

a gate of the eighth transistor M8 is connected to the third control terminal SET, a first pole of the eighth transistor M8 is connected to the third input terminal IN3, and a second pole of the eighth transistor M8 is connected to a first pole of the third transistor M3;

a gate of the ninth transistor M9 is connected to the third input terminal IN3, a first pole of the ninth transistor M9 is connected to the second level signal input terminal VGL, and a second pole of the ninth transistor M9 is connected to a second pole of the fourth transistor M4;

a gate of the tenth transistor M10 is connected to the reset signal control terminal RST, a first pole of the ninth transistor M9 is connected to the third input terminal IN3, and a second pole of the ninth transistor M9 is connected to a first pole of the third transistor M3.

2. The scan driving unit according to claim 1, wherein the scan driving unit is applied to a display panel including a timing generation circuit and a reset signal line; wherein:

the reset signal control end RST is directly and electrically connected with the time sequence generating circuit through the reset signal wire;

during reset, the timing generation circuit supplies the generated reset timing signal to the reset signal control terminal through the reset signal line.

3. The scan driving unit of claim 1, wherein the scan control module comprises a first transistor M1 and a second transistor M2; wherein:

the gate of the first transistor M1 is connected to the first control terminal CK1, the first pole of the first transistor M1 is connected to the first input terminal IN1, and the second pole of the first transistor M1 is connected to the output terminal Sout;

the gate of the second transistor M2 is connected to the second control terminal CK2, the first pole of the second transistor M2 is connected to the second input terminal IN2, and the second pole of the second transistor M2 is connected to the output terminal Sout.

4. The scan driving unit of claim 1, wherein the signal transmission module further comprises an eleventh transistor M11, wherein:

a gate of the eleventh transistor M11 is connected to the first level signal input terminal VGH, a first pole of the eleventh transistor M11 is connected to the first pole of the third transistor M3, and a second pole of the eleventh transistor M11 is connected to the gate of the seventh transistor M7.

5. The scan driving unit according to claim 1, further comprising a power down protection module, wherein the power down protection module comprises a fifth input terminal IN5, and the power down protection module is configured to provide a power down protection signal to each scan signal output terminal Gout after the scan signal is completely output; wherein:

the power failure protection module comprises a twelfth transistor, a thirteenth transistor and a fourteenth transistor;

a gate of the twelfth transistor is connected to the fifth input terminal, a first pole of the twelfth transistor is connected to the second level signal input terminal VGL, and a second pole of the twelfth transistor is connected to the gate of the sixth transistor M6;

a gate of the thirteenth transistor is connected to the fifth input terminal, a first pole of the thirteenth transistor is connected to the second level signal input terminal VGL, and a second pole of the thirteenth transistor is connected to a gate of the seventh transistor M7;

a gate of the fourteenth transistor is connected to the fifth input terminal, a first pole of the fourteenth transistor is connected to the first level signal input terminal VGH, and a second pole of the fourteenth transistor is connected to the scan signal output terminal Gout.

6. A scan driving circuit, comprising N stages of scan driving units according to any one of claims 1 to 5, wherein N is a positive integer; wherein:

the first control terminal CK1 of the second to nth stages of the scan driving units is connected to the scan signal output terminal Gout of the previous stage of the scan driving unit;

the second control terminal CK2 of the scan driving unit of the first to N-1 th stages is connected to the scan signal output terminal Gout of the scan driving unit of the next stage;

the scanning driving circuit further comprises a first start signal terminal ck1, a second start signal terminal ck2, a first clock signal terminal ck3, a second clock signal terminal ck4, a third clock signal terminal ck5, a fourth clock signal terminal ck6, a first signal input terminal in1, a second signal input terminal in2, a first level signal terminal vgh, a second level signal terminal vgl and a plurality of signal output terminals, wherein the scanning signal output terminals Gout of the scanning driving units of each stage are connected with the signal output terminals in a one-to-one correspondence manner;

the first control terminal CK1 of the first stage scan driving unit is connected to the first start signal terminal CK 1;

the second control terminal CK2 of the Nth scan driving unit is connected to the second start signal terminal CK 2; the scanning driving unit comprises a first scanning driving unit and a second scanning driving unit, wherein the first scanning driving unit is an odd-numbered scanning driving unit in the N-level cascaded scanning driving units, and the second scanning driving unit is an even-numbered scanning driving unit in the N-level cascaded scanning driving units;

the reset signal control terminal RST of the first scan driving unit is connected to the fourth clock signal terminal ck6, the fourth input terminal IN4 of the first scan driving unit is connected to the third clock signal terminal ck5, the first input terminal IN1 of the first scan driving unit is connected to the first signal input terminal IN1, the second input terminal IN2 of the first scan driving unit is connected to the second signal input terminal IN2, the first level signal input terminal VGH of the first scan driving unit is connected to the first level signal terminal VGH, and the second level signal input terminal VGL of the first scan driving unit is connected to the second level signal terminal VGL;

the reset signal control terminal RST of the second scan driving unit is connected to the second clock signal terminal ck4, the fourth input terminal IN4 of the second scan driving unit is connected to the first clock signal terminal ck3, the first input terminal IN1 of the second scan driving unit is connected to the first signal input terminal IN1, the second input terminal IN2 of the second scan driving unit is connected to the second signal input terminal IN2, the first level signal input terminal VGH of the second scan driving unit is connected to the first level signal terminal VGH, and the second level signal input terminal VGL of the second scan driving unit is connected to the second level signal terminal VGL.

7. The scan driving circuit of claim 6, wherein the third control terminal SET of the first scan driving unit is connected to the first clock signal terminal ck3, and the third control terminal SET of the second scan driving unit is connected to the third clock signal terminal ck 5.

8. The scan driving circuit of claim 6, further comprising a fifth clock signal terminal ck7, wherein the fifth input terminal IN5 of each scan driving unit is connected to the fifth clock signal terminal ck 7.

9. A display panel characterized in that the display panel comprises the scan driver circuit according to any one of claims 6 to 8;

the display panel also comprises a plurality of scanning signal lines, and the signal output end of the scanning driving circuit is correspondingly connected with the scanning signal lines.

10. The display panel according to claim 9, wherein the display panel comprises a first scan driver circuit and a second scan driver circuit, wherein:

the signal output end of the first scanning driving circuit is correspondingly connected with the odd-numbered scanning signal lines one by one;

and the signal output ends of the second scanning driving circuits are correspondingly connected with the even number scanning signal lines one to one.

11. A driving method of driving the scan driving circuit according to claim 6, the method comprising:

providing a first start signal to the first-stage scan driving unit, providing a first clock signal to the first clock signal terminal, providing a second clock signal to the second clock signal terminal, providing a third clock signal to the third clock signal terminal, providing a fourth clock signal to the fourth clock signal terminal, providing a first level signal to the first signal input terminal, providing a second level signal to the second signal input terminal, providing a first level signal to the first level signal terminal, providing a second level signal to the second level signal terminal, and outputting a scan signal to the signal output terminal step by step from the first-stage scan driving unit to the nth-stage scan driving unit by the scan driving circuit;

providing a second start signal to the nth stage scan driving unit, providing a first clock signal to the first clock signal terminal, providing a second clock signal to the second clock signal terminal, providing a third clock signal to the third clock signal terminal, providing a fourth clock signal to the fourth clock signal terminal, providing a second level signal to the first signal input terminal, providing a first level signal to the second signal input terminal, providing a first level signal to the first level signal terminal, providing a second level signal to the second level signal terminal, and outputting a scan signal to the signal output terminal step by step from the nth stage scan driving unit to the first stage scan driving unit.