CN107579739B - Feedforward delta-sigma analog-to-digital converter - Google Patents
Feedforward delta-sigma analog-to-digital converter Download PDFInfo
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- CN107579739B CN107579739B CN201610521180.7A CN201610521180A CN107579739B CN 107579739 B CN107579739 B CN 107579739B CN 201610521180 A CN201610521180 A CN 201610521180A CN 107579739 B CN107579739 B CN 107579739B
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Abstract
The invention provides a feedforward delta-sigma analog-to-digital converter, which integrates a feedback circuit, an addition circuit and a quantization circuit. The integrated circuit structure has the advantage of high stability, does not need an active circuit, and adopts a control circuit of a continuous approximation method, so that the multi-bit quantization function can be realized by only one comparator.
Description
Technical Field
The invention relates to the field of analog-to-digital converters, in particular to a feedforward delta-sigma analog-to-digital modulator.
Background
Sigma-delta modulation (SDM) is widely used in various electronic components, such as: analog-to-digital converters, switched capacitor filters, frequency synthesizers, and wireless communication systems. When the delta-sigma modulator is applied to an analog-to-digital converter, the higher the order of the delta-sigma modulator is, the better the noise shaping effect is, and the advantage of improving the signal-to-noise ratio (SNR) is achieved. Since the n-th order delta-sigma modulator needs n integrators, the power consumption and the circuit area are increased when the structure of the high-order delta-sigma modulator with more than two orders is adopted. In addition, the higher the delta-sigma modulation order is, the more unstable the circuit is.
In the conventional technology, a delta-sigma analog-to-digital modulator structure is disclosed, in which a feedforward-feedback connection is adopted among a plurality of integrators to improve the stability of the system, but an adder, a gain stage amplifier and a quantizer are required to be matched to generate an output signal, so that the complicated circuit structure increases the circuit area and power consumption.
When the n-order sigma-delta modulator is adopted, only n/2 (when n is an even number) or (n +1)/2 (when n is an odd number) integrators are needed to be used, and an operation method combined with the integrators is matched, and each integrator performs two-time integral operation, so that the function of the n-order sigma-delta modulator can be realized, and the area and the power consumption of an electronic system are reduced. The disadvantage is that when the sigma-delta modulator is applied to more than three-order delta-sigma modulators, n/2 or (n +1)/2 integrators are connected in series, the direct connection of the integrators easily causes instability of a circuit system, and in addition, the number of integration operations increases along with the number of the integrators, so that n or (n +1) integration operations are required in total, and the operation speed of the system is reduced. Taking a 3-order delta-sigma modulator as an example, the structure needs 2 integrators, and needs 4 integrations in total, compared with a 2-order delta-sigma modulator which only needs 2 integrations, when applied to an analog-digital converter, the conversion speed of the 3-order delta-sigma modulator is only half of that of the 2-order delta-sigma modulator.
In view of the above-mentioned problems of the conventional technologies, it is desirable to provide a modulator with high stability, which does not require an active circuit and only requires one comparator to achieve a multi-bit quantization function.
Disclosure of Invention
In view of the above, it is desirable to provide a feed-forward delta-sigma analog-to-digital converter with high stability, without requiring an active circuit, and with only one comparator, which can achieve multi-bit quantization function, in order to solve the problems of instability and large power consumption of the conventional modulator.
In order to solve the above problem, the present invention provides a feedforward delta-sigma analog-to-digital modulator, comprising:
an input end capacitance switching circuit which receives an input timing control signal, an input voltage and a capacitance switching signal and generates an integral input signal;
a feed-forward integrator receiving the integration input signal, the continuous progressive control signal, and the input timing control signal and generating an integration output signal;
a multi-bit quantizer receiving the integrated output signal and a quantization reference control signal and generating a modulated output signal;
a continuous progressive control circuit receiving the modulation output signal and generating the quantization reference control signal, the continuous progressive control signal and a data weighted average signal; and
and the data weighted average circuit receives the prime number data weighted average signal and generates the capacitance switching signal.
In one embodiment, the feed-forward integrator includes a plurality of integration circuits for processing integration operations, and the plurality of integration circuits are connected in a manner including:
the plurality of integrating circuits are connected in series to form a plurality of stages, the first-stage integrating circuit receives the integrating input signal, a series output signal is generated through integration operation and is connected to the input end of the second-stage integrating circuit, and then the output signal of the previous-stage integrating circuit is connected to the input end of the next-stage integrating circuit; and
each stage of the integrating circuit generates another output signal, respectively, which are interconnected into the integrated output signal.
In one embodiment, the first stage of integrating circuit and the intermediate stage of integrating circuit comprise:
a first set of switch circuits having inputs coupled to the integrated input signal and outputs coupled to one input of the amplifier;
one input end of the amplifier is connected to the output end of the first group of switch circuits, the other input end of the amplifier is grounded, and the output end of the amplifier is simultaneously coupled to the input ends of the second group of switch circuits and the third group of switch circuits;
the input ends of the second group of switch circuits are coupled to the output end of the amplifier, and the output ends of the second group of switch circuits are coupled to the second capacitor;
the input end of the third group of switch circuits is coupled to the output end of the amplifier, and the output end of the third group of switch circuits is coupled to a third capacitor;
a first capacitor coupled between the output terminals of the first set of switching circuits and the input terminal of the amplifier;
the second capacitor is coupled between the output ends of the second group of switch circuits and the integral output signal; and
the third capacitor is coupled between the output ends of the third group of switch circuits and the output signals in series.
In one embodiment, the last stage integrating circuit comprises:
a first set of switch circuits having inputs coupled to the integrated input signal and outputs coupled to one input of the amplifier;
the input end of the amplifier is connected to the output end of the first group of switch circuits, the other input end of the amplifier is grounded, and the output end of the amplifier is coupled to the input end of the second group of switch circuits;
the input ends of the second group of switch circuits are coupled to the output end of the amplifier, and the output ends of the second group of switch circuits are coupled to the second capacitor;
a first capacitor coupled between the output terminals of the first set of switching circuits and the input terminal of the amplifier;
the second capacitor is coupled between the output ends of the second group of switch circuits and the integration output signal.
In one embodiment, the first stage of integrating circuit and the intermediate stage of integrating circuit comprise:
a first group of switch circuits having input terminals coupled to the integrated input signal
A differential amplifier having a positive input coupled to the output of the first set of switching circuits;
a second set of switching circuits having inputs coupled to the negative outputs of the differential amplifier;
a third set of switching circuits having inputs coupled to the negative outputs of the differential amplifier;
a first capacitor coupled between the positive input terminal and the negative output terminal of the differential amplifier;
a second capacitor coupled between the output ends of the second set of switch circuits and the integrated output signal;
a third capacitor coupled between the output end of the third group of switch circuits and the output signal in series;
a negative side first set of switch circuits having inputs coupled to negative side input signals;
a negative side second set of switching circuits having inputs coupled to the positive outputs of the differential amplifier;
a negative side third set of switch circuits having inputs coupled to the positive outputs of the differential amplifier;
a negative terminal first capacitor coupled between the negative input terminal and the positive output terminal of the differential amplifier;
a negative side second capacitor coupled between the output of the negative side second set of switch circuits and the negative integral output signal; and
and the negative end third capacitor is coupled between the output end of the negative end third group of switch circuits and the negative serial output signal.
In one embodiment, the last stage of integrating circuit and the intermediate stages of integrating circuits include:
a first set of switch circuits, the input ends of which are coupled with the integration input signal;
a differential amplifier having a positive input coupled to the output of the first set of switching circuits;
a second set of switching circuits having inputs coupled to the negative outputs of the differential amplifier;
a first capacitor coupled between the positive input terminal and the negative output terminal of the differential amplifier;
a second capacitor coupled between the output ends of the second set of switch circuits and the integrated output signal;
a negative side first set of switch circuits having inputs coupled to negative side input signals;
a negative side second set of switching circuits having inputs coupled to the positive outputs of the differential amplifier;
a negative terminal first capacitor coupled between the negative input terminal and the positive output terminal of the differential amplifier; and
and the negative end second capacitor is coupled between the output end of the negative end second group of switch circuits and the negative integral output signal.
In one embodiment, the first set of switching circuits comprises:
the first switch is coupled between the input end and the output end, and the switch state is controlled by a first switch control signal; and
the second switch is coupled between the input end and the grounding end, and the switch state is controlled by a second switch control signal;
the second set of switching circuits comprises:
the first switch is coupled between the input end and the output end, and the switch state is controlled by a first switch control signal; and
the second switch is coupled between the output end and the grounding end, and the switch state is controlled by a second switch control signal.
In one embodiment, the control method of the switching circuit includes:
a first operation time sequence which generates a first time sequence signal, wherein the left contact of each first group of switch circuits is not conducted, the left contact is grounded, the right contact is in a suspension state, the left contact of each second group of switch circuits is conducted, the left contact of each third group of switch circuits is not conducted, and the first operation time sequence conducts charging sampling action on the second capacitor of each stage of integration circuit;
the continuous progressive control time sequence generates a continuous progressive control signal, sequentially conducts the third group of switch circuits of each stage of integration circuit, controls the charging electric quantity of the third capacitor of each stage of integration circuit, and does not conduct the left and right ends of each second group of switch circuits and the third group of switch circuits; and
and in the second time sequence, the left and right end contacts of each first group of switch circuits are conducted, the left end contact of each second group of switch circuits is not conducted, the right end contact of each second group of switch circuits is in a suspension state, and the left end contact of each third group of switch circuits is grounded.
In one embodiment, the capacitance of the second capacitor or the negative-side second capacitor in each stage of the integrating circuit can be adjusted, and the magnitude of the integrated output signal is adjusted accordingly.
In one embodiment, the input end capacitance switching circuit comprises a plurality of capacitance switching units connected in parallel with each other, the capacitance switching units receiving a positive reference voltage, a negative reference voltage, an input voltage, a timing signal and a switching signal and generating an output signal;
wherein the capacitance switching unit includes:
a first changeover switch having one end connected to the positive reference voltage;
a second switch connected between a negative reference voltage and the first switch;
a third switch, one end of which is connected to the first switch and the second switch, and the other end of which is grounded;
a fourth changeover switch having one end connected to the input voltage;
one end of the fifth change-over switch is connected with the fourth change-over switch, and the other end of the fifth change-over switch is grounded;
one end of the first switching capacitor is connected with the first switching switch, the second switching switch and the third switching switch, and the other end of the first switching capacitor is connected to an output end; and
and one end of the second switching capacitor is connected with the fourth switching switch and the fifth switching switch, and the other end of the second switching capacitor is connected to an output end.
In one embodiment, the method for controlling the switch includes:
the first operation time sequence is used for generating a first time sequence signal, directly conducting the fourth change-over switch, and simultaneously conducting the first change-over switch and the second change-over switch of each capacitance change-over unit according to a thermometer code in sequence, wherein the third change-over switch and the fifth change-over switch can not be conducted; and
and the second operation time sequence generates a second time sequence signal to directly conduct the third change-over switch and the fifth change-over switch, and at the moment, the first change-over switch, the second change-over switch and the fourth change-over switch can not be conducted.
In one embodiment, the multi-bit quantizer comprises a comparator, and the quantization reference control signal is generated by using a continuous gradual control circuit, so as to adjust the comparison level of the comparator, and enable the comparator to generate the multi-bit modulation output signal.
The beneficial effects of the invention include:
the feedback delta-sigma ADC is integrated with a feedback circuit, an adder circuit and a quantization circuit. The integrated circuit structure has the advantage of high stability, does not need an active circuit, and adopts a control circuit of a continuous approximation method, so that the multi-bit quantization function can be realized by only one comparator.
Drawings
FIG. 1 is a schematic diagram of a feedforward DAC modulator according to one embodiment;
FIG. 2 is a schematic diagram of a feedforward integrator in one embodiment;
FIG. 3 is a schematic diagram of a single stage integration circuit of the feedforward integrator in one embodiment;
FIG. 4 is a circuit diagram of a feedforward integrator in one embodiment;
FIG. 5 is a schematic diagram of a single stage integrating differential circuit of the feedforward integrator in one embodiment;
FIG. 6 is a schematic diagram of an embodiment of an input end capacitance switching circuit;
FIG. 7 is a schematic diagram of an input capacitance switching unit according to an embodiment;
FIG. 8 is a circuit diagram of the differential circuit of the feedforward integrator and the multi-bit quantizer in one embodiment;
FIG. 9 is a schematic diagram of a first set of switching circuits in each stage of the integrating circuits of the feedforward integrator in one embodiment;
fig. 10 is a schematic structural diagram of a second group of switching circuits in each stage of the integrating circuits of the feedforward integrator in one embodiment.
Detailed Description
The present invention will be more specifically described with reference to the following examples. Please note that the following description of the embodiments of the present invention is for illustrative purposes only; it is not intended to be exhaustive or to limit the invention to the precise form disclosed.
First, please refer to fig. 1 with reference to fig. 8, which shows a structure of a third-order feedforward delta-sigma analog-to-digital converter 1. The feedforward delta-sigma ADC modulator 1 includes an input capacitance switching circuit 10, a feedforward integrator 20, a multi-bit quantizer 30, a continuous gradual control circuit 40, and a data weighted average circuit 50. The input terminal capacitance switching circuit 10 receives an input timing control signal s125, an input voltage s123, and a capacitance switching signal s52, and generates an integrated input signal s 261. The feedforward integrator 20 receives an integration input signal s261, a continuous progression control signal s263, and an input timing control signal s125, and generates an integration output signal s 264. The multi-bit quantizer 30 receives the integrated output signal s264 and the quantization reference control signal s31 and generates a modulated output signal s 32. The continuous and gradual control circuit 40 receives the modulated output signal s32, and generates a quantized reference control signal s31, a continuous and gradual control signal s263 and a data weighted average signal s 51. The data weighted averaging circuit 50 receives the data weighted averaging signal s51 and generates the capacitance switching signal s 52.
Next, please refer to fig. 2, which shows an architecture structure of the feedforward integrator 20. The feedforward integrator 20 is formed by connecting a plurality of integration circuits that process integration operations in series, and the output of each stage of integration circuit is controlled by a control signal. For the present embodiment, the feedforward integrator 20 includes a first stage integrator 21, a second stage integrator 22, and a third stage integrator 23. The first stage integration circuit 21 receives an integration input signal s261 and an integration timing control signal s262, and generates two output signals through integration operation, which are respectively connected to the next stage integration circuit and the final output point. The middle stage of integrating circuit receives the output signal and the control signal of the previous stage, generates two output signals through integration operation, and is respectively connected to the next stage of integrating circuit and the final output point. The last stage of integrating circuit receives the output signal and the control signal of the previous stage, generates an output signal through integrating operation and is directly connected to the last output point.
Referring again to fig. 3, a single-stage integrator circuit structure of the feedforward integrator 20 is shown. Taking the first stage integration circuit 21 in the feedforward integrator 20 as an example, the first stage integration circuit 21 includes an amplifier 247, three capacitors (a first capacitor 244, a second capacitor 245, and a third capacitor 246), and three sets of switch circuits (a first set of switch circuits 241, a second set of switch circuits 242, and a third set of switch circuits 243). The first set of switching circuits 241 has inputs coupled to the integrated input signal s261 and outputs coupled to one of the inputs of the amplifier 247. The amplifier 247 has another input terminal connected to ground and an output terminal coupled to the input terminals of the second set of switching circuits 242 and the third set of switching circuits 243. The first capacitor 244 is coupled between the output of the first set of switching circuits 241 and the input of the amplifier 247. The second capacitor 245 is coupled between the output terminals of the second set of switch circuits 242 and the integrated output signal s 264. The third capacitor 246 is coupled between the output terminal of the third set of switch circuits 243 and the serial output signal s 265. The structure of the integrating circuits of the intermediate stages is the same as that of the integrating circuit 21 of the first stage, with the difference that the input of the integrating circuit 21 of the first stage receives the integrating input signal s261, while the input of the integrating circuits of the intermediate stages receives the tandem output signal s265 of the previous stage.
Next, referring to fig. 3 and fig. 4, a circuit diagram of the feedforward integrator 20 in an embodiment is shown, in which the last stage integrating circuit 23 of the feedforward integrator 20 includes an amplifier 247, two capacitors and two sets of switch circuits. The first set of switch circuits 241 has inputs coupled to the integration input signal s261 and the integration timing control signal s262, and outputs coupled to the input of the amplifier 247. The amplifier 247 has another input coupled to ground and an output coupled to inputs of the second set of switching circuits 242. The first capacitor 244 is coupled between the output of the first set of switching circuits 241 and the input of the amplifier 247. The second capacitor 245 is coupled between the output terminals of the second set of switch circuits 242 and the integrated output signal s 264.
Referring to fig. 5, a single-stage integrating differential circuit structure of the feedforward integrator 20 in one embodiment is shown. In accordance with the present invention, the first stage integration circuit 21 of the feedforward integrator 20 can also be realized by a differential structure, which has the effect of increasing the signal-to-noise ratio (SNR), and the structure includes a differential amplifier 257, six capacitors (a first capacitor 244, a second capacitor 245, a third capacitor 246, a negative side first capacitor 254, a negative side second capacitor 255, and a negative side third capacitor 256), and six sets of switch circuits (a first set of switch circuits 241, a second set of switch circuits 242, a third set of switch circuits 243, a negative side first set of switch circuits 251, a negative side second set of switch circuits 252, and a negative side third set of switch circuits 253). The input terminals of the first set of switch circuits 241 are coupled to the integration input signal s261 and the integration timing control signal s262, and the output terminals thereof are coupled to the positive input terminal of the differential amplifier 257. The negative output terminal of the differential amplifier 257 is coupled to the input terminals of the second and third sets of switch circuits 242 and 243. The first capacitor 244 is coupled between the output terminals of the first set of switch circuits 241 and the positive input terminal of the differential amplifier 257. The second capacitor 245 is coupled between the output terminals of the second set of switch circuits 242 and the integrated output signal s 264. The third capacitor 246 is coupled between the output terminal of the third set of switch circuits 243 and the serial output signal s 265. The negative side first set of switch circuits 251 has an input coupled to a negative side input signal and an output coupled to a negative input of the differential amplifier 257. The positive output of the differential amplifier 257 is coupled to the inputs of the negative side second set of switch circuits 252 and the negative side third set of switch circuits 253. The negative side first capacitor 254 is coupled between the output of the negative side first set of switch circuits 251 and the negative input of the differential amplifier 257. The negative side second capacitor 255 is coupled between the output of the negative side second set of switch circuits 252 and the negative side integrated output signal s 264. The negative side third capacitor 256 is coupled between the output of the negative side third set of switch circuits 253 and a negative side series output signal s 265. The structure of the intermediate stage of the integrating circuit is the same as that of the first stage of the integrating circuit 21, and the difference is that the input end of the first stage of the integrating circuit 21 receives the input signal and the negative input signal, and the input end of the intermediate stage of the integrating circuit receives the positive side serial output signal s265 and the negative side serial output signal s265 of the previous stage.
In one embodiment, the last stage of the integrator 23 of the feedforward integrator 20 may also be implemented by a differential structure, which includes a differential amplifier 257, four capacitors (a first capacitor 244, a second capacitor 245, a negative side first capacitor 254, a negative side second capacitor 255) and four sets of switch circuits (a first set of switch circuits 241, a second set of switch circuits 242, a negative side first set of switch circuits 251, and a negative side second set of switch circuits 252). The first set of switch circuits 241 has inputs coupled to the input signal and outputs coupled to the positive input of the differential amplifier 257. The negative output terminal of the differential amplifier 257 is coupled to the input terminals of the second set of switching circuits 242. The first capacitor 244 is coupled between the output terminals of the first set of switch circuits 241 and the positive input terminal of the differential amplifier 257. The second capacitor 245 is coupled between the output terminals of the second set of switch circuits 242 and the integrated output signal s 264. The negative side first set of switch circuits 251 has an input coupled to a negative side input signal and an output coupled to a negative input of the differential amplifier 257. The positive output terminal of the differential amplifier 257 is coupled to the input terminal of the negative terminal second set of switching circuits 252. The negative side first capacitor 254 is coupled between the output of the negative side first set of switch circuits 251 and the negative input of the differential amplifier 257. The negative side second capacitor 255 is coupled between the output of the negative side second set of switch circuits 252 and the negative side integrated output signal s 264.
Next, referring to fig. 9 and fig. 10, structures of a first set of switch circuits 241 and a second set of switch circuits 242 in each stage of the integration circuit in one embodiment are shown. As shown, the first group of switch circuits 241 includes two switches (a first switch 248 and a second switch 249), the first switch 248 is coupled between the input end and the output end, and the switch state is controlled by the control signal of the first switch 248. The second switch 249 is coupled between the input terminal and the ground terminal, and the switch state is controlled by a control signal of the second switch 249. The second set of switch circuits 242 also includes two switches (a first switch 248 and a second switch 249), the first switch 248 is coupled between the input terminal and the output terminal, and the switch states are controlled by the control signal of the first switch 248. The second switch 249 is coupled between the output terminal and the ground terminal, and the switch state is controlled by a control signal of the second switch 249.
In one embodiment, the capacitance of the second capacitor 245 or the negative side second capacitor 255 of each stage of the integration circuit of the feedforward integrator 20 can be adjusted, and the magnitude of the integrated output signal 264 can be adjusted accordingly.
In one embodiment, the control method of the switching circuit of the feedforward integrator 20 is divided into three operation timings. The first timing signal is generated at the first operation timing, and at this time, the left contact of each first group of switch circuits 241 is not turned on, the right contact is grounded, the left contact is in a floating state, the left contact of each second group of switch circuits 242 is turned on, and the left contact of each third group of switch circuits 243 is not turned on. This sequence performs a charge sampling operation on the second capacitor 245 of each stage of the integration circuit. Then, a continuous progressive control sequence is entered, at this time, a continuous progressive control signal s263 is generated, the third set of switch circuits 243 of each stage of integration circuit is sequentially turned on, the charging amount of the third capacitor 246 of each stage of integration circuit is controlled, and at this time, the left and right end contacts of each of the second set of switch circuits 242 and the third set of switch circuits 243 are not turned on. And finally, entering a second time sequence, wherein the left and right end contacts of each first group of switch circuits 241 are conducted, the left end contact of each second group of switch circuits 242 is not conducted, the right end contact is grounded, and the left and right end contacts of each third group of switch circuits 243 are not conducted. Because the integrating circuit has the characteristic that the capacitors for the feedforward and feedback paths are directly connected, the time sequence operation is utilized to control the charging and discharging of the capacitors so as to complete the trigonometric integral operation, and the circuit of the adder is saved at the output end.
Referring to fig. 6, a structure of the input end capacitance switching circuit 10 in one embodiment is shown. In one embodiment, the input capacitance switching circuit 10 of the feedforward delta-sigma analog-to-digital converter 1 includes a plurality of input capacitance switching units 101 connected in parallel, and the input capacitance switching units 101 receive the positive reference voltage s121, the negative reference voltage s122, the input voltage s123, the timing signal and the switching signal and generate the output signal.
Referring to fig. 7, the structure of the input capacitance switching unit 101 is shown. In one embodiment, the input capacitance switching unit 101 includes five switches (a first switch 111, a second switch 112, a third switch 113, a fourth switch 114, a fifth switch 115) and two capacitances (a first switch capacitance 116, a second switch capacitance 117). The first switch 111 has one end connected to the positive reference voltage s121 and the other end connected to the second switch 112, the third switch 113, and the first switching capacitor 116. The other end of the second changeover switch 112 is connected to the negative reference voltage s122, the other end of the third changeover switch 113 is grounded, the other end of the first changeover capacitor 116 is connected to the second changeover capacitor 117, and the other end of the second changeover capacitor 117 is connected to the fourth changeover switch 114 and the fifth changeover switch 115. The other end of the fourth switch 114 is connected to the input voltage s123, and the other end of the fifth switch 115 is grounded.
The control method of these switches is divided into two operation timings, in which a first timing signal is generated at the first operation timing to directly turn on the fourth switch 114, and simultaneously turn on the first switch 111 and the second switch 112 of each input capacitance switching unit 101 in sequence according to a thermometer code signal s124, at which time the third switch 113 and the fifth switch 115 are not turned on. The second timing signal is generated at the second operation timing to directly turn on the third switch 113 and the fifth switch 115, and at this time, the first switch 111, the second switch 112 and the fourth switch 114 are not turned on. The effect is to switch the capacitors in the capacitor switching units in sequence according to the output signal of the data weighted averaging circuit 50 to generate the input signal of the feedforward integrator 20, thereby reducing the noise caused by the mismatch of the capacitance values.
Finally, referring to fig. 8, a circuit diagram of the differential circuit of the feedforward integrator 20 and the multi-bit quantizer 30 in one embodiment is shown. In one embodiment, the multi-bit quantizer 30 may be implemented by a comparator, and the continuous gradual control circuit 40 is used to generate the quantization reference control signal s31, so as to adjust the comparison level of the comparator, such that the comparator generates the multi-bit modulated output signal s 32.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Description of the symbols:
1 feedforward type trigonometric integral analog-to-digital converter; 10 input end capacitance switching circuit; 20 a feedforward integrator; 21 a first stage integrating circuit; 22 a second stage integrating circuit; 23 a third pole integrating circuit; a 30-bit quantizer; 40 a continuous progressive control circuit; 50 a data weighted averaging circuit; 101 an input capacitance switching unit; 111 a first changeover switch; 112 a second switch; 113 a third changeover switch; 114 a fourth changeover switch; 115 a fifth changeover switch; 116 a first switched capacitance; 117 a second switching capacitance; 121 a positive reference voltage; 122 a negative reference voltage; 123 input voltage; 241 a first set of switching circuits; 242 a second set of switching circuits; 243 third set of switching circuits; 244 a first capacitance; 245 a second capacitance; 246 a third capacitance; 247 an amplifier; 248 a first switch; 249 a second switch; 251 negative terminal first group of switch circuits; 252 negative terminal second set of switching circuits; 253 negative terminal third set of switching circuits; 254 negative terminal first capacitance; 255 negative terminal second capacitance; 256 negative side third capacitors; 257 a differential amplifier;
s31 quantizing the reference control signal; s32 modulating the output signal; s51 data weighted average signal; s52 capacitance switching signal; s124, thermometer code signal; s125 inputting a timing control signal; s261 integrates the input signal; s262 integrating the timing control signal; s263 continuous progressive control signal; s264 integrates the output signal; s265 concatenates the output signals.
Claims (10)
1. A feed-forward delta-sigma analog-to-digital modulator, comprising:
an input end capacitance switching circuit which receives an input timing control signal, an input voltage and a capacitance switching signal and generates an integral input signal;
a feed-forward integrator receiving the integration input signal, the continuous progressive control signal, and the input timing control signal and generating an integration output signal;
a multi-bit quantizer receiving the integrated output signal and a quantization reference control signal and generating a modulated output signal;
a continuous progressive control circuit receiving the modulation output signal and generating the quantization reference control signal, the continuous progressive control signal and a data weighted average signal; and
a data weighted average circuit receiving the data weighted average signal and generating the capacitance switching signal,
wherein the feedforward integrator comprises a plurality of integrating circuits for processing integration operation, and the connection mode of the plurality of integrating circuits comprises:
the plurality of integrating circuits are connected in series to form a plurality of stages, the first-stage integrating circuit receives the integrating input signal, a series output signal is generated through integration operation and is connected to the input end of the second-stage integrating circuit, and then the output signal of the previous-stage integrating circuit is connected to the input end of the next-stage integrating circuit; and
each stage of integrating circuit generates another output signal, the output signals are mutually connected to become the integration output signal,
wherein the first stage of integrating circuit and the intermediate stage of integrating circuit comprise:
a first set of switch circuits having inputs coupled to the integrated input signal and outputs coupled to one input of the amplifier;
one input end of the amplifier is connected to the output end of the first group of switch circuits, the other input end of the amplifier is grounded, and the output end of the amplifier is simultaneously coupled to the input ends of the second group of switch circuits and the third group of switch circuits;
the input ends of the second group of switch circuits are coupled to the output end of the amplifier, and the output ends of the second group of switch circuits are coupled to the second capacitor;
the input end of the third group of switch circuits is coupled to the output end of the amplifier, and the output end of the third group of switch circuits is coupled to a third capacitor;
a first capacitor coupled between the output terminals of the first set of switching circuits and the input terminal of the amplifier;
the second capacitor is coupled between the output ends of the second group of switch circuits and the integral output signal; and
the third capacitor is coupled between the output ends of the third group of switch circuits and the output signals in series.
2. A feed-forward delta-sigma analog-to-digital modulator, comprising:
an input end capacitance switching circuit which receives an input timing control signal, an input voltage and a capacitance switching signal and generates an integral input signal;
a feed-forward integrator receiving the integration input signal, the continuous progressive control signal, and the input timing control signal and generating an integration output signal;
a multi-bit quantizer receiving the integrated output signal and a quantization reference control signal and generating a modulated output signal;
a continuous progressive control circuit receiving the modulation output signal and generating the quantization reference control signal, the continuous progressive control signal and a data weighted average signal; and
a data weighted average circuit receiving the data weighted average signal and generating the capacitance switching signal,
wherein the feedforward integrator comprises a plurality of integrating circuits for processing integration operation, and the connection mode of the plurality of integrating circuits comprises:
the plurality of integrating circuits are connected in series to form a plurality of stages, the first-stage integrating circuit receives the integrating input signal, a series output signal is generated through integration operation and is connected to the input end of the second-stage integrating circuit, and then the output signal of the previous-stage integrating circuit is connected to the input end of the next-stage integrating circuit; and
each stage of integrating circuit generates another output signal, the output signals are mutually connected to become the integration output signal,
wherein a last stage integrating circuit of the plurality of integrating circuits comprises:
a first set of switch circuits having inputs coupled to the integrated input signal and outputs coupled to one input of the amplifier;
one input end of the amplifier is connected to the output ends of the first group of switch circuits, the other input end of the amplifier is grounded, and the output ends of the amplifier are coupled to the input ends of the second group of switch circuits;
the input ends of the second group of switch circuits are coupled to the output end of the amplifier, and the output ends of the second group of switch circuits are coupled to the second capacitor;
a first capacitor coupled between the output terminals of the first set of switching circuits and the input terminal of the amplifier; and
the second capacitor is coupled between the output ends of the second group of switch circuits and the integration output signal.
3. A feed-forward delta-sigma analog-to-digital modulator, comprising:
an input end capacitance switching circuit which receives an input timing control signal, an input voltage and a capacitance switching signal and generates an integral input signal;
a feed-forward integrator receiving the integration input signal, the continuous progressive control signal, and the input timing control signal and generating an integration output signal;
a multi-bit quantizer receiving the integrated output signal and a quantization reference control signal and generating a modulated output signal;
a continuous progressive control circuit receiving the modulation output signal and generating the quantization reference control signal, the continuous progressive control signal and a data weighted average signal; and
a data weighted average circuit receiving the data weighted average signal and generating the capacitance switching signal,
wherein the feedforward integrator comprises a plurality of integrating circuits for processing integration operation, and the connection mode of the plurality of integrating circuits comprises:
the plurality of integrating circuits are connected in series to form a plurality of stages, the first-stage integrating circuit receives the integrating input signal, a series output signal is generated through integration operation and is connected to the input end of the second-stage integrating circuit, and then the output signal of the previous-stage integrating circuit is connected to the input end of the next-stage integrating circuit; and
each stage of integrating circuit generates another output signal, the output signals are mutually connected to become the integration output signal,
wherein the first stage of integrating circuit and the intermediate stage of integrating circuit comprise:
a first set of switch circuits, the input ends of which are coupled with the integration input signal;
a differential amplifier having a positive input coupled to the output of the first set of switching circuits;
a second set of switching circuits having inputs coupled to the negative outputs of the differential amplifier;
a third set of switching circuits having inputs coupled to the negative outputs of the differential amplifier;
a first capacitor coupled between the positive input terminal and the negative output terminal of the differential amplifier;
a second capacitor coupled between the output ends of the second set of switch circuits and the integrated output signal;
a third capacitor coupled between the output end of the third group of switch circuits and the output signal in series;
a negative side first set of switch circuits having inputs coupled to negative side input signals;
a negative side second set of switching circuits having inputs coupled to the positive outputs of the differential amplifier;
a negative side third set of switch circuits having inputs coupled to the positive outputs of the differential amplifier;
a negative terminal first capacitor coupled between the negative input terminal and the positive output terminal of the differential amplifier;
a negative side second capacitor coupled between the output of the negative side second set of switch circuits and the negative integral output signal; and
a negative terminal third capacitor coupled between the output terminal of the negative terminal third set of switch circuits and the negative series output signal,
wherein the first set of switching circuits comprises:
the first switch is coupled between the input end and the output end, and the switch state is controlled by a first switch control signal; and
the second switch is coupled between the input end and the grounding end, and the switch state is controlled by a second switch control signal;
the second set of switching circuits comprises:
the first switch is coupled between the input end and the output end, and the switch state is controlled by a first switch control signal; and
the second switch is coupled between the output end and the grounding end, and the switch state is controlled by a second switch control signal.
4. A feed-forward delta-sigma analog-to-digital modulator, comprising:
an input end capacitance switching circuit which receives an input timing control signal, an input voltage and a capacitance switching signal and generates an integral input signal;
a feed-forward integrator receiving the integration input signal, the continuous progressive control signal, and the input timing control signal and generating an integration output signal;
a multi-bit quantizer receiving the integrated output signal and a quantization reference control signal and generating a modulated output signal;
a continuous progressive control circuit receiving the modulation output signal and generating the quantization reference control signal, the continuous progressive control signal and a data weighted average signal; and
a data weighted average circuit receiving the data weighted average signal and generating the capacitance switching signal,
wherein the feedforward integrator comprises a plurality of integrating circuits for processing integration operation, and the connection mode of the plurality of integrating circuits comprises:
the plurality of integrating circuits are connected in series to form a plurality of stages, the first-stage integrating circuit receives the integrating input signal, a series output signal is generated through integration operation and is connected to the input end of the second-stage integrating circuit, and then the output signal of the previous-stage integrating circuit is connected to the input end of the next-stage integrating circuit; and
each stage of integrating circuit generates another output signal, the output signals are mutually connected to become the integration output signal,
wherein the last stage of the integrating circuits and the intermediate stages of the integrating circuits comprise:
a first set of switch circuits, the input ends of which are coupled with the integration input signal;
a differential amplifier having a positive input coupled to the output of the first set of switching circuits;
a second set of switching circuits having inputs coupled to the negative outputs of the differential amplifier;
a first capacitor coupled between the positive input terminal and the negative output terminal of the differential amplifier;
a second capacitor coupled between the output ends of the second set of switch circuits and the integrated output signal;
a negative side first set of switch circuits having inputs coupled to negative side input signals;
a negative side second set of switching circuits having inputs coupled to the positive outputs of the differential amplifier;
a negative terminal first capacitor coupled between the negative input terminal and the positive output terminal of the differential amplifier; and
a negative side second capacitor coupled between the output of the negative side second set of switch circuits and the negative integration output signal,
wherein the first set of switching circuits comprises:
the first switch is coupled between the input end and the output end, and the switch state is controlled by a first switch control signal; and
the second switch is coupled between the input end and the grounding end, and the switch state is controlled by a second switch control signal;
the second set of switching circuits comprises:
the first switch is coupled between the input end and the output end, and the switch state is controlled by a first switch control signal; and
the second switch is coupled between the output end and the grounding end, and the switch state is controlled by a second switch control signal.
5. A feed-forward delta-sigma analog-to-digital converter as set forth in any of claims 1-2, wherein said first set of switching circuits comprises:
the first switch is coupled between the input end and the output end, and the switch state is controlled by a first switch control signal; and
the second switch is coupled between the input end and the grounding end, and the switch state is controlled by a second switch control signal;
the second set of switching circuits comprises:
the first switch is coupled between the input end and the output end, and the switch state is controlled by a first switch control signal; and
the second switch is coupled between the output end and the grounding end, and the switch state is controlled by a second switch control signal.
6. A feedforward-type sigma-delta analog-to-digital converter according to any one of claims 1 to 4, wherein the control method of the switching circuit includes:
a first operation time sequence which generates a first time sequence signal, wherein the left contact of each first group of switch circuits is not conducted, the left contact is grounded, the right contact is in a suspension state, the left contact of each second group of switch circuits is conducted, the left contact of each third group of switch circuits is not conducted, and the first operation time sequence conducts charging sampling action on the second capacitor of each stage of integration circuit;
the continuous progressive control time sequence generates a continuous progressive control signal, sequentially conducts the third group of switch circuits of each stage of integration circuit, controls the charging electric quantity of the third capacitor of each stage of integration circuit, and does not conduct the left and right ends of each second group of switch circuits and the third group of switch circuits; and
and in the second time sequence, the left and right end contacts of each first group of switch circuits are conducted, the left end contact of each second group of switch circuits is not conducted, the right end contact of each second group of switch circuits is in a suspension state, and the left end contact of each third group of switch circuits is grounded.
7. A feedforward delta-sigma analog-to-digital converter as claimed in any one of claims 1 to 4, wherein the capacitance of the second capacitor or the negative side second capacitor in each stage of the integrator circuit is adjustable to adjust the magnitude of the integrated output signal accordingly.
8. A feed-forward delta-sigma analog-to-digital converter as set forth in claim 1, wherein said input capacitance switching circuit comprises a plurality of capacitance switching units connected in parallel with each other, said capacitance switching units receiving a positive reference voltage, a negative reference voltage, an input voltage, a timing signal and a switching signal and generating an output signal;
wherein the capacitance switching unit includes:
a first changeover switch having one end connected to the positive reference voltage;
a second switch connected between the negative reference voltage and the first switch;
a third switch, one end of which is connected to the first switch and the second switch, and the other end of which is grounded;
a fourth changeover switch having one end connected to the input voltage;
one end of the fifth change-over switch is connected with the fourth change-over switch, and the other end of the fifth change-over switch is grounded;
a first switching capacitor, one end of which is connected to the first switch, the second switch and the third switch, and the other end of which is connected to an output terminal; and
and one end of the second switching capacitor is connected with the fourth switching switch and the fifth switching switch, and the other end of the second switching capacitor is connected to an output end.
9. A feed forward delta-sigma analog to digital converter as set forth in claim 8, wherein said switch control method comprises:
the first operation time sequence is used for generating a first time sequence signal, directly conducting the fourth change-over switch, and simultaneously conducting the first change-over switch and the second change-over switch of each capacitance change-over unit according to a thermometer code in sequence, wherein the third change-over switch and the fifth change-over switch can not be conducted; and
and the second operation time sequence generates a second time sequence signal to directly conduct the third change-over switch and the fifth change-over switch, and at the moment, the first change-over switch, the second change-over switch and the fourth change-over switch can not be conducted.
10. A feed forward sigma delta analog to digital converter as set forth in any of claims 1 to 4, wherein said multi-bit quantizer comprises a comparator and a continuous gradual control circuit is used to generate a quantization reference control signal, whereby the comparison level of said comparator is adjusted such that said comparator generates a multi-bit modulated output signal.
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| CN102244517A (en) * | 2010-05-11 | 2011-11-16 | 迅宏科技股份有限公司 | Shared exchange capacitance type integrator and operation method thereof as well as sigma-delta modulator |
| CN102422539A (en) * | 2009-05-12 | 2012-04-18 | 高通股份有限公司 | Sigma-delta converters and methods for analog-to-digital conversion |
| CN102638268A (en) * | 2012-04-19 | 2012-08-15 | 北京工业大学 | Third-order feedforward Sigma-Delta modulator based on successive comparison quantizer |
| CN104682957A (en) * | 2013-11-29 | 2015-06-03 | 展讯通信（上海）有限公司 | Sigma-delta analog-to-digital converter |
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| JP4789878B2 (en) * | 2007-06-21 | 2011-10-12 | オンセミコンダクター・トレーディング・リミテッド | Delta-sigma modulator and delta-sigma AD converter |
| JP6468188B2 (en) * | 2013-07-11 | 2019-02-13 | 株式会社ソシオネクスト | Current-type D / A converter, delta-sigma modulator, and communication apparatus |
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| CN102422539A (en) * | 2009-05-12 | 2012-04-18 | 高通股份有限公司 | Sigma-delta converters and methods for analog-to-digital conversion |
| CN102244517A (en) * | 2010-05-11 | 2011-11-16 | 迅宏科技股份有限公司 | Shared exchange capacitance type integrator and operation method thereof as well as sigma-delta modulator |
| CN102638268A (en) * | 2012-04-19 | 2012-08-15 | 北京工业大学 | Third-order feedforward Sigma-Delta modulator based on successive comparison quantizer |
| CN104682957A (en) * | 2013-11-29 | 2015-06-03 | 展讯通信（上海）有限公司 | Sigma-delta analog-to-digital converter |
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