CN107579056A - Array base-plate structure and display device - Google Patents
Array base-plate structure and display device Download PDFInfo
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- CN107579056A CN107579056A CN201610525395.6A CN201610525395A CN107579056A CN 107579056 A CN107579056 A CN 107579056A CN 201610525395 A CN201610525395 A CN 201610525395A CN 107579056 A CN107579056 A CN 107579056A
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Abstract
The present invention discloses a kind of array base-plate structure and display device.The array base-plate structure includes：Substrate, there is the first surface and second surface being oppositely arranged, and the substrate has perforation；First film transistor, on the first surface of substrate；And second thin film transistor (TFT), on the second surface of substrate, wherein first film transistor is electrically connected to the second thin film transistor (TFT) via perforation.
Description
Technical field
The present invention relates to a kind of display device, more particularly to a kind of display device with a variety of transistors.
Background technology
The thin film transistor (TFT) of pixel cell is driven, is broadly divided into polysilicon transistors such as low-temperature polycrystalline silicon transistor (LTPS
Transistor), with MOS transistor (such as IGZO transistors).The former has high firing current (Ion) and high carrier
Mobility, and the latter has low closing electric current (Ioff) and the good uniformity.Both respectively have its own advantage, but without a kind of transistor
The advantages of both can be had concurrently simultaneously.
The advantages of in order to have above two transistor concurrently, have circuit design such as 2T1C or 4T2C at present, it uses two kinds
The single pixel cell of transistor driving above.But in the field of display, the area shared by transistor is bigger, then shows
The relative area in area is smaller, that is, reduces the resolution ratio for showing image.In other words, use the circuit design of multiple transistors will at present
The problem of causing resolution ratio to reduce.
In summary, new structure is needed badly at present, it is excessive and reduce resolution ratio to solve multiple transistor occupied areas
Problem.
The content of the invention
The array base-plate structure that one embodiment of the invention provides, including：Substrate, there is the first surface that is oppositely arranged and the
Two surfaces, and substrate has perforation；First film transistor, on the first surface of substrate；And second thin film transistor (TFT),
On the second surface of substrate, wherein first film transistor is electrically connected to the second thin film transistor (TFT) via perforation.
The display device that one embodiment of the invention provides, including：Substrate, there is the first surface and the second table being oppositely arranged
Face, and substrate has perforation；First film transistor, on the first surface of substrate；Second thin film transistor (TFT), positioned at substrate
Second surface on；And luminescence unit, on the second surface of substrate, wherein first film transistor is electrically connected via perforation
The second thin film transistor (TFT) is connected to, and luminescence unit is electrically connected to the second thin film transistor (TFT).
Brief description of the drawings
Fig. 1 is in one embodiment of the invention, using the circuit diagram of the single luminescence unit of multiple transistor drivings；
Fig. 2 is its phantom of the display device of the circuit diagram of corresponding diagram 1 in one embodiment of the invention；
Fig. 3 A to Fig. 3 E are the portions of its manufacture craft of the display device of the circuit diagram of corresponding diagram 1 in one embodiment of the invention
Divide sectional view；
Fig. 4 to Fig. 5 is its phantom of the display device of the circuit diagram of corresponding diagram 1 in the embodiment of the present invention；
Fig. 6 to Fig. 9 is the phantom of touch control display apparatus in the embodiment of the present invention.
Symbol description
11 data wires
13 scan lines
15 drive voltage lines
17 switching transistors
17a, 19c, 21b semiconductor layer
17c channel regions
17d drain regions
17g, 19g grid
17s source areas
19 driving transistors
The contact of 19a, 41,47,59
19d drains
19s source electrodes
21 storage capacitances
23 luminescence units
23a electrodes
23c common electrodes
25 substrates
27 cushions
29th, 29 ', 31 gate insulator
The insulating barrier of 31', 37,48
33 bridging lines
35 organic insulators
39th, 53 protective layer
43rd, 43', 57 perforation
45 external circuits
47th, 49 touch control electrode layer
51 light shield layers
55 touch control units
Embodiment
Fig. 1 is in one embodiment of the invention, using the circuit diagram of the single luminescence unit of multiple transistor drivings.Data wire 11
It is orthogonal to define pixel with scan line 13, and have switching transistor 17 luminous to drive with driving transistor 19 in pixel
Unit 23.In one embodiment, switching transistor 17 is polysilicon transistors (such as LTPS transistors), and driving transistor 19 is
MOS transistor (such as IGZO transistors).In other embodiments, switching transistor 17 and driving transistor 19 are phase
Allomeric pipe.As shown in figure 1, scan line 13 is connected to the grid of switching transistor 17, and data wire 11 is connected to switch crystal
The source electrode of pipe 17.The drain electrode of switching transistor 17 is connected to the grid of driving transistor 19, and drive voltage line 15 is connected to drive
The source electrode of dynamic transistor 19.The drain electrode of driving transistor 19 is connected to the pole plate of storage capacitance 21 and the electrode of luminescence unit 23,
And the grid of the drain electrode of switching transistor 17 and driving transistor 19 is connected to another pole plate of storage capacitance 21.As for luminous list
Another electrode of member 23 is then common electrode.
Fig. 2 is its phantom of the display device of the circuit diagram of corresponding diagram 1 in one embodiment of the invention.Such as Fig. 2 institutes
Show, cushion 27 is formed on substrate 25.In one embodiment, substrate 25 can be glass substrate, and cushion 27 can be oxidation
Silicon, silicon nitride or above-mentioned sandwich construction.Then semiconductor layer 17a is formed in the predetermined region for forming switching transistor 17, and
Semiconductor layer 21b is formed in the predetermined region for forming driving transistor 19.In one embodiment, semiconductor layer 17a and 21b material
Material can be low temperature polycrystalline silicon.Semiconductor layer 17a can be divided into channel region 17c and channel region both sides source area 17s and drain region
17d.Gate insulator 29 is subsequently formed on semiconductor layer 17a and 21b and cushion 27.In one embodiment, gate insulator
Layer 29 is silica.Then grid 17g is formed on respective channel area 17c gate insulator 29, and in corresponding semiconductor layer
Grid 19g is formed on 21b gate insulator 29.In one embodiment, grid 17g and 19g material is metal.So far shape
Into the primary structure of switching transistor 17, and semiconductor layer 21b, grid 19g, with being located in gate insulator 29 between the two
Form storage capacitance 21.
Gate insulator 31 is subsequently formed on grid 17g and 19g and gate insulator 29.In one embodiment, grid
Insulating barrier 31 can be silica.Semiconductor layer 19c is subsequently formed on corresponding grid 19g gate insulator 31.Implement one
In example, semiconductor layer 19c is metal-oxide semiconductor (MOS) such as IGZO.Then it is exhausted through grid multiple through holes to be defined with Lithography Etching
Edge layer 29 and 31, redeposited conductive material is in through hole and is stratification on gate insulator 31.Work is made with Lithography Etching etc. afterwards
Skill patterned conductive layer, source area 17s data wire 11, via through holes are connected to define via through holes and are connected to sweeping for grid 17g
Retouch line (not shown), via through holes connect drain region 17d and grid 19g bridging line 33, are connected to source electrode 19s drive voltage line
(not shown) and source electrode 19s and the drain electrode 19d for being connected to semiconductor layer 21b.Source electrode 19s is contacted and partly led respectively with drain electrode 19d
Body layer 19c both sides.So far the primary structure of driving transistor 19 has been formed.Organic insulator 35 is subsequently formed in above-mentioned conduction
In circuit/structure and gate insulator 31, then through hole is defined with Lithography Etching and passes through organic insulator 35.Conductive material is deposited afterwards
In through hole with organic insulator 35, then with the manufacture craft pattern conductive layer such as Lithography Etching, to define via through holes connection
To drain electrode 19d electrode 23a.Insulating barrier 37 is formed afterwards on electrode 23a, then Lithography Etching forms opening exposed portion electrode
23a.In one embodiment, the material of insulating barrier 37 is organic insulation layer material.Luminescence unit 23 is formed afterwards in opening
On electrode 23a, common electrode 23c is re-formed on luminescence unit 23 and insulating barrier 37.
In Fig. 2 structure, switching transistor 17 is respectively positioned on (same on the upper surface of substrate 25 with driving transistor 19
Side), therefore transistor area occupied area is larger and reduces image resolution.
Fig. 3 A to Fig. 3 E are the portions of its manufacture craft of the display device of the circuit diagram of corresponding diagram 1 in one embodiment of the invention
Divide sectional view.In the following embodiments, unless otherwise noted, then the material of the unit of identical label and forming method and foregoing reality
The similar units for applying example are similar without repeating.As shown in Figure 3A, cushion 27 is formed on substrate 25.Then opened in predetermined formation
The region for closing transistor 17 forms semiconductor layer 17a.In one embodiment, semiconductor layer 17a material can be low temperature polycrystalline silicon.
Semiconductor layer 17a can be divided into channel region 17c and channel region both sides source area 17s and drain region 17d.It is subsequently formed gate insulator
Layer 29 is on semiconductor layer 17a and cushion 27.Then grid 17g is formed on respective channel area 17c gate insulator 29
With scan line 13.In figure 3 a, scan line 13 is contacted after grid 17g coilings.So far the main knot of switching transistor 17 has been formed
Structure.
Insulating barrier 31' is subsequently formed on grid 17g, scan line 13 and gate insulator 29.In one embodiment, absolutely
Edge layer 31' is similar with the material of foregoing gate insulator 31.Then multiple through holes are defined with Lithography Etching and passes through gate insulator
Layer 29 and insulating barrier 31', redeposited conductive material is in through hole with being stratification on insulating barrier 31'.Made afterwards with Lithography Etching etc.
Art pattern CAD conductive layer, to define, via through holes are connected to source area 17s data wire 11 and via through holes are connected to scan line
13 contact.Protective layer 39 is formed afterwards on data wire 11, contact and insulating barrier 31'.In one embodiment, protective layer 39
Material can be that redeposition above it has after organic or inorganic material, or first inorganic material (silica, silicon nitride)
Machine material is protected.Lithography Etching forms through hole and passes through protective layer 39 afterwards, and conductive material is inserted into through hole and is stratification in protection
On layer 39, then Lithography Etching defines the contact 41 of via through holes contact data wire 11 and contact respectively.
Then as shown in Figure 3 B, perforation 43 is formed through cushion 27 and substrate 25, with exposed portion drain region 17d.
In another embodiment, perforation 43 can be initially formed through substrate 25 with after cushion 27, re-forming semiconductor layer 17a and layer thereon
Shape structure.
Then as shown in Figure 3 C, after conductive material being inserted into perforation 43, it is stratification on the lower surface of substrate 25.Then photoengraving
Conductive layer is carved to define the grid 19g that perforated 43 is connected to the drain region 17d of switching transistor 17.Gate insulator is formed afterwards
Layer 29' is on grid 19g and substrate 25.In one embodiment, gate insulator 29' material selection and the class of gate insulator 29
Seemingly.Semiconductor layer 19c is subsequently formed on corresponding grid 19g gate insulator 29'.
As shown in Figure 3 D, source electrode 19s and drain electrode 19d is subsequently formed on semiconductor layer 19c both sides, and is connected to source
Pole 19s drive voltage line (not shown).Organic insulator 35 is formed afterwards in gate insulator 29', source electrode 19s, drain electrode
On 19d and semiconductor layer 19c.So far the major part of driving transistor 19 has been completed.Grid 19g, drain electrode 19d, with being located in
Gate insulator 29' composition storage capacitances 21 between the two.Then through hole is formed with Lithography Etching and passes through organic insulator 35,
And conductive material is inserted into through hole and is stratification on organic insulator 35.Lithography Etching conductive layer is leaked with defining via through holes contact afterwards
Pole 19d electrode 23a, insulating barrier 37 is re-formed on electrode 23a and organic insulator 35, and opening dew is formed with Lithography Etching
Go out partial electrode 23a.Luminescence unit 23 is formed afterwards on the electrode 23a in opening, re-forms common electrode 23c in luminous single
In member 23.In certain embodiments, luminescence unit 23 can be the hair that Organic Light Emitting Diode (OLED) or inorganic laminated thing stack
Optical diode (LED).
In fig. 3d, switching transistor 17 and driving transistor 19 be overlapping on the direction on the surface of substrate 25,
The area shared by transistor can be reduced and increase image resolution.In addition, luminescence unit 23 is perpendicular to the surface of substrate 25
It is not overlapping with above-mentioned transistor on direction.Consequently, it is possible to when electrode 23a and common electrode 23c uses transparent conductive material such as
ITO, and organic insulator 35, gate insulator 29', substrate 25, cushion 27, gate insulator 29, insulating barrier 31' and guarantor
When the material of sheath 39 is with gauge, breathable light, the light that above-mentioned luminescence unit 23 is sent can be upward with passing display device down.
In this embodiment, the luminous display device in display device category both sides.In another embodiment, electrode 23a, organic insulator
35th, the material of gate insulator 29', substrate 25, cushion 27, gate insulator 29, insulating barrier 31' and protective layer 39 and thickness
Light-permeable is spent, and common electrode 23c belongs to lighttight conductive material such as metal.Now display device category unilateral (upside) is luminous
Display device.In another embodiment, electrode 23a, organic insulator 35, gate insulator 29', substrate 25, cushion 27, grid
Pole insulating barrier 29, insulating barrier 31', with least one of protective layer 39 can not printing opacity, and the conduction material of common electrode 23c category printing opacities
Material such as ITO.The now luminous display device of display device category unilateral (downside).
As shown in FIGURE 3 E, external circuit 45 is then bonded to contact 41.In one embodiment, external circuit 45 can be print
Printed circuit board (PCB) or integrated circuit (IC).In this embodiment, external circuit 45 and the homonymy of switching transistor 17, and with drive
Move transistor 19 and luminescence unit 23 not homonymy.
In another embodiment, switching transistor 17 and the first perforation through the first membrane material can be formed in the first membrane material
(being filled with conductive material).In addition, driving transistor 19 and luminescence unit 23 can be formed in the second membrane material, and through the second film
Second perforation (being filled with conductive material) of material.In one embodiment, the material of above-mentioned membrane material can be macromolecule membrane.Then by two
Membrane material bonding is opened, makes the perforation of the first perforation alignment second, to form the structure shown in Fig. 3 E.The advantages of such a manufacture craft, is
The manufacture craft yield of switching transistor 17, will not mutual shadow with the manufacture craft yield of driving transistor 19 and luminescence unit 23
Ring.
Fig. 4 is its phantom of the display device of the circuit diagram of corresponding diagram 1 in one embodiment of the invention.Such as Fig. 4 institutes
Show, cushion 27 is formed on substrate 25.Then semiconductor layer 17a is formed in the predetermined region for forming switching transistor 17.Half
Conductor layer 17a can be divided into channel region 17c and channel region both sides source area 17s and drain region 17d.It is subsequently formed gate insulator
29 on semiconductor layer 17a and cushion 27.Then scan line 13 and grid 17g, and grid are formed on gate insulator 29
17g respective channels area 17c.So far the primary structure of switching transistor 17 has been formed.
Insulating barrier 31' is subsequently formed on grid 17g, scan line 13 and gate insulator 29.Then determined with Lithography Etching
The multiple through holes of justice are through gate insulator 29 and insulating barrier 31', and redeposited conductive material is in through hole with being stratification in insulating barrier 31'
On.Afterwards with the manufacture craft pattern conductive layer such as Lithography Etching, source area 17s is connected to contacting substrate to define via through holes
25 data wire 11.In Fig. 4, contact scanning line 13 again after grid 17g coilings.Afterwards formed protective layer 39 in data wire 11 with
On insulating barrier 31'.
Perforation 43' is subsequently formed through substrate 25, cushion 27 and gate insulator 29, to expose drain region 17d, connect
It is connected to the through hole and scan line 13 of data wire 11.Then conductive material is inserted into above-mentioned perforation and is stratification in the following table of substrate 25
On face, then Lithography Etching conductive layer is to define grid 19g and contact 19a.Afterwards formed gate insulator 29' in grid 19g with
On contact 19a.Semiconductor layer 19c is subsequently formed on corresponding grid 19g gate insulator 29'.
Source electrode 19s and drain electrode 19d is subsequently formed on semiconductor layer 19c both sides, and is connected to source electrode 19s driving
Pressure-wire (not shown).Organic insulator 35 is formed afterwards in gate insulator 29', source electrode 19s, drain electrode 19d and semiconductor layer
On 19c.So far the major part of driving transistor 19 has been completed.Grid 19g, drain electrode 19d, with being located in grid between the two
Insulating barrier 29' forms storage capacitance 21.Then through hole is formed with Lithography Etching and pass through organic insulator 35, and be open through having
Machine insulating barrier 35 and gate insulator 29'.Conductive material is inserted into through hole, and is stratification in the side wall and organic insulator 35 of opening
On.Lithography Etching conductive layer is to define via through holes contact drain electrode 19d electrode 23a afterwards, and positioned at the bottom of opening and side
The contact 47 of (and contact terminal 19a) on wall and part organic insulator 35.
Insulating barrier 37 is formed afterwards on electrode 23a and organic insulator 35, and opening exposed division is formed with Lithography Etching
Sub-electrode 23a.Luminescence unit 23 is subsequently formed on the electrode 23a in opening, re-forms common electrode 23c in luminescence unit 23
On.In addition, external circuit 45 can be bonded to contact 47.
In Fig. 4, switching transistor 17 is located on the upper surface and lower surface of substrate 25 respectively with driving transistor 19, and
Switching transistor 17 and driving transistor 19 are overlapping on the direction on the surface of substrate 25, to reduce face shared by transistor
Product.In this embodiment, luminescence unit 23 is on the direction on the surface of substrate 25, not with switching transistor 17 and driving
Transistor 19 is overlapping, therefore it is alternatively unilateral luminous or dual-side emissive, hold the material of bedway thing and thickness whether printing opacity and
It is fixed.Fig. 4 and Fig. 3 E difference is that Fig. 4 external circuit 45 is to be located at homonymy with driving transistor 19 and luminescence unit 23.
Fig. 5 is similar with Fig. 3 E structure, and difference is Fig. 5 luminescence unit 23 in the direction vertical with the surface of substrate 25
On, it is overlapping with switching transistor 17 and driving transistor 19.Consequently, it is possible to pixel further can be reduced and increase image resolution
Rate.But in this embodiment, luminescence unit 23 is necessarily luminous for unilateral (downside), therefore common electrode 23c must be transparent
Conductive material, such as ITO.
Above-mentioned display device can be integrated further with touch control unit, as shown in Figure 6 to form touch control display apparatus.Citing comes
Say, can be in each self-forming touch control electrode layer 47 in the both sides up and down of Fig. 4 protective layer 39 luminescence unit 23 corresponding with 49, to define
The touch control unit 55 of meaning.In this embodiment, display device is unilateral (upside) display device.To avoid the metal of transistor anti-
Penetrate ambient light, can further form light shield layer 51 on protective layer 39, with the transistor area beyond corresponding luminescence unit 23 with it is outer
Portion's circuit 45.Then protective layer 53 can be formed on light shield layer 51, touch control electrode layer 49 and protective layer 39.In one embodiment,
The material of protective layer 53 can be organic or inorganic insulating layer material.When protective layer 53 is covering protection glass (not shown), protect
Sheath 53 is simultaneously comprising the adhesive agent pasted with protective glass.In other embodiments, the touch control electrode layer of individual layer can be used, its
It can be located on the upper surface or lower surface of protective layer 39.
Fig. 7 is similar with Fig. 6, and difference is that the position of Fig. 7 touch control electrode layer 47 and 49 is located on the both sides of substrate 25.One
As for, touch control electrode layer 47 and 49 can be initially formed on the upper surface and lower surface of substrate 25, after defining touch control unit 55,
Re-form cushion 27 and other nonwoven fabric from filaments thereon.In one embodiment, can before touch control electrode layer 47 and 49 is formed or
Perforation 43 is formed afterwards, then carries out subsequent manufacturing processes.In other embodiments, the touch control electrode layer of individual layer can be used, it can
On the upper surface of substrate 25 or lower surface.Above-mentioned display device is unilateral (upside) luminous device.
Above-mentioned display device can be integrated further with touch control unit, as shown in Figure 8 to form touch control display apparatus.Citing comes
Say, Fig. 2 luminescence unit 23 can be changed in the direction vertical with the surface of substrate 25, it is unbrilliant with driving with switching transistor 17
The overlapping position of body pipe 19.In addition, before cushion 27 is formed, light shield layer 51 is initially formed on substrate 25, and light shield layer 51 is right
Switching transistor 17 and driving transistor 19 should be formed afterwards.Perforation 57 passes through gate insulator 31, gate insulator 29, buffering
Layer 27 and substrate 25.Insulating barrier 37 does not cover corresponding perforation 57 and the organic insulator 35 of data wire 11.Formation opening, which is exposed, wears
Hole 57 and data wire 11, and the step of formation electrode 23a also forms conductive material and covers the bottom being open with side wall to define contact
59.External circuit 45 is bonded to contact 59.Touch control electrode layer 47 is located on the lower surface of substrate 25, and via perforation 57 and contact
59 are electrically connected to external circuit 45.Insulating barrier 48 is located on the lower surface of touch control electrode layer 47 and substrate 25, touch control electrode layer 49
On insulating barrier 48, and protective layer 53 is located on touch control electrode layer 49 and insulating barrier 48.In one embodiment, insulating barrier 48
Material is inorganic or organic material.In one embodiment, the material of protective layer 53 is organic or inorganic insulating layer material.Work as protection
When layer 53 is covering protection glass (not shown), protective layer 53 is simultaneously comprising the adhesive agent pasted with protective glass.Touch control electrode
Layer 47, touch control electrode layer 49, with being located in insulating barrier 48 i.e. touch control unit 55 between the two.In other embodiments, can adopt
With the touch control electrode layer of individual layer, it can be located on the upper surface or lower surface of insulating barrier 48.Above-mentioned display device for it is unilateral (under
Side) display device.
Fig. 9 is similar with Fig. 8, and difference is that the position of Fig. 9 touch control electrode layer 47 and 49 is located on the both sides of substrate 25.
In other embodiment, the touch control electrode layer of individual layer can be used, it can be located on the upper surface or lower surface of substrate 25.Above-mentioned display
Device is the device of unilateral (downside) display.
Although the present invention is disclosed with reference to several of the above embodiment, but it is not limited to the present invention, any skill
Skilled person in art field, without departing from the spirit and scope of the present invention, arbitrary change and retouching, therefore this can be made
The protection domain of invention should be defined by what the claim enclosed was defined.
Claims (16)
1. a kind of array base-plate structure, including：
Substrate, there is the first surface and second surface being oppositely arranged, and the substrate has perforation；
First film transistor, on the first surface of the substrate；And
Second thin film transistor (TFT), on the second surface of the substrate,
Wherein the first film transistor is electrically connected to second thin film transistor (TFT) via the perforation.
2. array base-plate structure as claimed in claim 1, the wherein first film transistor are a polysilicon transistors, bag
Include：
Polysilicon semiconductor layer, there is channel region, be located between source region and a drain region；
First grid, to should channel region；And
Gate insulator, between the polysilicon semiconductor layer and the first grid,
The source area of the wherein polysilicon semiconductor layer is connected to a data wire, and the drain region of the polysilicon semiconductor layer is connected to
The perforation, and the first grid is connected to scan line.
3. array base-plate structure as claimed in claim 1, wherein second thin film transistor (TFT) is MOS transistor, bag
Include：
Second grid；
Metal oxide semiconductor layer, to should grid；
Gate insulator, between the second grid and the metal oxide semiconductor layer；And
Source electrode and drain electrode, the both sides of the metal oxide semiconductor layer are contacted respectively,
Wherein the source electrode is connected to a drive voltage line, and the second grid is connected to the perforation.
4. array base-plate structure as claimed in claim 1, the wherein the first transistor are with the second transistor perpendicular to this
The direction of first surface is overlapping.
5. array base-plate structure as claimed in claim 1, the wherein substrate include the first membrane material directly contacted and the second film
Material, the first transistor are located in first membrane material, and the second transistor is located in second membrane material.
6. array base-plate structure as claimed in claim 1, in addition to touch control electrode layer, directly contact first table of the substrate
Face or the second surface.
7. a kind of display device, including：
Substrate, there is the first surface and second surface being oppositely arranged, and the substrate has perforation；
First film transistor, on the first surface of the substrate；
Second thin film transistor (TFT), on the second surface of the substrate；And
Luminescence unit, on the second surface of the substrate,
Wherein the first film transistor is electrically connected to second thin film transistor (TFT) via the perforation, and the luminescence unit electrically connects
To second thin film transistor (TFT).
8. display device as claimed in claim 7, the wherein first film transistor are polysilicon transistors, including：
Polysilicon semiconductor layer, there is channel region, be located between source area and drain region；
First grid, to should channel region；And
Gate insulator, between the polysilicon semiconductor layer and the first grid,
The source area of the wherein polysilicon semiconductor layer is connected to a data wire, and the drain region of the polysilicon semiconductor layer is connected to
The perforation, and the first grid is connected to scan line.
9. display device as claimed in claim 7, wherein second thin film transistor (TFT) is MOS transistor, including：
Second grid；
Metal oxide semiconductor layer, to should grid；
Gate insulator, between the second grid and the metal oxide semiconductor layer；
Source electrode and drain electrode, the both sides of the metal oxide semiconductor layer are contacted respectively,
Wherein the source electrode is connected to a drive voltage line, and the second grid is connected to the perforation, and the drain electrode is connected to this and lighted
Unit.
10. display device as claimed in claim 7, the wherein the first transistor and the second transistor perpendicular to this first
The direction on surface is overlapping.
11. display device as claimed in claim 10, the wherein luminescence unit and the second transistor perpendicular to this first
The direction on surface is overlapping.
12. display device as claimed in claim 11, in addition to external circuit, the first transistor is bonded to, and outside this
Circuit is located on the first surface of the substrate.
13. display device as claimed in claim 10, the wherein luminescence unit and the second transistor perpendicular to this first
The direction on surface is not overlapping.
14. display device as claimed in claim 13, in addition to external circuit, the first transistor is bonded to, and outside this
Circuit is located on the second surface of the substrate.
15. display device as claimed in claim 7, the wherein substrate include the first membrane material directly contacted and the second membrane material,
The first transistor is located in first membrane material, and the second transistor is located in second membrane material with the luminescence unit.
16. display device as claimed in claim 7, in addition to touch control electrode layer, contact the first surface of the substrate or be somebody's turn to do
Second surface.
Priority Applications (1)
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| CN201610525395.6A CN107579056A (en) | 2016-07-05 | 2016-07-05 | Array base-plate structure and display device |
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| CN201610525395.6A CN107579056A (en) | 2016-07-05 | 2016-07-05 | Array base-plate structure and display device |
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| CN108831892A (en) * | 2018-06-14 | 2018-11-16 | 京东方科技集团股份有限公司 | Show backboard and its manufacturing method, display panel and display device |
| CN109285845A (en) * | 2018-08-03 | 2019-01-29 | 友达光电股份有限公司 | Array substrate, display device using the same, and method for manufacturing the same and device |
| CN110796961A (en) * | 2018-07-31 | 2020-02-14 | 乐金显示有限公司 | Light emitting display device |
| TWI714093B (en) * | 2019-05-21 | 2020-12-21 | 友達光電股份有限公司 | Array substrate |
| CN112599537A (en) * | 2020-12-11 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | Display substrate and preparation method thereof |
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