CN107579055A - One kind overlapping encapsulating structure - Google Patents
One kind overlapping encapsulating structure Download PDFInfo
- Publication number
- CN107579055A CN107579055A CN201710762485.1A CN201710762485A CN107579055A CN 107579055 A CN107579055 A CN 107579055A CN 201710762485 A CN201710762485 A CN 201710762485A CN 107579055 A CN107579055 A CN 107579055A
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- holding tank
- lead frame
- overlapping
- encapsulating structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The present invention discloses a kind of overlapping encapsulating structure, including lead frame, lead frame has relative upper and lower surface, passive device is fixedly installed on upper surface, lead frame corresponds to passive device and is provided with multiple leads, the holding tank for accommodating semiconductor chip is provided with lower surface, semiconductor chip is arranged in holding tank, and the solder joint of semiconductor chip is located remotely from the side of holding tank, insulated between semiconductor chip and lead frame, by the holding tank for being provided for accommodating semiconductor chip on the lower surface of lead frame, semiconductor chip is arranged within holding tank, and passive device is arranged to the upper surface of lead frame, realize and the overlapping of passive device and semiconductor chip is encapsulated, simultaneously semiconductor chip can be protected to avoid being destroyed by the external world, reduce the use of encapsulating material, save production cost.
Description
Technical field
The present invention relates to technical field of electronic products, more particularly to a kind of overlapping encapsulating structure.
Background technology
In semiconductor integrated circuit, for semiconductor integrated circuit chip position set and encapsulate it is particularly important,
Good encapsulation can play placement, fixation, sealing, protection chip to the chip of semiconductor integrated circuit and strengthen electric heating property
Effect.And with the continuous development of semiconductor technology, require less and less for the encapsulation volume of semiconductor components and devices, therefore be
The less and less development trend of encapsulation volume is adapted to, the skill that multiple semiconductor chips overlap to encapsulation occurs in the market
Art.And be mostly that the chip of multiple same types is subjected to overlapping encapsulation in these techniques, encapsulation requires higher, and packaging technology is answered
It is miscellaneous, easily chip is caused to damage in encapsulation process.
The content of the invention
It is an object of the invention to：A kind of overlapping encapsulating structure is provided, it can be by Passive components and semiconductor chip
Overlapping is packaged as a whole.
To use following technical scheme up to this purpose, the present invention：
A kind of overlapping encapsulating structure is provided, including lead frame, the lead frame have relative upper surface and following table
Face, passive device is fixedly installed on the upper surface, the lead frame corresponds to the passive device and is provided with multiple leads,
The holding tank for accommodating semiconductor chip is provided with the lower surface, the semiconductor chip is arranged at the holding tank
It is interior, and the solder joint of the semiconductor chip is located remotely from the bottom land side of the holding tank, the semiconductor chip draws with described
Insulated between wire frame.
As a kind of perferred technical scheme, under the solder joint of the semiconductor chip and the described of the lead frame
Flush.
As a kind of perferred technical scheme, the lead by the upper surface of the lead frame lead to it is described under
On surface.
As a kind of perferred technical scheme, the leg of the passive device is welded in place in institute by conductive bonding material
State on the lead of upper surface.
As a kind of perferred technical scheme, the semiconductor chip passes through non-conductive solder material and the holding tank
Bottom land is fixedly connected.
As a kind of perferred technical scheme, the width of the holding tank is more than the width of the semiconductor chip, described
Semiconductor chip does not contact with the side of the holding tank.
As a kind of perferred technical scheme, the depth of the holding tank is more than the thickness of the semiconductor chip.
As a kind of perferred technical scheme, the space between the side of the semiconductor chip and the holding tank uses
Protection materials are filled.
As a kind of perferred technical scheme, the protection materials are non-conductive fill material, for further protection
The semiconductor chip.
As a kind of perferred technical scheme, opened up in the middle part of the bottom land of the holding tank through the logical of the lead frame
Hole, the passive device are located at the through hole.
Beneficial effects of the present invention are：By the appearance for being provided for accommodating semiconductor chip on the lower surface of lead frame
Receive groove, semiconductor chip is arranged within holding tank, and passive device is arranged to the upper surface of lead frame, realize to quilt
The overlapping encapsulation of dynamic element and semiconductor chip, while semiconductor chip can be protected to avoid being destroyed by the external world, reduce encapsulation
The use of material, save production cost.
Brief description of the drawings
The present invention is described in further detail below according to drawings and examples.
Fig. 1 is the structural representation that encapsulating structure is overlapped described in embodiment.
In figure：
1st, lead frame；101st, upper surface；102nd, lower surface；2nd, passive device；3rd, semiconductor chip；301st, solder joint；4、
Conductive bonding material；5th, non-conductive solder material；6th, non-conductive fill material.
Embodiment
Further illustrate technical scheme below in conjunction with the accompanying drawings and by embodiment.
As shown in figure 1, in the present embodiment, a kind of overlapping encapsulating structure of the present invention, including lead frame 1, institute
Stating lead frame 1 has relative upper surface 101 and lower surface 102, and passive device 2 is fixedly installed on the upper surface 101,
The corresponding passive device 2 of the lead frame 1 is provided with multiple leads, is provided with the lower surface 102 for accommodating half
The holding tank of conductor chip 3, the semiconductor chip 3 is arranged in the holding tank, and the solder joint of the semiconductor chip 3
301 are located remotely from the bottom land side of the holding tank, are insulated between the semiconductor chip 3 and the lead frame 1.
By being provided for accommodating the holding tank of semiconductor chip 3 on the lower surface 102 of lead frame 1, by semiconductor
Chip 3 is arranged within holding tank, and passive device 2 is arranged to the upper surface 101 of lead frame 1, is realized to passive device 2
And the overlapping encapsulation of semiconductor chip 3.Holding tank is set on the lower surface 102 of lead frame 1, and semiconductor chip 3 is set
It is placed within holding tank, lead frame 1 can protect semiconductor chip 3 to avoid being destroyed by the external world, the lead frame of metal material
Frame 1 preferably can also distribute caused heat in the course of work of semiconductor chip 3.Meanwhile semiconductor chip 3 is set
It is placed in the holding tank of lower surface 102 of lead frame 1, the use of encapsulating material can be reduced, saves manufacturing cost.
Preferably, the lower surface 102 of the solder joint 301 of the semiconductor chip 3 and the lead frame 1 is flat
Together.
The solder joint 301 of semiconductor chip 3 is concordant with the lower surface 102 of lead frame 1 to be easy to that packaged half will be overlapped
Conductor chip 3 and passive device 2 are welded on pcb board, and the solder joint 301 of semiconductor chip 3 can be avoided not concordant with lead frame 1
The welding phenomenon not in place or rosin joint of appearance, ensure that the passive device 2 and semiconductor encapsulated using the overlapping encapsulating structure
The reliability of chip 3 when in use.
Preferably, the lead is led on the lower surface 102 by the upper surface 101 of the lead frame 1.
Lead with the welding of the leg of passive device 2 is led on the lower surface 102 of lead frame 1, can facilitate to fold
Semiconductor chip 3 and passive device 2 after conjunction encapsulation are welded to welding when on pcb board to passive device 2, avoid being welded to
Occurs the problem of operation is complicated when on pcb board.
Further, the leg of the passive device 2 is welded in place in the upper surface 101 by conductive bonding material 4
The lead on.
The leg of passive device 2 is welded on the lead of upper surface 101 of lead frame 1 by conductive bonding material 4,
The fixation to passive device 2 can easily be realized.
Preferably, the semiconductor chip 3 is fixedly connected by non-conductive solder material 5 with the bottom land of the holding tank.
Semiconductor chip 3 is welded on the bottom land of holding tank by non-conductive solder material 5, can be easily to semiconductor
Chip 3 is fixed.
Preferably, the width of the holding tank is more than the width of the semiconductor chip 3, the semiconductor chip 3 and institute
The side for stating holding tank does not contact.
Semiconductor chip 3 easily can be arranged in holding tank by the width that the width of holding tank is more than semiconductor chip 3,
The side of semiconductor chip 3 does not contact with holding tank simultaneously can prevent short circuit caused by holding tank contact with semiconductor chip 3,
The safe to use and service life of semiconductor chip 3 is ensure that, and is caused more square using the production of the overlapping encapsulating structure
Just, the placement for semiconductor chip 3 requires relatively low, can realize quick production, improves production efficiency.
Specifically, the depth of the holding tank is more than the thickness of the semiconductor chip 3.
Further, the space between the side of the semiconductor chip 3 and the holding tank is carried out using protection materials
Filling.
Further, the protection materials are non-conductive fill material 6, for semiconductor core described in further protection
Piece 3.
Space between semiconductor chip 3 and holding tank is filled using protection materials, can be strengthened to semiconductor core
The protection of piece 3, avoid semiconductor chip 3 come off and semiconductor chip 3 contacts with holding tank and causes short circuit.
As a kind of perferred technical scheme, opened up in the middle part of the bottom land of the holding tank through the logical of the lead frame 1
Hole, the passive device 2 are located at the through hole.The setting of through hole can be easy to semiconductor chip 3 and passive device 2 to be connect with air
Touch, strengthen radiating effect.
It is to be understood that above-mentioned embodiment is only that presently preferred embodiments of the present invention and institute's application technology are former
Reason, in technical scope disclosed in this invention, change that any one skilled in the art is readily apparent that or
Replace, should all cover within the scope of the present invention.
Above by specific embodiment, the present invention is described, but the present invention is not limited to these specific implementations
Example.It will be understood by those skilled in the art that various modifications, equivalent substitution, change etc. can also be made to the present invention.But this
A little conversion, all should be within protection scope of the present invention without departing from the spirit of the present invention.In addition, present specification and power
Some terms used in sharp claim are not limitation, it is only for are easy to describe.In addition, " one described in above many places
Individual embodiment ", " another embodiment " etc. represent different embodiments, naturally it is also possible to which its all or part is incorporated in into one
In embodiment.
Claims (10)
1. one kind overlapping encapsulating structure, it is characterised in that including lead frame, the lead frame have relative upper surface and
Lower surface, is fixedly installed passive device on the upper surface, the lead frame correspond to the passive device be provided with it is multiple
Lead, the holding tank for accommodating semiconductor chip is provided with the lower surface, and the semiconductor chip is arranged at the appearance
Receive in groove, and the solder joint of the semiconductor chip is located remotely from the bottom land side of the holding tank, the semiconductor chip and institute
State and insulate between lead frame.
2. overlapping encapsulating structure according to claim 1, it is characterised in that the solder joint of the semiconductor chip and institute
The lower surface for stating lead frame is concordant.
3. overlapping encapsulating structure according to claim 1, it is characterised in that the lead is as described in the lead frame
Upper surface is led on the lower surface.
4. overlapping encapsulating structure according to claim 1, it is characterised in that the leg of the passive device is welded by conduction
Material is connect to be welded in place on the lead of the upper surface.
5. overlapping encapsulating structure according to claim 1, it is characterised in that the semiconductor chip passes through non-conductive solder
Material is fixedly connected with the bottom land of the holding tank.
6. overlapping encapsulating structure according to claim 1, it is characterised in that the width of the holding tank is partly led more than described
The width of body chip, the semiconductor chip do not contact with the side of the holding tank.
7. overlapping encapsulating structure according to claim 6, it is characterised in that the depth of the holding tank is partly led more than described
The thickness of body chip.
8. overlapping encapsulating structure according to claim 6, it is characterised in that the side of the semiconductor chip and the appearance
The space received between groove is filled using protection materials.
9. overlapping encapsulating structure according to claim 8, it is characterised in that the protection materials are non-conductive filling material
Material, for semiconductor chip described in further protection.
10. the overlapping encapsulating structure according to any one of claim 1 to 9, it is characterised in that in the bottom land of the holding tank
Portion opens up the through hole through the lead frame, and the passive device is located at the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710762485.1A CN107579055A (en) | 2017-08-30 | 2017-08-30 | One kind overlapping encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710762485.1A CN107579055A (en) | 2017-08-30 | 2017-08-30 | One kind overlapping encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107579055A true CN107579055A (en) | 2018-01-12 |
Family
ID=61030676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710762485.1A Pending CN107579055A (en) | 2017-08-30 | 2017-08-30 | One kind overlapping encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107579055A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314101A (en) * | 2023-05-24 | 2023-06-23 | 晶艺半导体有限公司 | QFN (quad Flat No-lead) stacking packaging structure and preparation method thereof |
Citations (8)
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|---|---|---|---|---|
| US20070246840A1 (en) * | 2006-04-19 | 2007-10-25 | Micron Technology, Inc. | Integrated circuit devices with stacked package interposers |
| US20100019362A1 (en) * | 2008-07-23 | 2010-01-28 | Manolito Galera | Isolated stacked die semiconductor packages |
| US20100244278A1 (en) * | 2009-03-27 | 2010-09-30 | Chipmos Technologies Inc. | Stacked multichip package |
| US7829990B1 (en) * | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
| US8080867B2 (en) * | 2009-10-29 | 2011-12-20 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof |
| CN204167308U (en) * | 2013-12-05 | 2015-02-18 | 江苏长电科技股份有限公司 | Multi-chip stacking falls formal dress without the flat pin metal framework structure of base island combined type |
| CN104425424A (en) * | 2013-09-09 | 2015-03-18 | 日月光半导体制造股份有限公司 | Substrate structure, semiconductor packaging, stacking type packaging structure and manufacturing method thereof |
| CN106847782A (en) * | 2015-10-30 | 2017-06-13 | 新光电气工业株式会社 | Semiconductor device and its manufacture method, lead frame and its manufacture method |
-
2017
- 2017-08-30 CN CN201710762485.1A patent/CN107579055A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070246840A1 (en) * | 2006-04-19 | 2007-10-25 | Micron Technology, Inc. | Integrated circuit devices with stacked package interposers |
| US7829990B1 (en) * | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
| US20100019362A1 (en) * | 2008-07-23 | 2010-01-28 | Manolito Galera | Isolated stacked die semiconductor packages |
| US20100244278A1 (en) * | 2009-03-27 | 2010-09-30 | Chipmos Technologies Inc. | Stacked multichip package |
| US8080867B2 (en) * | 2009-10-29 | 2011-12-20 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof |
| CN104425424A (en) * | 2013-09-09 | 2015-03-18 | 日月光半导体制造股份有限公司 | Substrate structure, semiconductor packaging, stacking type packaging structure and manufacturing method thereof |
| CN204167308U (en) * | 2013-12-05 | 2015-02-18 | 江苏长电科技股份有限公司 | Multi-chip stacking falls formal dress without the flat pin metal framework structure of base island combined type |
| CN106847782A (en) * | 2015-10-30 | 2017-06-13 | 新光电气工业株式会社 | Semiconductor device and its manufacture method, lead frame and its manufacture method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314101A (en) * | 2023-05-24 | 2023-06-23 | 晶艺半导体有限公司 | QFN (quad Flat No-lead) stacking packaging structure and preparation method thereof |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180112 |