CN107577567B

CN107577567B - Mainboard test circuit and related product

Info

Publication number: CN107577567B
Application number: CN201710770098.2A
Authority: CN
Inventors: 李路路
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2017-08-31
Filing date: 2017-08-31
Publication date: 2021-03-12
Anticipated expiration: 2037-08-31
Also published as: CN107577567A

Abstract

The present disclosure provides a motherboard test circuit and related products, including: the test device comprises a first test point, a second test point, a third test point, a fourth test point and a change-over switch; the switch is a dual-channel switch, the first test point is connected with a first control port of the switch, the second test point and the third test point are respectively connected with two common ports of the switch, the fourth test point is grounded, one channel of the switch is connected with a Universal Asynchronous Receiver Transmitter (UART) interface of a central processing unit, and the other channel of the switch is connected with a Universal Serial Bus (USB) of the central processing unit; the switch is connected with the other channel when the first control port is at a high level, and is connected with a channel when the first control port is at a low level. The technical scheme provided by the invention has the advantages of increasing the integration level and reducing the cost.

Description

Mainboard test circuit and related product

Technical Field

The invention relates to the technical field of communication, in particular to a mainboard test circuit and a related product.

Background

With the increase of complexity of the smart phone, hardware circuits and software designs become more complex, software downloading and various application tests need to be completed in the development and production process, automation equipment needs to be used for testing, and meanwhile, the stability of production line manufacturing process needs to be considered. The current designs are all independent designs, and the designs have not reached a better state.

Disclosure of Invention

The embodiment of the invention provides a mainboard test circuit and a related product, which can realize the combined design of the test circuit so as to achieve the advantage of better state.

In a first aspect, an embodiment of the present invention provides a motherboard testing circuit, including a first testing point, a second testing point, a third testing point, a fourth testing point, and a switch; wherein the content of the first and second substances,

the switch is a dual-channel switch, the first test point is connected with a first control port of the switch, the second test point and the third test point are respectively connected with two common ports of the switch, the fourth test point is grounded, one channel of the switch is connected with a Universal Asynchronous Receiver Transmitter (UART) interface of the central processing unit, and the other channel of the switch is connected with a Universal Serial Bus (USB) of the central processing unit; the switch is connected with the other channel when the first control port is at a high level, and is connected with a channel when the first control port is at a low level.

Optionally, the motherboard testing circuit further includes: and one end of the third anti-static circuit is connected with the third test point, and the other end of the third anti-static circuit is connected with the other common port of the change-over switch.

Optionally, the switch further includes a second control port, and when the first control port is at a low level and the second control port is at a medium level, the switch is connected to the channel.

Optionally, the motherboard testing circuit further includes: a voltage divider circuit, the voltage divider circuit comprising: the battery protection circuit comprises a first resistor R1 and a second resistor R2, wherein one end of the first resistor R1 is connected with the positive electrode of the battery, the other end of the first resistor R1 is connected with a second control port and one end of a second resistor R2, and the other end of the second resistor R2 is grounded.

In a second aspect, a smart device is provided, the device comprising: a motherboard, one or more processors, memory, a transceiver, and one or more programs stored in the memory and configured to be executed by the one or more processors, the processor comprising: a modem and an application processor AP; the main board includes: the test device comprises a first test point, a second test point, a third test point, a fourth test point and a change-over switch; the switch is a dual-channel switch, the first test point is connected with the first control port of the switch, the second test point and the third test point are respectively connected with two public ports of the switch, the fourth test point is grounded, one channel of the switch is connected with a Universal Asynchronous Receiver Transmitter (UART) interface of the processor, and the other channel of the switch is connected with a Universal Serial Bus (USB) of the processor.

Optionally, the main board further includes: and one end of the third anti-static circuit is connected with the third test point, and the other end of the third anti-static circuit is connected with the other common port of the change-over switch.

Optionally, the main board further includes: a voltage divider circuit, the voltage divider circuit comprising: the battery protection circuit comprises a first resistor R1 and a second resistor R2, wherein one end of the first resistor R1 is connected with the positive electrode of the battery, the other end of the first resistor R1 is connected with a second control port and one end of a second resistor R2, and the other end of the second resistor R2 is grounded.

Optionally, the intelligent device is: a smart phone, a tablet computer, or a smart watch.

In a third aspect, a motherboard is provided, the motherboard comprising a motherboard testing circuit as claimed in any of claims 1 to 4.

The embodiment of the invention has the following beneficial effects:

it can be seen that, by the embodiment of the invention, the detection of the UART and the USB is realized, so that the method and the device have the advantages of high integration level and cost reduction.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a USB download circuit and a fixture system.

Fig. 2 is a schematic diagram of a UART serial port circuit and a fixture system.

Fig. 3 is a schematic diagram of a motherboard testing circuit according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of another motherboard test circuit according to an embodiment of the present invention.

Fig. 5 is a schematic structural diagram of an intelligent terminal disclosed in the embodiment of the present invention.

Fig. 6 is a schematic structural diagram of another intelligent terminal disclosed in the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," "third," and "fourth," etc. in the description and claims of the invention and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The Mobile terminal in the present invention may include a smart Phone (e.g., an Android Phone, an iOS Phone, a Windows Phone, etc.), a tablet computer, a palmtop computer, a notebook computer, a Mobile Internet device (MID, Mobile Internet Devices), a wearable device, etc., and the Mobile terminal is merely an example, but not an exhaustive list, and includes but is not limited to the Mobile terminal, and for convenience of description, the Mobile terminal is referred to as a User Equipment (UE) in the following embodiments. Of course, in practical applications, the user equipment is not limited to the above presentation form, and may also include: intelligent vehicle-mounted terminal, computer equipment and the like.

For the platform chip solution, UART (Universal Asynchronous Receiver/Transmitter, english) is a port for a production line to test, a test point needs to communicate with a PC (personal computer), and a TVS (Transient Voltage super, diode) protection device also needs to be added; USB (Universal Serial Bus) is an OTG (On-The-Go) device and a port for communicating with a host, and after downloading software, a test point and a TVS device are also required.

Referring to fig. 1, fig. 1 is a USB download circuit and fixture system, referring to fig. 1, the system includes: the main board corresponds to the test point 10, the production line downloading jig 11, the program control power supply 12 and the software 13.

The main board corresponding test point 10 may include: VBUS, USB DM, USB DP and GND, this production line download jig 11 may include: the product downloading jig 11 is further connected with the program control power supply 12 through a VBAT (power supply voltage) thimble, and the product downloading jig 11 is further connected with the software 13.

The specific implementation manner of the connection between the product download jig 11 and the software 13 may be that the personal computer is connected to provide the software corresponding to the USB, or in practical applications, the software may be connected to the USB in other manners

The main flow of the test is that test points VBUS, USB DM, USB DP and GND corresponding to the terminal mainboard are respectively connected with a production line download jig: the VBUS thimble, the DM thimble, the DP thimble and the GND thimble are connected, and after the connection, the software 12 controls the mainboard to execute software downloading or updating flow through the USB so as to test whether the USB of the mainboard is normal.

Referring to fig. 2, fig. 2 provides a UART serial port circuit and fixture system, which includes: the main board corresponds to the test point 20, the production line downloading jig 21, the program control power supply 22 and the software 23.

The main board corresponding test point 20 may include: UARX, and GND, the production line download jig 21 may include: the product downloading jig 21 is further connected with a program control power supply 22 through a VBAT (power supply voltage) thimble, and the product downloading jig 21 is further connected with software 23.

The main flow of the test is that test points UATX, UARX and GND corresponding to a terminal mainboard are respectively downloaded to a production line in a jig: the UATX thimble, the UARX thimble and the GND thimble are connected, and after the connection, the software 23 controls the main board to execute UART transmission data so as to test whether the UART of the main board is normal or not.

Through the above description, the USB test and the UART test are both tested by different production line download tools, and the USB and the UART of the motherboard are tested by different circuits.

Referring to fig. 3, fig. 3 provides a motherboard testing circuit, which is shown in fig. 3 and includes: the test device comprises a first test point 1, a second test point 2, a third test point 3, a fourth test point 4, a change-over switch 301 and a central processing unit 302; the switch 301 may be a dual channel switch, each having two output ports. The first test point is connected to the first control port 3010 of the switch 301, the second test point and the third test point are respectively connected to the two common ports 3018 of the switch 301, the fourth test point is grounded, one channel 3011 of the switch 301 is connected to the UART interface of the central processor 302, and the other channel 3012 of the switch 301 is connected to the USB of the central processor 302.

The central processor 302 may integrate a modem (modem) and an application processor AP.

The switch 301 is connected to the other channel 3012 when the first control port is at a high level, and is connected to the one channel 3011 when the first control port is at a low level.

The motherboard test circuit shown in fig. 3 can implement detection of UART and USB, and the specific principle may be as follows: for USB detection, the first test point may be connected to VBUS of USB, the second test point may be connected to USB DM, the third test point is connected to USB DP, and the fourth test point is connected to GND. Since the first test point is connected to VBUS, and the level of the first test point is a high level of 5V, the switch at this time is switched to another channel 3012 due to the high level input by the first control port, the main board test circuit at this time is equivalent to the USB download circuit and the fixture system shown in fig. 1, and at this time, the central processing unit 302 controls the main board to execute a software download or update process through the USB to test whether the USB of the main board is normal.

The mainboard test circuit shown in fig. 3 is adopted to realize detection of UART, at this time, the first test point is suspended, the second test point can be connected with UART, the third test point is connected with UARX, the fourth test point is connected with GND, at this time, the mainboard test circuit is equivalent to the UART serial port circuit and the jig system shown in fig. 2, and at this time, the central processing unit 302 controls the mainboard to execute UART transmission data to test whether UART of the mainboard is normal or not.

Through the description, the mainboard test circuit realizes the test of the USB and the UART by one circuit, so the mainboard test circuit has the advantages of reducing the redundancy of the circuit, reducing the cost and reducing the test points.

For the system shown in fig. 1 and fig. 2, the test points required for detecting USB and UART are respectively 4 test points for USB shown in fig. 1, 3 test points for UART shown in fig. 2, and only 4 test points for the motherboard test circuit shown in fig. 3 are required to complete testing of USB and UART, so that it has the advantage of reducing test points. In addition, the system shown in fig. 1 and fig. 2 is integrated for the circuit shown in fig. 3, so that the integration level of the circuit is improved, and the redundancy of the circuit is reduced.

Optionally, the main board testing circuit further includes a plurality of anti-static circuits, one end of the first anti-static circuit is connected to the first testing point, the other end of the first anti-static circuit is connected to the first control port of the switch, one end of the second anti-static circuit is connected to the second testing point, the other end of the second anti-static circuit is connected to a common port of the switch, one end of the third anti-static circuit is connected to the third testing point, and the other end of the third anti-static circuit is connected to another common port of the switch.

The static circuit is prevented in setting up and the influence of the static that can avoid the test point to the mainboard, the basic physics characteristic of static: the force of attraction and repulsion; a potential difference exists between the base and the ground; generation of discharge current due to these characteristics, electrostatic discharge may cause the following damage to a semiconductor device: the thin oxide layer is broken down; the leakage current density is high, causing the conductor to be fused; leakage current, which causes premature failure, increases and breakdown voltage becomes high. Therefore, static electricity of the test point can easily cause the thin insulating layer of the mainboard to be damaged and lose efficacy, and further the quality of the mainboard is influenced, so that the service life of the mainboard can be prolonged by adding the anti-static circuit.

Referring to the main board testing circuit shown in fig. 3, for the switch, it corresponds to a normal state, that is, when the switch does not work, the switch is in an intermediate state, that is, in a suspended state, the switch is not connected to one channel or the other channel, because of not working, the level of the first control port at this time is a low level, if the switch is directly switched to one channel from the non-working state, the level of the first control port is also a low level at this time, for the switch at this time, it may not be able to sense whether the intermediate state is maintained or the switch is switched to one channel, and the intermediate state may still be maintained for the switch, which causes the switch to be disconnected, so that the USB cannot perform detection, and the accuracy of detection is affected.

Referring to fig. 4, the switch may further include a second control port 3016, where the second control port is connected to a middle level, and a voltage value of the middle level is between a low level and a high level. The switch is connected with a channel when the second control port is at the middle level.

The technical scheme is to facilitate the direct connection of the change-over switch with a channel, namely, the change-over switch realizes the switching control through the non-zero level, thereby avoiding the problem that the USB detection is switched from the non-working state to cause the switching failure and influencing the detection accuracy.

Optionally, the main board testing circuit further includes a voltage dividing circuit, the voltage dividing circuit includes a first resistor R1 and a second resistor R2, wherein one end of the first resistor R1 is connected to the positive electrode of the battery, the other end of the first resistor R1 is connected to the second control port and one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

The voltage division circuit performs voltage division operation on the battery voltage through the values of R1 and R2, so that the realization of a middle level is realized.

The present invention further provides a motherboard, where the motherboard includes a motherboard testing circuit shown in fig. 3 or fig. 4, and the motherboard testing circuit may specifically refer to the description of fig. 3 or fig. 4, which is not described herein again.

Referring to fig. 5, fig. 5 provides a smart device comprising a motherboard 509, one or more processors 501, a memory 502, a transceiver 503, and one or more programs stored in the memory 502 and configured to be executed by the one or more processors, in particular, the processor 501 comprising: a modem and an application processor AP,

the main board 509 includes: the test system comprises a first test point, a second test point, a third test point, a fourth test point, a change-over switch and a processor 501; the switch may be a dual channel switch, each channel having two output ports. The first test point is connected to the first control port of the switch, the second test point and the third test point are respectively connected to two common ports of the switch, the fourth test point is grounded, one channel of the switch is connected to the UART interface of the processor 501, and the other channel of the switch is connected to the USB of the processor 501.

The mainboard test circuit further comprises a plurality of anti-static circuits, one end of each first anti-static circuit is connected with the first test point, the other end of each first anti-static circuit is connected with the first control port of the change-over switch, one end of each second anti-static circuit is connected with the second test point, the other end of each second anti-static circuit is connected with one public port of the change-over switch, one end of each third anti-static circuit is connected with the third test point, and the other end of each third anti-static circuit is connected with the other public port of the change-over switch.

The Processor 501 may be a Processor or a controller, such as a Central Processing Unit (CPU), a general purpose Processor, a Digital Signal Processor (DSP), an Application-Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. The processor may also be a combination of computing functions, e.g., comprising one or more microprocessors, DSPs, and microprocessors, among others. The transceiver 503 may be a communication interface, a transceiver circuit, etc., wherein the communication interface is a generic term and may include one or more interfaces.

The switch can also comprise a second control port, wherein the second control port is connected with a middle level, and the voltage value of the middle level is between the low level and the high level. The switch is connected with a channel when the second control port is at the middle level.

Fig. 6 is a block diagram illustrating a partial structure of a server, which is an intelligent device provided by an embodiment of the present invention. Referring to fig. 6, the server includes: radio Frequency (RF) circuit 910, memory 920, input unit 930, sensor 950, audio circuit 960, Wireless Fidelity (WiFi) module 970, application processor AP980, motherboard 810, and power supply 990. Those skilled in the art will appreciate that the smart device architecture shown in FIG. 6 does not constitute a limitation of smart devices and may include more or fewer components than shown, or some components in combination, or a different arrangement of components.

The main board 810 includes: the test system comprises a first test point, a second test point, a third test point, a fourth test point, a change-over switch and an application processor AP 980; the switch may be a dual channel switch, each channel having two output ports. The first test point is connected with a first control port of the switch, the second test point and the third test point are respectively connected with two common ports of the switch, the fourth test point is grounded, one channel of the switch is connected with a UART interface of the application processor AP980, and the other channel of the switch is connected with a USB of the application processor AP 980.

The following describes each component of the smart device in detail with reference to fig. 6:

the input unit 930 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the smart device. Specifically, the input unit 930 may include a touch display 933, a handwriting pad 931, and other input devices 932. The input unit 930 may also include other input devices 932. In particular, other input devices 932 may include, but are not limited to, one or more of physical keys, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and the like.

The AP980 is a control center of the smart device, connects various parts of the entire smart device using various interfaces and lines, and performs various functions of the smart device and processes data by running or executing software programs and/or modules stored in the memory 920 and calling data stored in the memory 920, thereby integrally monitoring the smart device. Optionally, AP980 may include one or more processing units; alternatively, the AP980 may integrate an application processor that handles primarily the operating system, user interface, and applications, etc., and a modem processor that handles primarily wireless communications. It will be appreciated that the modem processor described above may not be integrated into the AP 980.

Further, the memory 920 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.

RF circuitry 910 may be used for the reception and transmission of information. In general, the RF circuit 910 includes, but is not limited to, an antenna, at least one Amplifier, a transceiver, a coupler, a Low Noise Amplifier (LNA), a duplexer, and the like. In addition, the RF circuit 910 may also communicate with networks and other devices via wireless communication. The wireless communication may use any communication standard or protocol, including but not limited to Global System for Mobile communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), and the like.

The smart device may also include at least one sensor 950, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor may include an ambient light sensor and a proximity sensor, wherein the ambient light sensor may adjust the brightness of the touch display screen according to the brightness of ambient light, and the proximity sensor may turn off the touch display screen and/or the backlight when the mobile phone moves to the ear. As one of the motion sensors, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally, three axes), can detect the magnitude and direction of gravity when stationary, and can be used for applications of recognizing the posture of a mobile phone (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer and tapping), and the like; as for other sensors such as a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor, which can be configured on the mobile phone, further description is omitted here.

The audio circuitry 960, speaker 961, microphone 962 may provide an audio interface between the user and the smart device. The audio circuit 960 may transmit the electrical signal converted from the received audio data to the speaker 961, and the audio signal is converted by the speaker 961 to be played; on the other hand, the microphone 962 converts the collected sound signal into an electrical signal, and the electrical signal is received by the audio circuit 960 and converted into audio data, and the audio data is processed by the audio playing AP980, and then sent to another mobile phone via the RF circuit 910, or played to the memory 920 for further processing.

WiFi belongs to short-distance wireless transmission technology, and the mobile phone can help a user to receive and send e-mails, browse webpages, access streaming media and the like through the WiFi module 970, and provides wireless broadband Internet access for the user. Although fig. 6 shows the WiFi module 970, it is understood that it does not belong to the essential constitution of the smart device and can be omitted entirely as needed within the scope not changing the essence of the invention.

The smart device also includes a power supply 990 (e.g., a battery or a power module) for supplying power to various components, and optionally, the power supply may be logically connected to the AP980 via a power management system, so that functions of managing charging, discharging, and power consumption are implemented via the power management system.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that the acts and modules illustrated are not necessarily required to practice the invention.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.

The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A motherboard test circuit, comprising: the test device comprises a first test point, a second test point, a third test point, a fourth test point and a change-over switch; wherein the content of the first and second substances,

the switch is a dual-channel switch, the first test point is connected with a first control port of the switch, the second test point and the third test point are respectively connected with two common ports of the switch, the fourth test point is grounded, one channel of the switch is connected with a Universal Asynchronous Receiver Transmitter (UART) interface of a central processing unit, and the other channel of the switch is connected with a Universal Serial Bus (USB) of the central processing unit;

the change-over switch is connected with the other channel when the first control port is at a high level, and is connected with a channel when the first control port is at a low level;

when the Universal Serial Bus (USB) is detected, the first test point is connected with the VBUS of the Universal Serial Bus (USB), the second test point is connected with the DM end of the Universal Serial Bus (USB), the third test point is connected with the DP end of the Universal Serial Bus (USB), the fourth test point is connected with the grounding end (GND), the change-over switch is switched to the other channel, the mainboard test circuit is used as a USB download circuit and a jig system, and the central processing unit controls a mainboard to execute a software download or update process through the Universal Serial Bus (USB) so as to test the Universal Serial Bus (USB) of the mainboard;

when the Universal Asynchronous Receiver Transmitter (UART) is detected, the first test point is suspended, the second test point is connected with a UATX end of the Universal Asynchronous Receiver Transmitter (UART), the third test point is connected with a UARX end of the Universal Asynchronous Receiver Transmitter (UART), the fourth test point is connected with a ground end (GND), the mainboard test circuit is used as a serial port circuit and a jig system of the Universal Asynchronous Receiver Transmitter (UART), and the central processing unit controls the mainboard to execute the Universal Asynchronous Receiver Transmitter (UART) to transmit data so as to test the Universal Asynchronous Receiver Transmitter (UART) of the mainboard.

2. The motherboard test circuit of claim 1, further comprising: and one end of the third anti-static circuit is connected with the third test point, and the other end of the third anti-static circuit is connected with the other common port of the change-over switch.

3. The motherboard test circuit as claimed in claim 1 or 2, wherein the switch further comprises a second control port, the switch connects to the channel when the first control port is at a low level and the second control port is at a middle level, and a voltage value of the middle level is between a low level and a high level.

4. The motherboard test circuit of claim 3, further comprising: a voltage divider circuit, the voltage divider circuit comprising: the battery protection circuit comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the anode of the battery, the other end of the first resistor is connected with a second control port and one end of the second resistor, and the other end of the second resistor is grounded.

5. A smart device, the device comprising: a motherboard, one or more processors, memory, a transceiver, and one or more programs stored in the memory and configured to be executed by the one or more processors, the processor comprising: a modem and an application processor AP;

the main board includes: the test device comprises a first test point, a second test point, a third test point, a fourth test point and a change-over switch; the switch is a dual-channel switch, the first test point is connected with a first control port of the switch, the second test point and the third test point are respectively connected with two common ports of the switch, the fourth test point is grounded, one channel of the switch is connected with a Universal Asynchronous Receiver Transmitter (UART) interface of the processor, and the other channel of the switch is connected with a Universal Serial Bus (USB) of the processor;

when the Universal Serial Bus (USB) is detected, the first test point is connected with the VBUS of the Universal Serial Bus (USB), the second test point is connected with the DM end of the Universal Serial Bus (USB), the third test point is connected with the DP end of the Universal Serial Bus (USB), the fourth test point is connected with the grounding end (GND), the change-over switch is switched to the other channel, the mainboard test circuit is used as a USB download circuit and a jig system, and the processor controls a mainboard to execute a software download or update process through the Universal Serial Bus (USB) so as to test the Universal Serial Bus (USB) of the mainboard;

when the Universal Asynchronous Receiver Transmitter (UART) is detected, the first test point is suspended, the second test point is connected with a UATX end of the Universal Asynchronous Receiver Transmitter (UART), the third test point is connected with a UARX end of the Universal Asynchronous Receiver Transmitter (UART), the fourth test point is connected with a ground end (GND), the mainboard test circuit is used as a serial port circuit and a jig system of the Universal Asynchronous Receiver Transmitter (UART), and the processor controls the mainboard to execute the Universal Asynchronous Receiver Transmitter (UART) to transmit data so as to test the Universal Asynchronous Receiver Transmitter (UART) of the mainboard.

6. The smart device of claim 5, wherein the motherboard further comprises: and one end of the third anti-static circuit is connected with the third test point, and the other end of the third anti-static circuit is connected with the other common port of the change-over switch.

7. The intelligent device according to claim 5 or 6, wherein the switch further comprises a second control port, and when the first control port is at a low level and the second control port is at a middle level, the switch is connected to the channel, and a voltage value of the middle level is between a low level and a high level.

8. The smart device of claim 7, wherein the motherboard further comprises: a voltage divider circuit, the voltage divider circuit comprising: the battery protection circuit comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the anode of the battery, the other end of the first resistor is connected with a second control port and one end of the second resistor, and the other end of the second resistor is grounded.

9. The smart device of claim 5, wherein the smart device is: a smart phone, a tablet computer, or a smart watch.

10. A motherboard, characterized in that the motherboard comprises a motherboard test circuit as claimed in any one of claims 1 to 4.