CN107576867B - Co-time base device suitable for comprehensive test of active clock mode device - Google Patents
Co-time base device suitable for comprehensive test of active clock mode device Download PDFInfo
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- CN107576867B CN107576867B CN201710727144.0A CN201710727144A CN107576867B CN 107576867 B CN107576867 B CN 107576867B CN 201710727144 A CN201710727144 A CN 201710727144A CN 107576867 B CN107576867 B CN 107576867B
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Abstract
The invention discloses a common time base device and a common time base method suitable for comprehensive testing of a local active clock working mode device, and particularly relates to the technical field of microwave testing. The common time base device suitable for the comprehensive test of the local active clock working mode device comprises a power divider, wherein the output end of the power divider is connected with a pilot frequency clock common time base closed-loop control loop and a frequency measurement module, the output end of the pilot frequency clock common time base closed-loop control loop is connected with a filter, the frequency measurement module and the pilot frequency clock common time base closed-loop control loop are connected with a main control unit through a data bus, the main control unit is connected with an interface circuit through the data bus, and the interface circuit is connected with an upper computer through a standard program control bus. The device solves the problem that the common time base cannot be realized due to frequency difference between the local clock and an external reference clock (usually 10MHz) of a common test instrument because the local clock of the device only has a local clock output port is closely related to the technical characteristics of the device.
Description
Technical Field
The invention relates to the technical field of microwave testing, in particular to a common time base device and a common time base method suitable for comprehensive testing of local active clock working mode devices.
Background
For a device with only a local clock output port, since the local clock is closely related to its technical characteristics, there is often a problem that a common time base cannot be realized due to a frequency difference with an external reference clock (usually 10MHz) of a common test instrument. Because timing synchronization, control and the like based on a common time base mode are key points for realizing accurate comprehensive test, a common time base method suitable for the comprehensive test of a local active clock working mode device is needed, the realization problem of the accurate comprehensive test function related to the device, the timing control, the synchronization and the like is supported and solved, and the test requirement of practical application is met to the maximum extent in a generalized mode.
The current solutions to such problems are mainly dependent on the external reference clock technology characteristics of the commonly used test instruments. Under a normal condition, the frequency of an external reference clock of a common test instrument is 10MHz, and if the design is not adaptively changed according to the output clock frequency of a tested device, the common time base of the test cannot be realized; the external reference clock frequency of part of the test instrument has a certain range, if the output clock frequency of the tested device is in the range and the technical characteristics such as amplitude and the like also meet the requirements of the test instrument, the common time base of the test can be realized, but if the output clock frequency is not in the range, the common time base of the test cannot be realized.
The common time base problem of the tested device comprehensive test with only a local clock output port is solved by utilizing the external reference clock working mode of the current common test instrument, and the following defects exist:
1. for a common test instrument with an external reference clock frequency of 10MHz, if the design is not adaptively changed according to the output clock frequency of a tested device, a common time base of the test cannot be realized;
2. for a test instrument with an external reference clock frequency within a certain range, if the output clock frequency of a tested device is not within the range or the technical characteristics such as amplitude and the like do not meet the requirements of the test instrument, the common time base of the test cannot be realized;
3. the design is adaptively changed for the related common test instrument aiming at the related technical characteristics such as the frequency of the output clock of the tested device, so that the design change cost is high, the time consumption is high, a universal solution is not provided, the tested device with the related technical characteristics beyond the change design range still cannot meet the common time base requirement of the test, and the comprehensive cost is very high.
Disclosure of Invention
The present invention aims to overcome the above disadvantages, and provides a common time base device and method suitable for the integrated test of a local active clock operation mode device, which can provide a clock bridging function between a device to be tested and a test instrument through a closed-loop control method without knowing local clock information of the local active clock operation mode device or having specific limitation on the frequency of the local active clock operation mode device or adaptively changing the design of the test instrument according to the clock information, so as to realize the common time base of different-frequency clocks between the device to be tested and the test instrument.
The invention specifically adopts the following technical scheme:
the output end of the power divider is connected with a pilot frequency clock common-time-base closed-loop control loop and a frequency measurement module, the output end of the pilot frequency clock common-time-base closed-loop control loop is connected with a filter, the frequency measurement module and the pilot frequency clock common-time-base closed-loop control loop are connected with a main control unit through a data bus, the main control unit is connected with an interface circuit through the data bus, and the interface circuit is connected with an upper computer through a standard program control bus.
Preferably, the pilot frequency clock common-time-base closed-loop control loop is realized based on a programmable gate array, and comprises a digital phase detector, a digital loop filter and a digital frequency synthesizer which are connected in series, wherein the digital frequency synthesizer is connected with a high-stability time base for providing a unified internal reference clock, the output end of the digital frequency synthesizer is respectively connected with a frequency multiplier and a frequency divider, and the output ends of the frequency multiplier and the frequency divider are connected with the digital phase detector.
The common time base method suitable for the comprehensive test of the local active clock working mode device adopts the common time base device suitable for the comprehensive test of the local active clock working mode device, and specifically comprises the following steps:
after the output local clock signal of the tested device enters the device, the power divider divides the output local clock signal into two paths of signals, one path of signal is transmitted to the frequency measurement module, the frequency measurement module accurately tests the frequency of the output local clock signal of the tested device, and the frequency information is sent to the main control unit through a data bus;
the other path of signal is used as an input signal and transmitted to a pilot frequency clock common time base closed-loop control loop; meanwhile, according to the technical characteristics of an external reference clock of the test instrument, the upper computer sends clock signal frequency information meeting the requirements of the test instrument to a main control unit of the device through a standard bus;
the main control unit sends the frequency information of the input and output clock signals of the device to a pilot frequency clock common-time-base closed-loop control loop through a data bus, realizes the generation of frequency division ratio numbers or frequency multiplication times and signals of a digital frequency synthesizer through the loading and configuration of a programmable self-adaptive algorithm according to the relationship between the two frequencies, achieves stable phase locking between the output signals and the input signals through the closed-loop control loops such as phase demodulation, filtering and the like, and finally realizes the clock signal output which is common-time-base with the input clock signals and meets the frequency requirements through a filter for signal conditioning.
Preferably, the high stability time base provides an internal reference clock for the operation of the functional units of the device.
The invention has the following beneficial effects:
the test instrument is not required to be subjected to adaptive change design according to related technical characteristics such as the frequency of a local clock output by a tested device, so that the common time base between the test instrument and the tested device during comprehensive and accurate test can be realized, and the test requirement of practical application is met to the maximum extent in a generalized mode;
the frequency of the local clock output by the tested device does not need to be limited specifically, and according to the frequency and other related technical characteristics of the local clock output by the tested device, the common time base with the clock can be realized quickly through the loading and configuration mode of the programmable self-adaptive algorithm, so that the accurate comprehensive test problems related to time sequence control, synchronization and the like are supported and solved, and the test requirements of practical application are met to the maximum extent in a generalized mode.
Drawings
Fig. 1 is a schematic block diagram of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made with reference to the accompanying drawings:
as shown in fig. 1, a common time base device suitable for comprehensive testing of local active clock working mode devices includes a power divider, an output end of the power divider is connected with a pilot frequency clock common time base closed-loop control loop and a frequency measurement module, an output end of the pilot frequency clock common time base closed-loop control loop is connected with a filter, the frequency measurement module and the pilot frequency clock common time base closed-loop control loop are connected with a main control unit through a data bus, the main control unit is connected with an interface circuit through a data bus, and the interface circuit is connected with an upper computer through a standard program control bus.
The pilot frequency clock common-time-base closed-loop control loop is realized based on a programmable gate array (FPGA) and comprises a digital phase discriminator, a digital loop filter and a digital frequency synthesizer which are connected in series, wherein the digital frequency synthesizer is connected with a high-stability time base for providing a unified internal reference clock, the output end of the digital frequency synthesizer is respectively connected with a frequency multiplier and a frequency divider, and the output ends of the frequency multiplier and the frequency divider are connected with the digital phase discriminator.
The common time base method suitable for the comprehensive test of the local active clock working mode device adopts the common time base device suitable for the comprehensive test of the local active clock working mode device, and specifically comprises the following steps:
after the output local clock signal of the tested device enters the device, the power divider divides the output local clock signal into two paths of signals, one path of signal is transmitted to the frequency measurement module, the frequency measurement module accurately tests the frequency of the output local clock signal of the tested device, and the frequency information is sent to the main control unit through a data bus;
the other path of signal is used as an input signal and transmitted to a pilot frequency clock common time base closed-loop control loop; meanwhile, according to the technical characteristics of an external reference clock of the test instrument, the upper computer sends clock signal frequency information meeting the requirements of the test instrument to a main control unit of the device through a standard bus;
the main control unit sends the frequency information of the input and output clock signals of the device to a pilot frequency clock common-time-base closed-loop control loop through a data bus, realizes the generation of frequency division ratio numbers or frequency multiplication times and signals of a digital frequency synthesizer through the loading and configuration of a programmable self-adaptive algorithm according to the relationship between the two frequencies, achieves stable phase locking between the output signals and the input signals through the closed-loop control loops such as phase demodulation, filtering and the like, and finally realizes the clock signal output which is common-time-base with the input clock signals and meets the frequency requirements through a filter for signal conditioning. Wherein the high-stability time base provides a working internal reference clock for each functional unit of the device.
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.
Claims (2)
1. A common time base device suitable for the comprehensive test of a local active clock working mode device is characterized by comprising a power divider, wherein the output end of the power divider is connected with a pilot frequency clock common time base closed loop control loop and a frequency measurement module, the pilot frequency clock common time base closed loop control loop is realized based on a programmable gate array and comprises a digital phase discriminator, a digital loop filter and a digital frequency synthesizer which are connected in series, the digital frequency synthesizer is connected with a high stable time base providing a unified internal reference clock, the output end of the digital frequency synthesizer is respectively connected with a frequency multiplier and a frequency divider, the output ends of the frequency multiplier and the frequency divider are both connected with the digital phase discriminator, the output end of the pilot frequency clock common time base closed loop control loop is connected with the filter, the frequency measurement module and the pilot frequency clock common time base closed loop control loop are connected with a main control unit through a data bus, and the main control unit, the interface circuit is connected with an upper computer through a standard program control bus;
after the output local clock signal of the tested device enters the device, the power divider divides the output local clock signal into two paths of signals, one path of signal is transmitted to the frequency measurement module, the frequency measurement module accurately tests the frequency of the output local clock signal of the tested device, and the frequency information is sent to the main control unit through a data bus;
the other path of signal is used as an input signal and transmitted to a pilot frequency clock common time base closed-loop control loop; meanwhile, according to the technical characteristics of an external reference clock of the test instrument, the upper computer sends clock signal frequency information meeting the requirements of the test instrument to a main control unit of the device through a standard bus;
the main control unit sends the frequency information of the output local clock signal of the tested device and the output clock signal of the device to a pilot frequency clock common-time-base closed-loop control loop through a data bus, frequency division ratio number or frequency multiplication number and the signal generation of a digital frequency synthesizer are realized through the loading and configuration of a programmable self-adaptive algorithm according to the relation between two frequencies, the stable phase locking between the output signal and the input signal is achieved through a phase demodulation and filtering closed-loop control loop, the signal conditioning is carried out through a filter, and finally the clock signal output which is common-time-base with the input clock signal and meets the frequency requirement is realized.
2. A co-clock based apparatus suitable for integrated testing of devices operating in local active clock modes of operation as claimed in claim 1 wherein the high stability time base provides an internal reference clock for operation of the functional units of the apparatus.
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| CN204498106U (en) * | 2015-02-26 | 2015-07-22 | 中兵宇丰通信科技（北京）有限公司 | A kind of frequency with output power function closes circuit |
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| US20090322311A1 (en) * | 2008-06-27 | 2009-12-31 | International Business Machines Corporation | Method and Apparatus for On-Chip Testing of High Speed Frequency Dividers |
| CN102315927A (en) * | 2011-06-30 | 2012-01-11 | 大唐移动通信设备有限公司 | Clock synchronization device and method |
| CN105049035B (en) * | 2015-07-16 | 2018-04-10 | 中国电子科技集团公司第四十一研究所 | A kind of multi-mode miniaturization Low phase noise broadband point frequency combiner circuit and method |
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| CN204498106U (en) * | 2015-02-26 | 2015-07-22 | 中兵宇丰通信科技（北京）有限公司 | A kind of frequency with output power function closes circuit |
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| Title |
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| 具有快速锁定时间的新型低相噪频率合成技术;魏福立等;《半导体技术》;20060531;全文 * |
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