CN107565959B - High-speed delay phase-locked loop - Google Patents
High-speed delay phase-locked loop Download PDFInfo
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Abstract
The invention relates to a high-speed delay phase-locked loop and an automatic frequency calibration method thereof, wherein the high-speed delay phase-locked loop comprises an automatic frequency calibration algorithm module, a delay unit chain, a four-frequency divider, a phase discriminator, a sampling circuit, a charge pump, a filter, a voltage regulator and a bias voltage generating circuit; the automatic frequency calibration algorithm module is used for obtaining a sampling result output by the sampling circuit; and setting an output voltage of the voltage regulator and an output of the bias voltage generating circuit; the delay unit chain is used for generating an input clock and a delay clock according to the output voltage of the voltage regulator, the delay control voltage of the filter and the high-speed clock; the four frequency divider is used for respectively dividing the input clock and the delay clock twice; the phase discriminator is used for phase discriminating the input clock and the delay clock after the speed reduction and outputting corresponding phase error signals to the charge pump; the charge pump is used for converting the phase error signal into a current signal, and the filter generates the delay control voltage according to the current signal.
Description
Technical Field
The invention belongs to the field of high-speed interface data transmission, and mainly relates to a high-speed delay phase-locked loop and an automatic frequency calibration method thereof, which are used for generating quadrature clocks in a high-speed interface circuit.
Background
With the development of submicron and ultra-deep submicron technologies, very large scale integrated circuits and system integration technologies are becoming mature, and the integration scale of chips is becoming larger and the working speed is also becoming faster, which makes the quality of on-chip clocks as an important component of chips more important. Because the unconditionally stable delay phase-locked loop has the characteristics of zero delay, low noise, low jitter and easy design, the unconditionally stable delay phase-locked loop is suitable for clock synchronization of large-scale high-speed chips. In recent years, a technique using a delay locked loop as a clock distribution has been widely used in chips such as a field programmable gate array and a microprocessor.
In high-speed interface circuits, quadrature clocks are often used to participate in clock data recovery. Implementations of generating quadrature clocks are frequency dividers, polyphase filters, etc. When the data rate is as high as tens or twenty gigabits per second (Gbps), it is difficult to implement a quadrature clock using the above method.
Disclosure of Invention
In order to overcome the difficulty of generating stable quadrature clocks in a high-speed interface circuit, the invention is realized by using a method of a high-speed delay phase-locked loop, and simultaneously provides an automatic frequency calibration method which is used for correctly selecting a delay frequency band of the high-speed delay phase-locked loop, selecting a proper frequency band suitable for the current application environment, and then performing loop locking through the closed-loop characteristic of the high-speed delay phase-locked loop so as to obtain stable quadrature clock output.
In order to achieve the above objective, in one aspect of the present invention, a high-speed delay phase locked loop is provided, which includes an automatic frequency calibration algorithm module, a delay cell chain, a four-frequency divider, a phase discriminator, a sampling circuit, a charge pump, a filter, a voltage regulator, and a bias voltage generating circuit; the automatic frequency calibration algorithm module is used for obtaining a sampling result output by the sampling circuit, wherein the sampling result comprises an input clock and a delay clock after frequency division by the four frequency dividers; and setting an output voltage of the voltage regulator and an output of the bias voltage generating circuit; a delay unit chain for generating an input clock and a delay clock according to an output voltage of the voltage regulator, a delay control voltage of the filter, and a high-speed clock; the four frequency divider is used for respectively dividing the input clock and the delay clock by two times, so that the speed reduction of the four frequency divisions is completed, and the speeds of the input clock and the delay clock are reduced to the speed which can be correctly processed by the phase discriminator; the phase discriminator is used for phase discriminating the input clock and the delay clock after the speed reduction and outputting corresponding phase error signals to the charge pump; and the charge pump is used for converting the phase error signal into a current signal, and the filter generates a delay control voltage according to the current signal.
Preferably, the delay unit chain adopts a multistage delay variable inverter to form a link, the delay time of the inverter is respectively regulated by the output voltage of the voltage regulator and the delay control voltage of the filter, the output voltage of the voltage regulator corresponds to coarse delay adjustment, and the delay control voltage of the filter corresponds to fine delay adjustment.
Preferably, the phase discriminator performs phase discrimination on the input clock and the delay clock after the speed reduction, judges whether the phase is advanced or retarded, and outputs a phase error signal to the charge pump.
Preferably, the charge pump converts the phase error signal output from the phase detector into an analog current amount, and outputs the analog current amount to a filter at a subsequent stage.
Preferably, the output of the voltage regulator is used as a power supply voltage of the delay cell chain, different power supply voltages correspond to delay frequency bands which are not communicated by the delay chain, and the delay frequency band suitable for the current input frequency is determined by selecting different power supply voltage values.
Preferably, the bias voltage generating circuit is configured to generate two high and low control voltages, VH and VL, during the automatic frequency calibration, and set the control voltages.
Preferably, the sampling circuit is used for mutually sampling the frequency-divided input clock and the delay clock so as to determine the sequence relationship of the two clocks, and outputting the sampling result to the automatic frequency calibration algorithm module for judgment so as to determine the selection of the frequency band.
In another aspect, an automatic frequency calibration method is provided, including the steps of: setting an output voltage of the voltage regulator and an output of the bias voltage generating circuit; acquiring sampling results of the input clock and the delay clock after the speed reduction; and selecting a delay frequency band required by the current input clock frequency according to the sampling result, and completing automatic frequency calibration.
The invention utilizes an automatic frequency calibration method to select the correct delay frequency band for the high-speed delay phase-locked loop, selects the proper frequency band suitable for the current application environment, and then performs loop locking through the closed-loop characteristic of the high-speed delay phase-locked loop so as to obtain stable quadrature clock output.
Drawings
FIG. 1 is a block diagram of the overall structure of a high-speed delay-locked loop of the present invention;
FIG. 2 is a schematic diagram of an automatic frequency calibration method according to the present invention;
FIG. 3 is a timing diagram of the automatic frequency calibration sampling result of 00 according to the present invention;
FIG. 4 is a timing diagram of the automatic frequency calibration sampling result of 01 according to the present invention;
fig. 5 is a timing diagram of the automatic frequency calibration sampling result of 11 according to the present invention.
Detailed Description
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Fig. 1 is a block diagram of the overall structure of the high-speed delay phase-locked loop of the present invention.
As shown in fig. 1, the high-speed delay locked loop includes: the automatic frequency calibration algorithm module, a delay unit chain, a four-frequency divider, a phase discriminator, a sampling circuit, a charge pump, a filter, a voltage regulator and a bias voltage generating circuit.
The automatic frequency calibration algorithm module is used for obtaining a sampling result output by the sampling circuit, wherein the sampling result comprises an input clock and a delay clock after frequency division by the four frequency dividers, and an output voltage of the voltage regulator and an output of the bias voltage generating circuit are set; the delay unit chain generates an input clock and a delay clock according to the output voltage of the voltage regulator, the delay control voltage of the filter and the high-speed clock; the input clock and the delay clock of the four frequency divider are divided twice and twice respectively, so that the speed reduction of the four frequency dividers is completed, and the speeds of the input clock and the delay clock are reduced to the speed which can be correctly processed by the phase discriminator; the phase discriminator performs phase discrimination on the input clock and the delay clock after the speed reduction, and outputs a corresponding phase error signal to the charge pump; the charge pump converts the phase error signal into a current signal and the filter generates a delay control voltage based on the current signal.
And the delay unit chain is formed by adopting a multistage delay variable inverter, the delay time of the inverter can be respectively regulated by a power supply voltage Vldo and a control voltage Vctrl, the power supply voltage Vldo corresponds to coarse delay adjustment, and the control voltage Vctrl corresponds to fine delay adjustment.
The quadrature clocks are extracted from the delay cell chain, clk_i and clk_q, respectively.
The four-frequency divider divides the input clock CLK_IN and the delay clock CLK_OUT by two times respectively, thereby completing the speed reduction of the four-frequency division and reducing the speeds of the input clock and the delay clock to the speed which can be correctly processed by the phase discriminator.
The phase discriminator is used for phase discrimination of the input clock CLK_In4 and the delay clock CLK_OUT4 after the speed reduction, judging whether the phase is advanced or retarded, and outputting a phase error signal UP/DOWN to the charge pump.
The charge pump converts the phase error signal UP/DOWN output by the phase discriminator into an analog current amount ICh and outputs the analog current amount ICh to a filter at a later stage.
And the filter is used for integrating the current signal output by the charge pump to obtain a stable voltage value, wherein the voltage is used as a delay control voltage Vctrl of the delay unit chain to determine the delay amount of the delay unit chain, and after Vctrl is stable, the quadrature clock can be taken out from the delay unit chain.
And a voltage regulator that outputs a power supply voltage Vldo as a delay cell chain, wherein different Vldos correspond to delay frequency bands for which the delay link is not in communication, and wherein the delay frequency band suitable for the current input frequency is determined by selecting different values of the Vldo.
And the bias voltage generating circuit is used for generating two high and low control voltages, namely VH and VL, in the automatic frequency calibration process and setting the control voltage Vctrl.
The sampling circuit is used for mutually sampling the frequency-divided input clock CLK_In4 and the delay clock CLK_OUT4 so as to determine the sequence relationship of the two clocks, and outputting the sampling result to the automatic frequency calibration algorithm for judgment so as to determine the selection of the frequency band.
The automatic frequency calibration algorithm module is used for setting the output voltage Vldo of the voltage regulator and the output of the bias voltage generating circuit, acquiring sampling results of the input clock and the delay clock after the speed is reduced, and selecting a delay frequency band required by the current input clock frequency according to the sampling results to complete the function of automatic frequency calibration.
The whole delay phase-locked loop comprises two loops, wherein the first loop is a frequency band selection loop and comprises a delay unit chain, a four frequency divider, a sampling circuit, a voltage regulator, a bias voltage generating circuit and an automatic frequency calibration algorithm module. The second loop is an analog closed-loop fine-tuning loop and comprises a delay unit chain, a four-frequency divider, a phase discriminator, a charge pump, a filter and a voltage regulator. The two loops share part of the modules and work sequentially.
FIG. 2 is a schematic diagram of an automatic frequency calibration method according to the present invention.
As shown in fig. 2, the band selection loop works first, executing on command of the automatic frequency calibration method. The frequency band with the highest frequency is selected first, that is, the output voltage of the voltage regulator is adjusted to the highest, and the delay unit chain corresponds to the shortest delay time. The high-speed clock CLK is processed by a delay unit chain to obtain an input clock CLK_IN and a delay clock CLK_OUT, and because the frequencies of the CLK_IN and the CLK_OUT are equal to the highest clock frequency, the phase discriminator is difficult to achieve the phase discrimination speed equivalent to the highest clock frequency, and therefore, the CLK_IN and the CLK_OUT are subjected to the same four-frequency division processing, so that the two clocks are subjected to the same four-frequency division channel to obtain four-frequency division clocks of the two clocks, namely CLK_In4 and CLK_OUT4. The bias voltage generating circuit is set to be high and low control voltages of VH and VL in sequence, and clock sampling values obtained when the control voltage Vctrl is equal to the high and low control voltages are recorded. The first cycle selects the highest frequency band and the resulting timing is shown in fig. 3. CLK_OUTH and CLK_OUTL correspond to CLK_OUTl output clocks under the condition that Vctrl is equal to VH and VL respectively, CLK_OU4H and CLK_OUTl correspond to CLK_OUTl output clocks after four frequency division respectively, and as the frequency band is the highest frequency sub-band, the rising edge sampling result of CLK_OUT4H and CLK_OUT4L to CLK_IN4 is 0, and the sampling value corresponding to the frequency band is 00. Then, the frequency band number is reduced by 1, and the bias voltage generating circuit is again provided, so that the sampling result of the clock divided by four by clk_in and clk_out is obtained and stored IN the same manner. The traversal of all the frequency bands is completed according to the operation until the frequency band number is reduced to 0, and the circulation is stopped.
During the whole traversal process, the sampling results appear in the sequence of 00, 01 and 11, which correspond to the three cases of fig. 3, fig. 4 and fig. 5 respectively. The sampling results 00 and 11 indicate that the phase of the delay clock clk_out will lead or lag the input clock clk_in regardless of the control voltage IN the current frequency band, which indicates that the analog closed loop cannot be locked within the target delay range, and the control voltage Vctrl will exceed the voltage range defined by the highest voltage VH and the lowest voltage VL. Therefore, the frequency band with the sampling result of 01 is the target sub-band, IN which the control voltage does not exceed the preset range, and the delay of clk_out by exactly one period relative to clk_in after the analog closed-loop locking can be ensured.
After the band selection loop is completed, the output voltage Vldo of the voltage regulator is determined, at which point it can be switched to analog closed-loop fine-tuning loop operation, which relies solely on the closed-loop stability characteristics of the analog circuit to lock the control voltage Vctrl. The phase discriminator compares the phase error of the four frequency division clocks CLK_In4 and CLK_OUT4 to obtain leading and lagging digital signals UP/DOWN, controls the charge pump to convert the digital signals into analog current, obtains a stable control voltage through the integral characteristic of the filter to delay the delay unit chain, and completes the whole generation process of the quadrature clock.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (8)
1. A high-speed delay locked loop, comprising:
the input end of the automatic frequency calibration algorithm module is electrically connected with the output end of the sampling circuit, the output end of the automatic frequency calibration algorithm module is electrically connected with the input end of the voltage regulator, and the automatic frequency calibration algorithm module is used for controlling the output voltage of the voltage regulator and the output voltage of the bias voltage generating circuit according to the sampling result after receiving the sampling result output by the sampling circuit; the sampling result comprises a slowed input clock and a delayed clock which are output by the four frequency dividers;
the output end of the bias voltage generating circuit is electrically connected with the output end of the filter and is used for setting the delay control voltage of the filter to generate a high-speed clock;
a delay unit chain, the input end of which is electrically connected with the output end of the voltage regulator and the output end of the filter, and is used for receiving the output voltage of the voltage regulator, the delay control voltage of the filter and the high-speed clock of the bias voltage generating circuit, and generating an input clock and a delay clock according to the output voltage of the voltage regulator, the delay control voltage of the filter and the high-speed clock of the bias voltage generating circuit;
the input end of the four frequency dividers is electrically connected with the output end of the delay unit chain, the output end of the four frequency dividers is electrically connected with the input end of the sampling circuit and the input end of the phase discriminator, and the four frequency dividers are used for respectively carrying out frequency division on the input clock and the delay clock twice, so that the speeds of the input clock and the delay clock are reduced;
the input end of the phase discriminator is electrically connected with the output end of the four frequency divider and is used for phase discriminating the input clock after the speed reduction and the delay clock to obtain a phase error signal;
the input end of the charge pump is electrically connected with the input end of the phase discriminator and is used for converting the phase error signal into a current signal;
and the output end of the filter is electrically connected with the input end of the delay unit chain and is used for generating the delay control voltage according to the current signal.
2. A high speed delay locked loop as claimed in claim 1, wherein said chain of delay cells comprises a chain of multi-stage delay variable inverters whose delay times are respectively adjusted by an output voltage of said voltage regulator corresponding to a coarse delay adjustment and a delay control voltage of said filter corresponding to a fine delay adjustment.
3. The high-speed delay locked loop of claim 1, wherein the phase detector phase-checks the input clock and the delay clock after the deceleration to determine whether the phase is leading or lagging, and outputs a phase error signal to the charge pump.
4. A high speed delay locked loop as claimed in claim 1, wherein the charge pump converts the phase error signal output from the phase detector into an analog current amount and outputs the analog current amount to a filter at a subsequent stage.
5. A high speed delay locked loop as claimed in claim 1, wherein the output of the voltage regulator is used as a supply voltage for a chain of delay cells, different supply voltages corresponding to delay bands for which the delay chain is not open, the delay bands being determined by selecting different supply voltage values.
6. The high-speed delay locked loop of claim 1, wherein the bias voltage generating circuit is configured to generate two high and low control voltages, VH and VL, during the automatic frequency calibration process, the control voltages being set.
7. The high-speed delay locked loop of claim 1 wherein the sampling circuit is configured to sample the divided input clock and the delay clock to determine a relationship between the two clocks, and output a sampling result to the automatic frequency calibration algorithm module for determination, thereby determining a selection of the frequency band.
8. An automatic frequency calibration method applied to the high-speed delay locked loop as claimed in claim 1, comprising the steps of:
setting an output voltage of the voltage regulator and an output of the bias voltage generating circuit;
acquiring sampling results of the input clock and the delay clock after the speed reduction;
and selecting a delay frequency band required by the current input clock frequency according to the sampling result, and completing automatic frequency calibration.
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| TW531966B (en) * | 2002-05-20 | 2003-05-11 | Mediatek Inc | Phase lock loop with low static state phase error and calibration circuit |
| CN101305519A (en) * | 2005-11-11 | 2008-11-12 | Nxp股份有限公司 | Integrating analog to digital converter |
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| KR20120025660A (en) * | 2010-09-07 | 2012-03-16 | 한국전자통신연구원 | Phase locked loop circuit including automatic frequency control circuit and operating method thereof |
| CN102299709A (en) * | 2011-04-27 | 2011-12-28 | 广州润芯信息技术有限公司 | High precision pulse width comparator based on time-to-digit conversion |
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