CN107565017B - Resistive random access memory based on stannous halide - Google Patents
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Abstract
The invention provides a stannous halide-based resistive random access memory and a preparation method thereof, wherein the specific structure of the resistive random access memory is a sandwich structure, FTO (fluorine-doped tin oxide), ITO (indium tin oxide) or ZTO (zinc oxide) is used as a substrate and a bottom electrode, a stannous halide film is used as a resistive layer, and Pt, Au and W are used as top electrodes. The invention adopts a novel stannous halide with a resistance change function material, and has the characteristics of simple components, easy film formation and stable performance. The resistive random access memory unit prepared by taking stannous halide as the resistive layer has the characteristics of large ratio window of high and low resistance states, stable electrical property, simple preparation process, low cost, safety, reliability and no environmental pollution. The resistance-change material has good cycle tolerance and still has good resistance-change performance after repeated erasing and writing. The invention has better development potential and application value.
Description
Technical Field
The invention belongs to the technical field of electronic materials and components, relates to an information storage technology, and particularly relates to a stannous halide-based resistive random access memory unit and a preparation method thereof.
Background
The semiconductor memory is one of the most important technologies in the integrated circuit industry, is widely applied to various fields of information, social security, aerospace, military and national defense, new energy and scientific research, and is an important embodiment of national competitiveness. The nonvolatile memory in the semiconductor memory is mainly a Flash memory (Flash) memory with a floating gate structure, floating gate Flash has not changed greatly in recent 30 years, and the evolution is mainly reflected in the reduction of characteristic size. The characteristic size of the current flash memory is reduced to be below 16nm, continuous reduction faces to a plurality of limitations on physical limit, the size is difficult to continuously reduce, meanwhile, a planar integrated architecture is difficult to further improve storage density to meet the requirements of the memory in big data era, a novel storage technology based on a new material, a new structure, a new principle and a new integrated architecture becomes a trend of future high-density storage development, a Resistive Random Access Memory (RRAM) is one of representative candidate technologies capable of solving the bottleneck of the traditional polycrystalline silicon floating gate technology, the resistive random access memory realizes storage through reversible transformation of material resistance, and compared with the traditional flash memory, the resistive random access memory has obvious advantages, including simple device structure, small unit size, good micro-scalability, high operation speed, low power consumption, compatibility with a CMOS (complementary metal oxide semiconductor transistor) process, easiness in three-dimensional integration and the like, and becomes an important.
The inorganic dielectric materials that can undergo resistance transition behavior are very diverse, and can be roughly classified into the following categories: binary oxides, ternary and multicomponent oxides, chalcogenic solid electrolytes, nitrides and other inorganic materials. The binary oxide has the advantages of simple structure, easily controlled material components, compatible preparation process and semiconductor process and the like, but generally needs a larger initial voltage to form a conductive channel in the resistance change layer, thereby increasing the power consumption and the complexity of a peripheral circuit. The preparation process of ternary and multi-element oxide materials is complex, the component proportion is difficult to control and is incompatible with the current CMOS process, so that the research on the resistance change device based on the multi-element metal oxide is mostly carried out in a laboratory, and the application prospect of the materials in the industrial field is not clear. The chalcogenide solid electrolyte material is used as an excellent fast ion conductor material of Ag and Cu ions, has great advantages in the aspect of researching the resistance transition mechanism of a PMC device, and is still a common dielectric material for researching the resistance transition behavior in a laboratory. Other inorganic materials are commonly nitride, amorphous carbon, amorphous silicon and the like, and also have the problems of complex process, high preparation cost and the like. In order to realize the industrial application requirements, in addition to good resistance change performance, the economic cost of various material preparation technologies is also a factor which must be considered. Therefore, the significance of finding a new resistance change layer material which has the characteristics of simple structure, easy control of material components, simple preparation process, low cost and good resistance change performance is important.
Disclosure of Invention
In view of the above existing problems, the present invention provides a resistive random access memory unit based on a stannous halide film as a resistive layer and a method for manufacturing the same, wherein the stannous halide has high resistivity, high chemical stability and low price, so that the resistive random access memory unit has a large storage window value, high electrical stability and low cost, and a manufacturing process is simple, and thus the stannous halide is a resistive layer material with great development potential and research value.
A resistive random access memory based on stannous halide sequentially comprises a transparent conductive glass substrate, a bottom electrode, a resistive layer and a top electrode from bottom to top, wherein the transparent conductive glass is made of FTO (fluorine-doped tin oxide), ITO (indium tin oxide) or ZTO (zero oxide), and the bottom electrode is a conductive film and is a common electrode of the resistive random access memory.
The resistance-change layer is a stannous halide film, the thickness of the resistance-change layer is 50-300 nm, the resistance-change layer is composed of one or more units, one end of each unit is connected with the top electrode, and the other end of each unit is connected with the bottom electrode.
The top electrode is an Au film, a Pt film or a W film, the thickness of the top electrode is 50-300 nm, the top electrode is composed of a plurality of top electrode units, one end of each top electrode unit floats, and the other end of each top electrode unit is connected with the corresponding resistance change layer unit.
The stannous halide is SnI2Or is SnBr2Or is SnF2。
The resistive random access memory based on stannous halide is characterized in that the unit size of the upper layer does not exceed the unit size of the lower layer.
The preparation method of the resistive random access memory unit comprises the following steps:
1) cleaning a substrate: respectively cleaning the FTO for 15-30 minutes by using deionized water, acetone and absolute ethyl alcohol in an ultrasonic instrument;
2) preparing a resistance change layer, namely preparing a stannous halide film on a cleaned substrate by utilizing physical vapor deposition or chemical vapor deposition or a solution coating method to prepare a single unit or dividing the stannous halide film into a plurality of units by utilizing a mask;
3) preparing a top electrode: and depositing a top electrode of an Au thin film, a Pt thin film or a W thin film on the resistance change layer thin film by a magnetron sputtering method, and dividing the top electrode into a plurality of units by using a mask.
The physical vapor deposition comprises an evaporation method, a sputtering method and an ion coating method, the chemical vapor deposition comprises atmospheric pressure chemical vapor deposition and low pressure chemical vapor deposition, and the solution coating method comprises a solution spin coating method and a sol-gel method.
And carrying out I-V test on the prepared resistive random access memory unit based on stannous halide. The device test is carried out on an Agilent B1500A semiconductor parameter analyzer test platform, one probe is pressed on the surface of the bottom electrode, and the other probe is pressed on the surface of the top electrode. And then, setting a scanning voltage of-6V to +6V by using Agilent B1500A test software, and adopting a current limiting measure to limit the current to 10mA so as to prevent the device from being broken down. One cycle of the scanning voltage work is divided into four parts, namely scanning from 0V to +6V, then scanning from +6V to 0V, then scanning from 0V to-6V, and finally scanning from-6V to 0V, namely, one cycle is completed, the scanning step number of each part is 101, namely, the current is taken at 101 points when the voltage is scanned from 0V to +6V, as shown in figure 4. The endurance test is to perform the above-mentioned scanning voltage cycle continuously for many times, and then obtain the distribution of the high and low resistance states of the device when the read voltage is 0.18V, as shown in fig. 5.
The results of these analyses are shown in the figures, respectively.
The advantages and the characteristics of the invention are as follows:
(1) the invention adopts a brand new stannous halide material which is different from the known resistance change layer material as the resistance change layer, and has the characteristics of novel material, simple components, stable performance and low cost. The invention has larger storage window value, high electrical stability and low cost. Therefore, the invention has great development potential and application value.
(2) The invention adopts stannous halide material as the resistance change layer, and the device does not need electric initialization process during operation.
(3) According to the invention, a stannous halide material is used as the resistance change layer, and the stannous halide has the characteristics of easiness in film formation and no pollution, so that the preparation process is simple and environment-friendly.
(4) The resistive random access memory unit device prepared by taking stannous halide as the resistive layer has good cycle tolerance and still has good resistive performance after repeated erasing and writing.
Drawings
FIG. 1 is a schematic diagram of a resistive random access memory unit based on stannous halide;
FIG. 2 is an I-V test chart of a resistive random access memory unit based on stannous halide;
FIG. 3 is a stannous halide-based resistive random access memory unit cycle tolerance test chart;
reference numerals: 1-top electrode, 2-resistance change layer, 3-bottom electrode, 4-transparent glass substrate
Detailed Description
The present invention will be described in further detail with reference to examples.
A resistive random access memory based on stannous halide film as a resistive layer mainly comprises a top electrode, a resistive layer and a bottom electrode, wherein the resistive layer is prepared by a solution spin coating method in the following examples, which are only used for illustrating the invention and are not used for limiting the scope of the invention.
Wherein Pt is adopted as a top electrode material, the top electrode is composed of a plurality of units, each unit is circular in shape, the diameter is 200 mu m, and the thickness is 150 nm; FTO is used as a bottom electrode material, is square and is a single unit, and the side length of the unit is 2cm and the thickness of the unit is 250 nm; stannous halide is used as a resistance change layer material, the shape of the resistance change layer material is rectangular, the resistance change layer material is a single unit, the thickness of the resistance change layer material is 200nm, and the size of the resistance change layer material is slightly smaller than that of a bottom electrode.
Example 1:
step 1. cleaning a substrate
Respectively cleaning the FTO for 30 minutes in an ultrasonic instrument by using deionized water, acetone and absolute ethyl alcohol;
step 2. reserve the electrode
Attaching an insulating adhesive tape with the width of 2mm to one side of the FTO conductive layer, and then irradiating the surface of the FTO with ultraviolet light in a UV cleaning instrument for 30 minutes;
step 3. preparing stannous iodide solution
0.372g of stannous iodide powder is prepared and dissolved in 1ml of dimethyl sulfoxide, and then the mixture is filtered by a 0.45 mu m filter head;
step 4. spin coating and drying
And spin-coating the stannous iodide solution on the surface of the FTO by using a spin coater at a rotating speed of 3000r/min for 30 seconds. Drying at 70 ℃ for 30 minutes;
step 5, preparing a top electrode
And (4) placing the substrate in the step (4) in a magnetron sputtering device, and depositing a top electrode with the diameter of 200 mu m and the thickness of 150nm on the surface of the stannous iodide film by using a direct-current magnetron sputtering deposition method and a mask plate with the aperture of 200 mu m to obtain the stannous iodide-based resistive random access memory.
And 6, removing the insulating tape to expose the bottom electrode so as to carry out testing.
And carrying out I-V test on the prepared resistive random access memory based on stannous iodide. The device is tested on an Agilent B1500A semiconductor parameter analyzer test platform, one probe is pressed on the surface of the bottom electrode FTO, and the other probe is pressed on the surface of the top electrode. And then, setting a scanning voltage of-6V to +6V by using Agilent B1500A test software, and adopting a current limiting measure to limit the current to 10mA so as to prevent the device from being broken down. A cycle of the scanning voltage work is divided into four parts, namely scanning from 0V to +6V, then scanning from +6V to 0V, then scanning from 0V to-6V, and finally scanning from-6V to 0V, namely, a cycle is completed, the scanning step number of each part is 101, namely, the current is taken as 101 points when the voltage is scanned from 0V to + 6V. And the tolerance test is to circularly and continuously carry out the scanning voltage for multiple times, and then read the high and low resistance values of the device when the voltage is 0.18V to obtain the high and low resistance state distribution of the device.
Example 2:
step 1. cleaning a substrate
Respectively cleaning the FTO for 30 minutes in an ultrasonic instrument by using deionized water, acetone and absolute ethyl alcohol;
step 2. reserve the electrode
Attaching an insulating adhesive tape with the width of 2mm to one side of the FTO conductive layer, and then irradiating the surface of the FTO with ultraviolet light in a UV cleaning instrument for 30 minutes;
step 3. preparing stannous bromide solution
0.278g of stannous bromide powder is dissolved in 1ml of dimethyl sulfoxide, and then the solution is filtered by a 0.45-micron filter head;
step 4. spin coating and drying
And (3) spin-coating the stannous bromide solution to the surface of the FTO by using a spin coater at the rotating speed of 3000r/min for 30 seconds. Drying at 70 ℃ for 30 minutes;
step 5, preparing a top electrode
And (4) placing the substrate in the step (4) in a magnetron sputtering device, and depositing a top electrode with the diameter of 200 mu m and the thickness of 150nm on the surface of the stannous bromide film by using a direct-current magnetron sputtering deposition method and a mask with the aperture of 200 mu m to obtain the stannous bromide-based resistive random access memory unit.
And 6, removing the insulating tape to expose the bottom electrode so as to carry out testing.
And carrying out I-V test on the prepared resistive random access memory based on stannous bromide. The device is tested on an Agilent B1500A semiconductor parameter analyzer test platform, one probe is pressed on the surface of the bottom electrode FTO, and the other probe is pressed on the surface of the top electrode. And then, setting a scanning voltage of-6V to +6V by using Agilent B1500A test software, and adopting a current limiting measure to limit the current to 10mA so as to prevent the device from being broken down. A cycle of the scanning voltage work is divided into four parts, namely scanning from 0V to +6V, then scanning from +6V to 0V, then scanning from 0V to-6V, and finally scanning from-6V to 0V, namely, a cycle is completed, the scanning step number of each part is 101, namely, the current is taken as 101 points when the voltage is scanned from 0V to + 6V. And the tolerance test is to circularly and continuously carry out the scanning voltage for multiple times, and then read the high and low resistance values of the device when the voltage is 0.18V to obtain the high and low resistance state distribution of the device.
Example 3:
step 1. cleaning a substrate
Respectively cleaning the FTO for 30 minutes in an ultrasonic instrument by using deionized water, acetone and absolute ethyl alcohol;
step 2. reserve the electrode
Attaching an insulating adhesive tape with the width of 2mm to one side of the FTO conductive layer, and then irradiating the surface of the FTO with ultraviolet light in a UV cleaning instrument for 30 minutes;
step 3. preparing stannous chloride solution
0.450g of stannous chloride powder is prepared and dissolved in 1ml of dimethyl sulfoxide, and then the filtration is carried out by using a 0.45 mu m filter head;
step 4. spin coating and drying
The stannous chloride solution was spin coated on the FTO surface using a spin coater at 3000r/min for 30 seconds. Drying at 35 deg.C for 30 min;
step 5, preparing a top electrode
And (3) placing the substrate in a magnetron sputtering device, and depositing a top electrode with the diameter of 200 mu m and the thickness of 150nm on the surface of the stannous chloride film by using a direct-current magnetron sputtering deposition method and a mask plate with the aperture of 200 mu m to obtain the stannous chloride-based resistive random access memory unit.
And 6, removing the insulating tape to expose the bottom electrode so as to carry out testing.
And carrying out I-V test on the prepared resistive random access memory based on stannous chloride. The device is tested on an Agilent B1500A semiconductor parameter analyzer test platform, one probe is pressed on the surface of the bottom electrode FTO, and the other probe is pressed on the surface of the top electrode. And then, setting a scanning voltage of-6V to +6V by using Agilent B1500A test software, and adopting a current limiting measure to limit the current to 10mA so as to prevent the device from being broken down. A cycle of the scanning voltage work is divided into four parts, namely scanning from 0V to +6V, then scanning from +6V to 0V, then scanning from 0V to-6V, and finally scanning from-6V to 0V, namely, a cycle is completed, the scanning step number of each part is 101, namely, the current is taken as 101 points when the voltage is scanned from 0V to + 6V. And the tolerance test is to circularly and continuously carry out the scanning voltage for multiple times, and then read the high and low resistance values of the device when the voltage is 0.18V to obtain the high and low resistance state distribution of the device.
Example 4:
step 1. cleaning a substrate
Respectively cleaning the FTO for 30 minutes in an ultrasonic instrument by using deionized water, acetone and absolute ethyl alcohol;
step 2. reserve the electrode
Attaching an insulating adhesive tape with the width of 2mm to one side of the FTO conductive layer, and then irradiating the surface of the FTO with ultraviolet light in a UV cleaning instrument for 30 minutes;
step 3. preparing stannous fluoride solution
0.314g of stannous fluoride powder is prepared and dissolved in 1ml of dimethyl sulfoxide, and then the filtration is carried out by using a 0.45 mu m filter head;
step 4. spin coating and drying
And spin-coating the stannous fluoride solution on the surface of the FTO by using a spin coater at a rotating speed of 3000r/min for 30 seconds. Drying at 70 ℃ for 30 minutes;
step 5, preparing a top electrode
And (4) placing the substrate in the step (4) in a magnetron sputtering device, and depositing a top electrode with the diameter of 200 mu m and the thickness of 150nm on the surface of the stannous fluoride film by using a direct-current magnetron sputtering deposition method and a mask with the aperture of 200 mu m to obtain the stannous fluoride-based resistive random access memory.
And 6, removing the insulating tape to expose the bottom electrode so as to carry out testing.
And carrying out I-V test on the prepared resistive random access memory based on stannous fluoride. The device is tested on an Agilent B1500A semiconductor parameter analyzer test platform, one probe is pressed on the surface of the bottom electrode FTO, and the other probe is pressed on the surface of the top electrode. And then, setting a scanning voltage of-6V to +6V by using Agilent B1500A test software, and adopting a current limiting measure to limit the current to 10mA so as to prevent the device from being broken down. A cycle of the scanning voltage work is divided into four parts, namely scanning from 0V to +6V, then scanning from +6V to 0V, then scanning from 0V to-6V, and finally scanning from-6V to 0V, namely, a cycle is completed, the scanning step number of each part is 101, namely, the current is taken as 101 points when the voltage is scanned from 0V to + 6V. And the tolerance test is to circularly and continuously carry out the scanning voltage for multiple times, and then read the high and low resistance values of the device when the voltage is 0.18V to obtain the high and low resistance state distribution of the device.
Claims (3)
1. A resistive random access memory based on stannous halide sequentially comprises a transparent conductive glass substrate, a bottom electrode, a resistive layer and a top electrode from bottom to top, and is characterized in that
The transparent conductive glass is made of FTO (fluorine-doped tin oxide), ITO (indium tin oxide) or ZTO (zero oxide), and the bottom electrode is a conductive film and is a common electrode of the resistive random access memory;
the resistance-change layer is a stannous halide film, the thickness of the resistance-change layer is 50-300 nm, the resistance-change layer is composed of one or more units, one end of each unit is connected with the top electrode, and the other end of each unit is connected with the bottom electrode;
the top electrode is an Au, Pt or W film, the thickness of the top electrode is 50-300 nm, the top electrode is composed of a plurality of top electrode units, one end of each top electrode unit floats, and the other end of each top electrode unit is connected with the corresponding resistance change layer unit;
the stannous halide is SnI2Or is SnBr2Or is SnF2。
2. The method for preparing the resistive random access memory based on the stannous halide according to claim 1, comprising the following steps of:
1) cleaning a substrate: respectively cleaning glass substrates on which FTO (fluorine-doped tin oxide), ITO (indium tin oxide) or ZTO (zinc tin oxide) grows for 15-30 minutes by using deionized water, acetone and absolute ethyl alcohol in an ultrasonic instrument;
2) preparing a resistance change layer, namely preparing a stannous halide film on a cleaned substrate by utilizing physical vapor deposition or chemical vapor deposition or a solution coating method to prepare a single unit or dividing the stannous halide film into a plurality of units by utilizing a mask;
3) preparing a top electrode: depositing a top electrode of an Au film, a Pt film or a W film on the resistance change layer film by a magnetron sputtering method, and dividing the top electrode into a plurality of units by using a mask;
the stannous halide is SnI2Or is SnBr2Or is SnF2。
3. The method for preparing a resistive random access memory based on stannous halide according to claim 2, wherein in the step 2), the physical vapor deposition comprises an evaporation method, a sputtering method and an ion plating method, the chemical vapor deposition comprises atmospheric pressure chemical vapor deposition and low pressure chemical vapor deposition, and the solution plating method comprises a solution spin coating method and a sol-gel method.
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