CN107564952B - Power semiconductor - Google Patents
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- CN107564952B CN107564952B CN201610502531.XA CN201610502531A CN107564952B CN 107564952 B CN107564952 B CN 107564952B CN 201610502531 A CN201610502531 A CN 201610502531A CN 107564952 B CN107564952 B CN 107564952B
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Abstract
A power semiconductor, comprising: a substrate; a first conductive region formed in the substrate, the first conductive region having a source region of a first conductivity type formed therein; the gate oxide layer is formed on one surface of the substrate and is in contact with the source region, wherein the gate oxide layer has various thicknesses, and the thickness of the gate oxide layer shows a gradually increasing trend along with the increase of the distance between the gate oxide layer and the first conductive region; and a polysilicon layer formed on the gate oxide layer. Compared with the conventional power semiconductor, the power semiconductor is smoother, and the process (mark alignment, photoetching, etching and the like) difficulty is effectively reduced, so that the performance of the power semiconductor device and the reliability of a chip packaging function are improved.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a power semiconductor.
Background
The power semiconductor is the basis of power electronic technology and its application device, and is the main source for promoting the development of power electronic converter. Power semiconductors are in the heart of modern power electronic converters and play a significant role in device reliability, cost and performance. The common thyristor, the gate turn-off thyristor and the Insulated Gate Bipolar Transistor (IGBT) are successively called development platforms of power semiconductor devices.
The thickness of the gate oxide layer of a (planar) gate-controlled power semiconductor device, such as an IGBT, has a direct influence on the magnitude of the gate capacitance, which in turn affects the threshold voltage and the switching characteristics of the overall power semiconductor device. In order to reduce the gate capacitance, the prior art generally adopts a mode of increasing the thickness of a gate oxide layer. While if the threshold voltage is considered at the same time, it is required that the thickness of the gate oxide layer needs an optimal compromise. However, the optimal compromise of the thickness of the gate oxide layer adopted by the existing power semiconductor device causes the surface of the gate oxide layer to be uneven and is easy to cause the surface topography of the gate oxide layer to be discontinuous.
Disclosure of Invention
To solve the above problems, the present invention provides a power semiconductor including:
a substrate;
a first conductive region formed in the substrate, the first conductive region having a source region of a first conductivity type formed therein;
a gate oxide layer formed on a surface of the substrate, the gate oxide layer contacting the source region, wherein the gate oxide layer has a plurality of thicknesses, and the thickness of the gate oxide layer shows a gradually increasing trend along with the distance from the first conductive region;
and a polysilicon layer formed on the gate oxide layer.
According to one embodiment of the invention, the thickness of the gate oxide layer at the thickest position is more than 8 times the thickness of the gate oxide layer at the thinnest position.
According to one embodiment of the invention, the first conductive region comprises:
an enhanced charge carrier layer formed in the substrate;
a P-base layer having a second conductivity type formed in the enhanced charge carrier layer;
a source region and an ohmic contact region having a second conductivity type formed in the P-based layer, wherein the ohmic contact region is located at a middle position of the first conductive region.
According to an embodiment of the invention, a thickness of the ohmic contact region is larger than a thickness of the source region.
According to one embodiment of the invention, the thickness of the polysilicon layer is equal at each location.
According to an embodiment of the present invention, a thickness of the gate oxide layer increases linearly with increasing distance from the first conductive region.
According to one embodiment of the present invention, the gate oxide layer includes a plurality of layer segments connected in sequence, wherein,
each odd-numbered interval in the multiple intervals is a flat interval, and each even-numbered interval is an inclined interval; or the like, or, alternatively,
each odd-numbered interval in the multiple intervals is an inclined interval, and each even-numbered interval is a flat interval;
the flat layer section is a layer section with the thickness of each position kept unchanged, and the inclined layer section is a layer section with the thickness linearly increased.
According to one embodiment of the invention, the gate oxide layer comprises a plurality of layer segments connected in sequence, wherein the plurality of layer segments form a stepped structure, wherein the greater the distance from the first conductive region, the greater the thickness of the layer segment.
According to one embodiment of the invention, the layer segment furthest away from the source region is removed, and the sum of the lengths of the remaining layer segments is twice larger than the half-cell width of the power semiconductor.
According to an embodiment of the invention, the power semiconductor further comprises:
a buffer layer formed on the other surface of the substrate;
a collector region formed on the buffer layer.
According to an embodiment of the present invention, the power semiconductor further includes a short-circuit point formed at the collector region.
The gate oxide layer in the power semiconductor provided by the invention is linearly changed, so that the defects of high convex and discontinuous device surface of the conventional power semiconductor can be effectively avoided. Compared with the conventional power semiconductor, the power semiconductor is smoother, and the process (mark alignment, photoetching, etching and the like) difficulty is effectively reduced, so that the performance of the power semiconductor device and the reliability of the chip packaging function are improved.
The gate oxide layer of the power semiconductor can be manufactured by adopting standard photoetching and etching processes, and special photoetching and etching processes do not need to be additionally developed aiming at the stepped gate structure, so that the process development cost can be saved. Meanwhile, the gate oxide layer is a relatively gentle structure formed by multiple times of step-by-step photoetching and etching, so that single deep etching can be avoided, and the process difficulty is reduced.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The drawings illustrate various embodiments of aspects of the invention, and together with the description serve to explain the principles of the invention. Those skilled in the art will appreciate that the particular embodiments illustrated in the drawings are illustrative only and are not intended to limit the scope of the invention. It should be appreciated that in some examples, one element shown may also be designed as multiple elements, or multiple elements may also be designed as one element. In some examples, an element shown as an internal component of another element may also be implemented as an external component of the other element, and vice versa. In order that the exemplary embodiments of the present invention may be more clearly and specifically understood so that those skilled in the art may better understand the advantages of the various aspects of the present invention and their features, reference is now made to the accompanying drawings, in which:
fig. 1 is a schematic structural diagram of a conventional power semiconductor;
FIG. 2 is a schematic diagram of a power semiconductor half-cell structure according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of a power semiconductor half-cell structure according to one embodiment of the present invention;
FIG. 4 is a schematic diagram of a power semiconductor half-cell structure according to one embodiment of the present invention;
FIG. 5 is a schematic diagram of a power semiconductor half-cell structure according to one embodiment of the present invention;
FIG. 6 is a schematic diagram of a power semiconductor half-cell structure according to one embodiment of the present invention;
FIG. 7 is a schematic diagram of a power semiconductor half-cell structure according to one embodiment of the present invention;
fig. 8 and 9 are flow diagrams of fabricating the power semiconductor shown in fig. 7, according to one embodiment of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details or with other methods described herein.
Additionally, the steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions and, although a logical order is illustrated in the flow charts, in some cases, the steps illustrated or described may be performed in an order different than here.
As shown in fig. 1, for the conventional planar gate-controlled power semiconductor device, a trapezoidal design scheme is adopted for a gate oxide layer, and a thin gate oxide layer is arranged at a position close to a channel and a thick gate oxide layer is arranged at a position far away from the channel, so that the effects of reducing gate capacitance and optimizing the switching characteristic of the power semiconductor device are achieved, and meanwhile, the threshold voltage characteristic can be adjusted. However, how to design the ratio of the thin and thick gate oxide (the ratio of the packet length to the thickness) directly affects the size of the gate capacitance, and thus the optimal compromise between the switching characteristic and the threshold voltage characteristic. Moreover, most importantly, the design scheme of the existing gate oxide layer greatly affects the appearance of the surface of a device, and is easy to cause high convexity and discontinuity of the surface of the device, thereby affecting the flatness of the surface of the device. This not only increases the difficulty of device fabrication, but also affects device performance and chip package reliability.
Aiming at the problems in the prior art, the invention provides a novel power semiconductor, the thickness of a gate oxide layer of the power semiconductor is changed smoothly, so that the smoothness of the surface of the power semiconductor can be improved, the process difficulty of the gate oxide layer is reduced, and meanwhile, the performance of a chip and the packaging reliability can be improved.
In order to more clearly illustrate the structure and advantages of the power semiconductor provided by the present invention, the power semiconductor provided by the present invention is further described below with reference to different embodiments, and since the structure of the power semiconductor provided by the present invention is symmetrical, the following embodiments are all described in terms of a half-cell structure for the purpose of aspect description.
The first embodiment is as follows:
fig. 2 shows a schematic structural diagram of a half cell of the power semiconductor provided in this embodiment.
As shown in fig. 2, the power semiconductor provided by the present embodiment preferably includes: a substrate 201, a first conductive region, a gate oxide layer 202, and a polysilicon layer 203. In this embodiment, the first conductive region is formed in the substrate 201, and includes: an enhanced carrier layer 204 having a first conductivity type, a P-base layer 205 having a second conductivity type, a source region 206 having the first conductivity type, and an ohmic contact region 207 having the second conductivity type. In this embodiment, the conductivity type of the substrate 201 is the first conductivity type.
In this embodiment, enhancement carrier layer 204 is formed in substrate 201. In the process of fabricating the enhanced carrier layer 204, an oxide layer is first deposited on the substrate 201, and the thickness of the oxide layer is preferably not more than 0.5 μm, and then the formed oxide layer is etched, so as to fabricate an injection/doping window of the enhanced carrier layer 204. After obtaining the implantation/doping window of enhanced carrier layer 204, the implantation/doping window is utilizedThe substrate 201 is implanted/doped with an enhanced charge carrier layer, followed by high temperature drive/diffusion, to form an enhanced charge carrier layer 204 with a higher doping concentration than the substrate 201. In the present embodiment, the doping concentration of enhanced carrier layer 204 is preferably greater than 1e15/cm3。
After the enhanced charge carrier layer 204 is obtained, a P-base layer 205 needs to be further formed in the enhanced charge carrier layer 204. In this embodiment, since the thickness of the oxide layer is increased by the high-temperature propulsion process in the process of forming the enhanced carrier layer 204 by using the injection/doping window of the enhanced carrier layer 204, the oxide layer with the increased thickness needs to be etched first to form the injection/doping window of the P-base region.
After an implantation/doping window of the P-base region is formed, the window can be used to perform P-base region implantation/doping on the enhanced carrier layer 204, and then high-temperature propulsion/diffusion processing is performed, so that the P-base region 205 is formed in the enhanced carrier layer 204. In this embodiment, the doping concentration of the P-base region 205 is preferably e17/cm3Magnitude.
It should be noted that in other embodiments of the present invention, the doping concentration of enhancement carrier layer 204 and/or P-base region 205 may also be other reasonable values according to practical needs, and the present invention is not limited thereto.
Similarly, the source region 206 and the ohmic contact region 207 may be formed in the P-base region 205 by the same method, and the detailed forming process thereof is not described herein. In the present embodiment, the thickness of the ohmic contact region 207 is preferably greater than the thickness of the source region 206.
As shown in fig. 2, in the present embodiment, a gate oxide layer 202 is formed on a substrate 201, and one end of the gate oxide layer 202 near a source region 206 is in contact with the source region 206. A polysilicon layer 207 is formed on the gate oxide layer 202, the thickness of which at each location preferably remains constant.
In order to avoid the problems of large process difficulty and poor process uniformity control of the conventional power semiconductor due to overlarge thickness difference of the thin and thick parts of the gate oxide layer and the problems of high surface convexity and discontinuity of a power semiconductor device caused by the problem, the gate oxide layer of the power semiconductor provided by the embodiment adopts a novel mesa gate structure. Specifically, as shown in fig. 2, the gate oxide layer 202 has various thicknesses, and the thickness of the gate oxide layer increases linearly as the distance from the line in the first conductive region increases.
In the power semiconductor half-cell structure shown in fig. 2, the gate oxide layer 202 has a starting point (i.e., the left end point in the drawing) located above the source region 206 and an ending point (i.e., the right end point in the drawing) aligned with the cell edge. In this embodiment, the thickness of the gate oxide layer 202 is linearly increased from the starting point to the end point, and the thickness D of the gate oxide layer at the starting point is1Preferably of conventional thickness (e.g. 0.1 μm), the thickness D of the gate oxide layer at the end position2Preferably more than 10 times the thickness at the starting point (e.g. 1 μm).
It should be noted that in other embodiments of the present invention, the thickness of the gate oxide layer 202 at the starting position may be a reasonable thickness, and the thickness at the ending position may be other values larger than the thickness at the starting position (for example, the thickness of the gate oxide layer at the ending position is 8 times or more the thickness at the starting position), according to practical requirements, and the present invention is not limited thereto.
In this embodiment, after the source region 206 and the ohmic contact region 207 are formed, the gate oxide layer 202 and the polysilicon layer 203 may be formed. Specifically, in the present embodiment, a thickness D is first formed on the substrate 201 and the first conductive region2SiO of (2)2Layer, followed by multiple photolithography and etching, thereby making SiO2The thickness of the layer varies linearly.
To obtain SiO with the thickness linearly changing2After the layer, in the SiO2A polysilicon layer with a specific thickness is formed on the layer, and N-type polysilicon doping is carried out. In this embodiment, the polysilicon layer preferably has a thickness of less than 0.5 μm and a doping concentration of preferably 1e19/cm3The above. Of course, in other embodiments of the present invention, the thickness and the doping concentration of the polysilicon layer may be other reasonable values according to actual needs, and the present invention is not limited thereto.
After the above process is completed, in the present embodiment, a portion of SiO is covered on the ohmic contact region 207 and the source region 2062The layers and the polysilicon layer are subjected to photolithography or etching to finally form the power semiconductor structure as shown in fig. 2.
It should be noted that in other embodiments of the present invention, the material of the gate oxide layer may also be selected from other reasonable materials, and the present invention is not limited thereto. Meanwhile, it should be noted that in other embodiments of the present invention, the source region 206 and the ohmic contact region 207 are also fabricated after the gate oxide layer 202 and the polysilicon layer 203 are fabricated, and since the detailed fabrication process thereof is known by those skilled in the art from the foregoing description, it is not described herein again.
In this embodiment, the power semiconductor further comprises a buffer layer 208 having a first conductivity type and a collector region 209 having a second conductivity type. Wherein a buffer layer 208 is formed on the other surface of the substrate 201, which preferably includes a first buffer layer 208a and a second buffer layer 208 b. It should be noted that in other embodiments of the present invention, the buffer layer 208 may include only one layer or three or more layers, but the present invention is not limited thereto.
A collector region 209 is formed on the buffer layer 208, and as shown in fig. 2, in the present embodiment, a plurality of short-circuiting points 210 having the first conductivity type are formed in the collector region 209.
In this embodiment, in the process of fabricating the buffer layer 208, the collector region 209 and the short-circuit point 210, one or more N buffer layer structures are first formed on the surface of the substrate 201 by using high temperature (e.g., greater than 1000 ℃) diffusion or ion implantation + low temperature (e.g., less than 500 ℃) annealing, so as to obtain the buffer layer 208. Then, a P + collector region 209 is formed on the surface of the buffer layer 208 by high temperature diffusion or ion implantation + laser annealing. Finally, a number of N + shorting dots 210 are formed in the P + collector region 209, again by high temperature diffusion or ion implantation + laser annealing.
It should be noted that, in different embodiments of the present invention, for a power semiconductor with a thicker thickness, the order of the front surface process and the back surface process (i.e., the process for fabricating the buffer layer, the collector region, and the short circuit point) may be adjusted, that is, the front surface process may be performed first, or the front surface process may be performed first, and then the back surface process may be performed. For the power semiconductor needing to be thinned, the front surface process is required to be carried out firstly, and then the back surface process is required to be carried out, and a high-temperature process cannot be carried out in the back surface process.
As can be seen from the above description, the gate oxide layer in the power semiconductor provided by the present embodiment varies linearly, so that the defects of the conventional power semiconductor, such as high device surface convexity and discontinuity, can be effectively avoided. Compared with the conventional power semiconductor, the power semiconductor provided by the embodiment is smoother, and the process (mark alignment, photoetching, etching and the like) difficulty is effectively reduced, so that the performance of the power semiconductor device and the reliability of the chip packaging function are improved.
The gate oxide layer of the power semiconductor provided by the embodiment can be manufactured by adopting a standard photoetching and etching process, and a specific photoetching and etching process does not need to be additionally developed aiming at the stepped gate structure, so that the process development cost can be saved. Meanwhile, the gate oxide layer is a relatively gentle structure formed by multiple times of step-by-step photoetching and etching, so that single deep etching can be avoided, and the process difficulty is reduced.
Example two:
fig. 3 shows a schematic structural diagram of a power semiconductor half cell provided in this embodiment.
As can be seen from comparing fig. 2 and fig. 3, the power semiconductor provided in this embodiment is different from the power semiconductor provided in the first embodiment only in the gate oxide layer and the polysilicon layer, and therefore, for convenience of description, the above different points are highlighted, and only the gate oxide layer and the polysilicon layer of the power semiconductor in this embodiment are further described below.
As shown in fig. 3, in the present embodiment, the gate oxide layer includes two layer segments, i.e., a 1 st layer segment and a 2 nd layer segment. Wherein the projection lengths of the 1 st layer segment and the 2 nd layer segment on the substrate are respectively L1And L2. For the layer 1 segment, the thickness of the segment is kept constant with the distance from the line in the ohmic contact region, namely the thickness is always D1(ii) a And for the layer 2 segment, the thickness thereof is increased by D with the distance from the line in the ohmic contact region1Linear increase to D2。
Of course, in other embodiments of the present invention, the thickness of the gate oxide layer in the power semiconductor may be linearly increased and then kept constant as the distance from the line in the ohmic contact region is increased, i.e., the structure shown in fig. 4 is formed.
It should be noted that, for the power semiconductor shown in fig. 4, in order to avoid the large-thickness gate oxide layer occupying too large proportion, the length L of the 2 nd layer segment is larger2Preferably less than half the power semiconductor half-cell length to control the threshold voltage of the power semiconductor within a reasonable range.
Example three:
fig. 5 shows a schematic structural diagram of a power semiconductor half cell provided in this embodiment.
As can be seen from comparing fig. 2 and fig. 5, the power semiconductor provided in this embodiment is different from the power semiconductor provided in the first embodiment only in the gate oxide layer and the polysilicon layer, and therefore, for convenience of description, the above different points are highlighted, and only the gate oxide layer and the polysilicon layer of the power semiconductor in this embodiment are further described below.
As shown in fig. 5, in the present embodiment, the gate oxide layer includes three layer segments, i.e., a 1 st segment, a 2 nd segment, and a 3 rd segment. Wherein the projection lengths of the three layer segments on the substrate are L respectively1、L2And L3. For the layer 1 segment, the thickness is kept constant, i.e. the thickness is kept at D, with increasing line distance from the ohmic contact region1(ii) a For the layer-2 segment, the thickness is represented by D as the distance from the line in the ohmic contact region increases1Linear increase to D2(ii) a For the layer 3 segment, the thickness is kept constant, i.e. the thickness is kept at D, with increasing line distance from the ohmic contact region2。
It should be noted that in other embodiments of the present invention, the number n of the layer segments included in the gate oxide layer may also be other reasonable values, and the present invention is not limited thereto. For example, when the gate oxide layer comprises 7 layer segments, the structure of the power semiconductor will be as shown in fig. 6.
Meanwhile, it should be noted that, in order to avoid the large proportion of the gate oxide layer with large thickness, the length L of the last layer section (i.e. the nth layer section) is set to be too largenPreferably less than half the power semiconductor half-cell length L to control the threshold voltage of the power semiconductor within a reasonable range. Namely, the existence of:
L1+L2+...+Ln-1＜L/2
it should be noted that, when the gate oxide layer includes multiple layer segments, the odd-numbered layer segment in the multiple layer segments may be a flat layer segment (i.e., a layer segment whose thickness remains unchanged with increasing line distance from the ohmic contact region), the even-numbered layer segment may be an inclined layer segment (i.e., a layer segment whose thickness increases linearly with increasing line distance from the ohmic contact region), or the odd-numbered layer segment in the multiple layer segments may be an inclined layer segment and the even-numbered layer segment is a base layer segment, which is not limited in this respect.
Furthermore, the projected lengths thereof on the substrate are preferably equal for each of the plurality of layer segments, i.e. there is L1＝L2＝...＝LnAnd the slopes of the individual ramp segments are preferably equal.
Example four:
fig. 7 shows a schematic structural diagram of a power semiconductor half cell provided in this embodiment.
As can be seen from comparing fig. 2 and fig. 7, the power semiconductor provided in this embodiment is different from the power semiconductor provided in the first embodiment only in the gate oxide layer and the polysilicon layer, and therefore, for convenience of description, while highlighting the above difference, only the gate oxide layer and the polysilicon layer of the power semiconductor in this embodiment are further described below.
As shown in FIG. 7, in the present embodiment, the gate oxide layer includes four layer segments, i.e., the second layer1-th, 2-nd, 3-rd and 4-th intervals. Wherein, the four layer segments are all flat segments, and the respective projection lengths on the substrate are respectively L1、L2、L3And L4Thus, a stepped gate oxide structure is formed.
In this embodiment, the lengths of the plurality of layer segments included in the gate oxide layer are preferably equal to each other, i.e., L exists1＝L2＝L3＝L4。
It should be noted that in other embodiments of the present invention, the number of the layer segments included in the gate oxide layer may also be other reasonable numbers, and meanwhile, the lengths of the different layer segments may also be unequal, which is not limited in the present invention. Meanwhile, in order to avoid the overlarge proportion of the gate oxide layer with large thickness, the length of the last layer section of the gate oxide layer is preferably less than half of the length L of the half cell of the power semiconductor, so that the threshold voltage of the power semiconductor is controlled within a reasonable range.
In order to more conveniently understand the characteristics of the power semiconductor provided by the present embodiment, the following further describes the manufacturing process of the power semiconductor provided by the present embodiment.
Fig. 8 and 9 show a flowchart of manufacturing the power semiconductor shown in fig. 7 in the present embodiment.
In the present embodiment, as shown in fig. 8, an oxide layer is first deposited on the substrate 201, and the thickness of the oxide layer is preferably not more than 0.5 μm, and then the formed oxide layer is etched, so as to fabricate an injection/doping window of the enhanced carrier layer 204. After obtaining the injection/doping window of the enhanced carrier layer 204, the injection/doping window is utilized to inject/dope the enhanced carrier layer into the substrate 201, and then high temperature propulsion/diffusion is performed, so as to form the enhanced carrier layer 204 with a doping concentration higher than that of the substrate 201. In the present embodiment, the doping concentration of enhanced carrier layer 204 is preferably greater than 1e15/cm3。
After the enhanced charge carrier layer 204 is obtained, a P-base layer 205 needs to be further formed in the enhanced charge carrier layer 204. As shown in fig. 8, in the present embodiment, in the process of forming the enhanced carrier layer 204 by using the implantation/doping window of the enhanced carrier layer 204, the thickness of the oxide layer 211 is increased by the high-temperature driving process, so that the implantation/doping window made for forming the enhanced carrier layer 204 is covered by the oxide layer, and at this time, the oxide layer with the increased thickness needs to be etched first to form the implantation/doping window of the P-base region.
After an implantation/doping window of the P-base region is formed, the window can be used to perform P-base region implantation/doping on the enhanced carrier layer 204, and then high-temperature propulsion/diffusion processing is performed, so that the P-base region 205 is formed in the enhanced carrier layer 204. In this embodiment, the doping concentration of the P-base region 205 is preferably e17/cm3Magnitude.
It should be noted that in other embodiments of the present invention, the doping concentration of enhancement carrier layer 204 and/or P-base region 205 may also be other reasonable values according to practical needs, and the present invention is not limited thereto.
After forming the P-base region 205, a thickness D is formed on the substrate 2012SiO of (2)2 Layer 211, and multiple photolithography and etching processes are performed to form the step-shaped SiO layer shown in FIG. 82Mesa, wherein the SiO2The thinnest part of the table top has a thickness D1. In this example, D2Is preferably D1Over 10 times the value, D1The value of (A) is preferably 0.1. mu.m.
To obtain the SiO2Behind the mesa, in the SiO2A polysilicon layer with a specific thickness is formed on the table-board, and N-type polysilicon doping is carried out. In this embodiment, the polysilicon layer preferably has a thickness of less than 0.5 μm and a doping concentration of preferably 1e19/cm3The above. Of course, in other embodiments of the present invention, the thickness and the doping concentration of the polysilicon layer may be other reasonable values according to actual needs, and the present invention is not limited thereto.
As can be seen from fig. 9, after the polysilicon layer is formed, the ohmic contact region 207 and the source region 206 are covered by a portion of SiO2The layer and the polysilicon layer are subjected to photoetching or etching, thereby finally obtaining the required gate oxidationLayer 202 and polysilicon layer 203, and at the same time, by the photolithography or etching process, implantation/doping windows for making ohmic contact layers and source regions can also be formed.
After the implantation/doping windows of the ohmic contact layer and the source region are obtained, in this embodiment, the source region 206 and the ohmic contact region 207 are sequentially formed in the P-base region 205, and since the specific forming processes of the source region 206 and the ohmic contact region 207 are similar to the forming process of the P-base region, detailed descriptions thereof are omitted here. In the present embodiment, the thickness of the ohmic contact region 207 is preferably greater than the thickness of the source region 206.
Thus, the front process of the power semiconductor is completed. After the front side process is completed, the method provided by this embodiment performs the fabrication of the back side process of the power semiconductor. Specifically, as shown in fig. 9, one or more N buffer layer structures are first formed on the other surface of the substrate 201 by high temperature (e.g., greater than 1000 ℃) diffusion or ion implantation + low temperature (e.g., less than 500 ℃) annealing, thereby obtaining a buffer layer 208. In this embodiment, the buffer layer 208 includes a first buffer layer 208a and a second buffer layer 208 b. Then, a P + collector region 209 is formed on the surface of the buffer layer 208 by high temperature diffusion or ion implantation + laser annealing. Finally, a number of N + shorting dots 210 are formed in the P + collector region 209, again by high temperature diffusion or ion implantation + laser annealing.
It should be noted that, in different embodiments of the present invention, for a power semiconductor with a thicker thickness, the order of the front surface process and the back surface process (i.e., the process for fabricating the buffer layer, the collector region, and the short circuit point) may be adjusted, that is, the front surface process may be performed first, or the front surface process may be performed first, and then the back surface process may be performed. For the power semiconductor needing to be thinned, the front surface process is required to be carried out firstly, and then the back surface process is required to be carried out, and a high-temperature process cannot be carried out in the back surface process.
In addition, it should be noted that in other embodiments of the present invention, the process of fabricating the source region 206 and the ohmic contact region 207 may be advanced to before fabricating the gate oxide layer according to actual needs, and the present invention is not limited thereto.
It is to be understood that the disclosed embodiments of the invention are not limited to the particular structures, process steps, or materials disclosed herein but are extended to equivalents thereof as would be understood by those ordinarily skilled in the relevant arts. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.
Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.
While the above examples are illustrative of the principles of the present invention in one or more applications, it will be apparent to those of ordinary skill in the art that various changes in form, usage and details of implementation can be made without departing from the principles and concepts of the invention. Accordingly, the invention is defined by the appended claims.
Claims (6)
1. A power semiconductor, comprising:
a substrate;
a first conductive region formed in the substrate, the first conductive region having a source region of a first conductivity type formed therein;
a gate oxide layer formed on a surface of the substrate, the gate oxide layer contacting the source region, wherein the gate oxide layer has a plurality of thicknesses, and the thickness of the gate oxide layer shows a gradually increasing trend along with the distance from the first conductive region;
forming a polycrystalline silicon layer covering the gate oxide layer;
wherein the first conductive region includes an enhanced charge carrier layer formed in the substrate, a P-base layer having a second conductivity type formed in the enhanced charge carrier layer, a source region formed in the P-base layer, and an ohmic contact region having the second conductivity type, and the ohmic contact region is located at a middle position of the first conductive region;
the first end of the gate oxide layer is positioned above the source electrode region, and the second end of the gate oxide layer is aligned with the edge of the half cell; the gate oxide layer comprises a first layer section close to the ohmic contact area and a second layer section far away from the ohmic contact area, and the first layer section is positioned above the source electrode area and the P-base layer;
the first layer segment has a thickness that remains constant as the distance from the line in the ohmic contact region increases; the thickness of the second layer segment increases linearly with increasing line distance from the ohmic contact region.
2. The power semiconductor of claim 1, wherein the thickness of said gate oxide layer at its thickest location is more than 8 times the thickness at its thinnest location.
3. The power semiconductor of claim 1, wherein a thickness of the ohmic contact region is greater than a thickness of the source region.
4. The power semiconductor of claim 1, wherein the thickness of the polysilicon layer is equal at each location.
5. The power semiconductor of claim 1, further comprising:
a buffer layer formed on the other surface of the substrate;
a collector region formed on the buffer layer.
6. The power semiconductor of claim 5, further comprising a shorting point formed at the collector region.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5422505A (en) * | 1990-10-17 | 1995-06-06 | Kabushiki Kaisha Toshiba | FET having gate insulating films whose thickness is different depending on portions |
| CN1347158A (en) * | 2000-09-28 | 2002-05-01 | 株式会社东芝 | Semiconductor device and method for mfg. same |
| CN102194861A (en) * | 2009-12-28 | 2011-09-21 | 富士电机控股株式会社 | Semiconductor device |
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| JPH05198794A (en) * | 1992-01-23 | 1993-08-06 | Hitachi Ltd | Mis-type field-effect transistor |
| GB9423423D0 (en) * | 1994-11-14 | 1995-01-11 | Fuji Electric Co Ltd | Semiconductor device |
| DE112014001296T5 (en) * | 2013-03-13 | 2016-02-25 | Abb Technology Ag | Power semiconductor device and corresponding module |
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| US5422505A (en) * | 1990-10-17 | 1995-06-06 | Kabushiki Kaisha Toshiba | FET having gate insulating films whose thickness is different depending on portions |
| CN1347158A (en) * | 2000-09-28 | 2002-05-01 | 株式会社东芝 | Semiconductor device and method for mfg. same |
| CN102194861A (en) * | 2009-12-28 | 2011-09-21 | 富士电机控股株式会社 | Semiconductor device |
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