CN107563956B - Image-text superposition method and device - Google Patents
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Abstract
The invention provides a method and a device for superimposing pictures and texts. The method comprises the following steps: dividing a DDR storage space according to the number of the image-text information, and configuring a storage address corresponding to a DDR storage subspace for each image-text information; performing clock domain conversion on each image-text data to obtain converted image-text data; generating corresponding read address data and indication information according to each control information; storing the converted image-text data into corresponding DDR storage subspaces in an image-text information receiving sequence, and caching the indication information; reading corresponding image-text data from the DDR memory subspace according to the read address data, and finding corresponding indication information according to the image-text data; and inserting the corresponding image-text data into the video stream according to the indication information to realize image-text superposition. The image-text superposition method has high image-text superposition efficiency and low resource consumption, and can ensure that the FPGA can realize other functions while superposing the images and texts.
Description
Technical Field
The invention relates to the technical field of image-text superposition, in particular to an image-text superposition method and device.
Background
At present, the image-text superimposition scheme based on an FPGA (Field Programmable Gate Array) mainly used in the industry is to perform independent image-text reception, clock domain conversion, data storage, and data reading processing on each piece of image-text information, and then superimpose the processed image-text information on a video stream in sequence, thereby completing the corresponding image-text superimposition. However, the image-text superposition scheme has low image-text superposition efficiency, needs to consume a large amount of FPGA logic resources, and needs to allocate a whole set of FPGA logic resources corresponding to image-text receiving, clock domain conversion, data storage, and data reading processing flows for processing the added image-text information every time when adding one piece of image-text information, which easily causes the shortage of FPGA logic resources and cannot realize other functions of the FPGA.
Disclosure of Invention
In order to overcome the above disadvantages in the prior art, the present invention provides a method and an apparatus for superimposing images and texts. The image-text superposition method is high in image-text superposition efficiency, can fully utilize FPGA logic resources, reduces FPGA resource consumption, and enables the FPGA to realize other functions while carrying out image-text superposition.
In terms of the image-text superposition method, a preferred embodiment of the present invention provides an image-text superposition method, which is applied to an image-text superposition device based on an FPGA. The method comprises the following steps:
receiving input image-text information, dividing a DDR storage space into a corresponding number of DDR storage subspaces according to the number of the image-text information, and configuring a storage address corresponding to the DDR storage subspaces for each image-text information, wherein the image-text information comprises image-text data and corresponding control information;
performing clock domain conversion on each image-text data to obtain image-text data under a system clock domain of the FPGA after conversion;
generating reading address data and indication information corresponding to the image-text data according to the control information corresponding to the image-text data, wherein the reading address data is used for reading the image-text data stored in the corresponding DDR storage subspace, and the indication information is used for indicating the position of the corresponding image-text data superposed on the video stream;
sequentially storing each converted image-text data into a DDR storage subspace corresponding to the storage address according to the image-text information receiving sequence, and caching the indication information corresponding to each image-text data;
reading corresponding image-text data from the DDR storage subspace according to the read address data, and searching corresponding indication information from the cached indication information according to the read image-text data;
and receiving an input video stream, and inserting corresponding image-text data into the video stream according to each indication information to realize image-text superposition.
As for the image-text superimposing apparatus, a preferred embodiment of the present invention provides an image-text superimposing apparatus, which is generated based on an FPGA. The device comprises:
the space dividing module is used for receiving input image-text information, dividing the DDR storage space into DDR storage subspaces with corresponding numbers according to the number of the image-text information, and configuring a storage address corresponding to the DDR storage subspaces for each image-text information, wherein the image-text information comprises image-text data and corresponding control information;
the clock domain conversion module is used for performing clock domain conversion on each image-text data to obtain the image-text data under the system clock domain of the FPGA after conversion;
the read address generation module is used for generating read address data and indication information corresponding to the image-text data according to control information corresponding to the image-text data, wherein the read address data is used for reading the image-text data stored in a corresponding DDR storage subspace, and the indication information is used for indicating the position of the corresponding image-text data superposed on a video stream;
the data storage module is used for sequentially storing each converted image-text data into the DDR storage subspace corresponding to the storage addresses according to the image-text information receiving sequence and caching the indication information corresponding to each image-text data;
the data reading module is used for reading corresponding image-text data from the DDR storage subspace according to the reading address data and finding corresponding indication information from the cached indication information according to the read image-text data;
and the image-text superposition module is used for receiving the input video stream and inserting the corresponding image-text data into the video stream according to the indication information so as to realize image-text superposition.
Compared with the prior art, the image-text superposition method and device provided by the preferred embodiment of the invention have the following beneficial effects: the image-text superposition method is high in image-text superposition efficiency, can fully utilize FPGA logic resources, reduces FPGA resource consumption, and enables the FPGA to realize other functions while carrying out image-text superposition. Specifically, the image-text superposition method divides a DDR storage space into a corresponding number of DDR storage sub-spaces according to the number of the received image-text information, and configures a corresponding storage address for each image-text information so as to complete storage allocation of all the image-text information; performing clock domain conversion on the image-text data in the image-text information to obtain each image-text data in a system clock domain of the FPGA after conversion; generating reading address data and indication information corresponding to each image-text data by processing control information in each image-text information; sequentially storing the converted image-text data into corresponding DDR storage subspaces according to the image-text information receiving sequence of the storage address of each image-text information, and caching the indication information corresponding to each image-text data; reading corresponding image-text data from the DDR storage subspace according to the read address data, and searching corresponding indication information from the cached indication information according to the read image-text data; when the image-text data and the indication information corresponding to all the image-text information are read, the read image-text data are inserted into the received video stream at the same time according to the corresponding indication information, so that the corresponding image-text superposition is realized, the FPGA resource occupancy rate of the image-text superposition function is reduced, and the image-text superposition efficiency is improved. The read address data is used for reading the image-text data stored in the corresponding DDR storage subspace, and the indication information is used for indicating the position of the corresponding image-text data superposed on the video stream.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments are briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the claims of the present invention, and it is obvious for those skilled in the art that other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a flowchart illustrating a method for superimposing images and texts according to a preferred embodiment of the present invention.
Fig. 2 is a flowchart illustrating sub-steps included in a part of step S240 shown in fig. 1.
Fig. 3 is a flowchart illustrating sub-steps included in another part of step S240 shown in fig. 1.
Fig. 4 is a flowchart illustrating the sub-steps included in step S250 shown in fig. 1.
Fig. 5 is a block diagram of a graphics-text superimposing apparatus according to a preferred embodiment of the present invention.
Icon: 100-image-text superposition device; 110-a space division module; 120-clock domain conversion module; 130-a read address generation module; 140-a data storage module; 150-a data reading module; 160-image-text superposition module.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
How to provide a graphic superposition method and a graphic superposition device which have high graphic superposition efficiency and low FPGA resource consumption, can fully utilize FPGA logic resources, and can realize other functions while the FPGA performs graphic superposition, is a technical problem which needs to be solved urgently for technical personnel in the field.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Fig. 1 is a schematic flow chart of a graphics-text superimposing method according to a preferred embodiment of the present invention. In the embodiment of the present invention, the image-text superimposing method is applied to the image-text superimposing apparatus 100 based on the FPGA, and is used to improve the efficiency of superimposing image-text information onto a video stream by the FPGA, reduce the logic resource consumption of the FPGA, and enable the FPGA to realize other functions while performing image-text superimposition. The specific flow and steps of the image-text superimposing method shown in fig. 1 will be described in detail below.
In the embodiment of the invention, the image-text superposition method comprises the following steps:
step S210, receiving the input image-text information, dividing the DDR storage space into DDR storage subspaces with corresponding numbers according to the number of the image-text information, and configuring a storage address corresponding to the DDR storage subspaces for each image-text information.
In this embodiment, the teletext overlay arrangement 100 comprises a network interface, a processor and a DDR (double data rate synchronous dynamic random access memory), wherein the network interface is connected to the processor, and the processor is connected to the DDR. The image-text superimposing apparatus 100 receives externally input image-text information through the network interface, and divides a DDR memory space in a DDR by the processor when receiving the corresponding image-text information, so as to provide a corresponding memory space for each received image-text information.
Specifically, the processor divides the DDR memory space into a corresponding number of DDR memory subspaces according to the number of the received graphics and text information, configures a corresponding DDR memory subspace for each piece of graphics and text information, and allocates the memory address of each DDR memory subspace to the corresponding graphics and text information, thereby providing a corresponding memory space for each piece of received graphics and text information.
And step S220, performing clock domain conversion on each image-text data to obtain the image-text data in the system clock domain of the FPGA after conversion.
In this embodiment, the graphics information includes graphics data and corresponding control information, where the graphics data is substantial content corresponding to the graphics, and the control information is attribute information such as size, working mode, insertion position, overlay mode, moving speed, graphics line number, graphics column number, and graphics validity corresponding to the graphics. After receiving each piece of graphics and text information, the graphics and text superimposing apparatus 100 separates graphics and text data and control information from the corresponding graphics and text information, and performs clock domain conversion on each obtained graphics and text data, so that the converted graphics and text data can operate in the system clock domain of the FPGA.
Step S230, generating read address data and indication information corresponding to the image-text data according to the control information corresponding to each image-text data.
In this embodiment, the image-text superimposing apparatus 100 configures a storage address corresponding to the DDR memory subspace for each image-text information, and after separating the corresponding control information from each image-text information, processes the corresponding control information according to the storage address corresponding to each image-text information, and generates read address data and indication information corresponding to the image-text data in the image-text information. Each image-text data corresponds to a read address data and an indication message, and the read address data is used for reading the image-text data from a DDR memory subspace when the image-text data is stored in the DDR memory subspace corresponding to a memory address; the indication information is used for indicating the specific position of the corresponding image-text data when the image-text data is superposed on the video stream, and the indication information comprises information such as a frame header, a frame length, an image-text size, an insertion position and the like of the corresponding image-text data.
And step S240, sequentially storing the converted image-text data into DDR memory subspaces of corresponding memory addresses according to the image-text information receiving sequence, and caching the indication information corresponding to the image-text data.
In this embodiment, the image-text superimposing apparatus 100, after acquiring the storage address corresponding to each image-text information, each image-text data after clock domain conversion, the read address data corresponding to each image-text data, and the indication information, stores each image-text data obtained after conversion, and correspondingly caches the indication information corresponding to each image-text data. Specifically, the image-text superimposing apparatus 100 sequentially stores each converted image-text data into the DDR memory sub-space corresponding to the memory address according to the image-text information receiving sequence, and buffers each indication information into the buffer space included in the FPGA.
Further, please refer to fig. 2, which is a flowchart illustrating sub-steps included in a part of step S240 shown in fig. 1. In this embodiment of the present invention, the step of sequentially storing the converted teletext data in the DDR memory subspace corresponding to the memory address in the teletext information receiving order in step S240 may include sub-step S241 and sub-step S242. The substeps 241 and the substep S242 are as follows:
and a substep S241 of sequentially storing the converted image-text data into the same storage queue according to the image-text information receiving sequence.
In this embodiment, the teletext stacking arrangement 100 may store the teletext data of each teletext information after clock domain conversion in the same storage queue in sequence according to the order in which each teletext information is received at the network interface. Wherein the storage queue can be stored in a buffer space included in the FPGA.
And a substep S242, sequentially storing each image-text data into the DDR storage subspace matched with the corresponding storage address according to the distribution sequence of each image-text data in the storage queue.
In this embodiment, after storing all the converted teletext data in the same storage queue, the teletext stacking apparatus 100 sequentially stores each teletext data in a DDR storage subspace matching a corresponding storage address according to a distribution sequence of each teletext data in the storage queue. After storing all the image-text data into the corresponding DDR memory subspace, the image-text superimposing device 100 can release the cache space in which the memory queue is stored, so as to save the cache resources of the FPGA.
Fig. 3 is a schematic flow chart of sub-steps included in another part of step S240 shown in fig. 1. In an embodiment of the present invention, the step of buffering the indication information corresponding to each teletext data in step S240 may include substeps S243 and substep S244. The substeps 243 and the substep S244 are as follows:
and a substep S243, selecting the buffer spaces with the same number as the number of the indication information from the plurality of buffer spaces, wherein the total number of the buffer spaces is not less than the number of the indication information.
In this embodiment, a plurality of buffer spaces exist in the FPGA, the buffer spaces are previously divided in the FPGA by a manufacturer or a designer of the image-text superimposing apparatus 100 according to actual requirements, and the total number of the buffer spaces may be set differently by the manufacturer or the designer according to the actual requirements. When the image-text superimposing apparatus 100 caches the indication information corresponding to each image-text data, the same number of cache spaces as the number of the indication information may be selected from the plurality of cache spaces included in the FPGA, so as to cache each indication information. Wherein the total number of the buffer spaces existing in the FPGA is not less than the number of the indication information.
And a substep S244, respectively storing the indication information into the selected cache space, and establishing the relation between the selected cache space and the image-text data.
In this embodiment, the teletext overlay arrangement 100 allocates the selected cache space, so that each piece of indication information corresponds to one cache space. The image-text superimposing apparatus 100 stores each indication information into the corresponding buffer space, and establishes a connection between the buffer space in which the indication information is stored and the corresponding image-text data.
Referring to fig. 1 again, in step S250, corresponding image-text data is read from the DDR memory subspace according to each read address data, and corresponding indication information is searched from each indication information cached according to the read image-text data.
In this embodiment, after storing each image-text data in the DDR memory sub-space of the corresponding memory address, the image-text superimposing apparatus 100 may find the DDR memory sub-space corresponding to each read address data from the DDR memory space according to each read address data and the corresponding relationship between the read address data and the image-text data, and read the corresponding image-text data from the corresponding DDR memory sub-space. After reading the image-text data from the DDR memory subspace, the image-text superimposing apparatus 100 searches the indication information corresponding to the image-text data from the cached indication information according to the read image-text data.
Specifically, please refer to fig. 4, which is a flowchart illustrating the sub-steps included in step S250 shown in fig. 1. In this embodiment of the present invention, the step of finding the corresponding indication information from the cached indication information according to the read image-text data in step S250 may include substep S251 and substep S252. Wherein the substeps 251 and the substep S252 are as follows:
and a substep S251, searching a cache space corresponding to the read image-text data according to the relation between the image-text data and the cache spaces.
In this embodiment, the image-text superimposing apparatus 100 searches the cache space corresponding to the read image-text data from the selected cache space according to the relationship between the image-text data and the selected cache space, and obtains the cache space in which the indication information corresponding to the image-text data is cached.
And a substep S252, reading corresponding indication information from the searched cache space.
In this embodiment, after finding the cache space corresponding to the read image-text data, the image-text superimposing apparatus 100 directly reads the cache space, so as to extract the indication information corresponding to the image-text data from the cache space.
Step S260, receiving the input video stream, and inserting the corresponding image-text data into the video stream according to each indication information to realize image-text superposition.
In this embodiment, after completing reading of each piece of graphics-text data and corresponding knowledge information, the graphics-text superimposing apparatus 100 receives an externally input video stream through the network interface, and inserts the corresponding piece of graphics-text data into the video stream according to each piece of indication information, so as to realize graphics-text superimposition. Specifically, the step of inserting the corresponding teletext data into the video stream according to the respective indication information includes:
and if the image-text data and the indication information corresponding to all the image-text information are read, inserting the read image-text data into the video stream according to the corresponding indication information at the same moment, thereby completing the corresponding image-text superposition.
Fig. 5 is a block diagram of a graphics-text superimposing apparatus 100 according to a preferred embodiment of the invention. In the embodiment of the present invention, the image-text superimposing apparatus 100 is used for superimposing images and texts. The teletext overlay arrangement 100 may comprise: the space division module 110, the clock domain conversion module 120, the read address generation module 130, the data storage module 140, the data reading module 150, and the image-text superposition module 160.
The space dividing module 110 is configured to receive the input image-text information, divide the DDR memory space into a corresponding number of DDR memory subspaces according to the number of the image-text information, and configure a memory address corresponding to the DDR memory subspaces for each image-text information.
In this embodiment, the graphics and text information includes graphics and text data and corresponding control information, and the space dividing module 110 may perform step S210 in fig. 1, and the detailed description may refer to the above detailed description of step S210.
The clock domain conversion module 120 is configured to perform clock domain conversion on each image-text data to obtain image-text data in a system clock domain of the converted FPGA.
In this embodiment, the clock domain conversion module 120 may execute step S220 in fig. 1, and the detailed description may refer to the above detailed description of step S220.
The read address generating module 130 is configured to generate read address data and indication information corresponding to the image-text data according to the control information corresponding to each image-text data.
In this embodiment, the read address data is used to read the teletext data stored in the corresponding DDR memory subspace, and the indication information is used to indicate a position where the corresponding teletext data is overlaid on the video stream. The read address generating module 130 may include a read address generator and an indication information generator, and the read address generating module 130 generates each read address data through the read address generator and generates each indication information through the indication information generator. The read address generating module 130 may execute step S230 in fig. 1, and the detailed description may refer to the above detailed description of step S230.
The data storage module 140 is configured to store the converted image-text data into the DDR memory sub-spaces corresponding to the memory addresses in sequence according to the image-text information receiving sequence, and cache the indication information corresponding to the image-text data.
In this embodiment, the data storage module 140 may include an image-text storage sub-module and an indication cache sub-module, and the data storage module 140 sequentially stores the converted image-text data into DDR storage sub-spaces of corresponding storage addresses in an image-text information receiving sequence through the image-text storage sub-module, and caches indication information corresponding to the image-text data through the indication cache sub-module.
In this embodiment, the manner that the teletext sub-module in the data storage module 140 stores the converted teletext data into the DDR storage sub-spaces of the corresponding storage addresses in sequence in the reception order of the teletext information includes:
sequentially storing the converted image-text data into the same storage queue according to the image-text information receiving sequence;
and sequentially storing each image-text data into the DDR storage subspace matched with the corresponding storage address according to the distribution sequence of each image-text data in the storage queue.
In this embodiment, the manner of caching the indication information corresponding to each teletext data by the indication cache submodule in the data storage module 140 includes:
selecting cache spaces with the same number as the number of the indication information from the plurality of cache spaces, wherein the total number of the cache spaces is not less than the number of the indication information;
and respectively storing the indication information into the selected cache space, and establishing the relation between the selected cache space and the image-text data.
The data storage module 140 may execute step S240 shown in fig. 1, sub-step S241 and sub-step S242 shown in fig. 2, and sub-step S243 and sub-step S244 shown in fig. 3, and the detailed description may refer to the detailed description of step S240, sub-step S241, sub-step S242, sub-step S243, and sub-step S244 above.
The data reading module 150 is configured to read corresponding image-text data from the DDR memory subspace according to each read address data, and search corresponding indication information from each indication information cached according to the read image-text data.
In this embodiment, the manner for the data reading module 150 to find the corresponding indication information from the cached indication information according to the read image-text data includes:
searching a cache space corresponding to the read image-text data according to the relation between the image-text data and the cache spaces;
and reading corresponding indication information from the searched cache space.
The data reading module 150 can execute step S250 shown in fig. 1, and sub-steps S251 and S252 shown in fig. 2, and the detailed description can refer to the above detailed description of step S250, sub-step S251, and sub-step S252.
The image-text overlapping module 160 is configured to receive an input video stream, and insert corresponding image-text data into the video stream according to each indication information, so as to realize image-text overlapping.
In this embodiment, the manner of inserting the corresponding teletext data into the video stream by the teletext overlay module 160 according to each indication information includes:
and if the image-text data and the indication information corresponding to all the image-text information are read, inserting the read image-text data into the video stream according to the corresponding indication information at the same moment, thereby completing the corresponding image-text superposition.
The teletext overlay module 160 may perform step S260 shown in fig. 1, and the detailed description may refer to the above detailed description of step S260.
In summary, in the image-text superimposing method and apparatus provided in the preferred embodiment of the present invention, the image-text superimposing efficiency of the image-text superimposing method is high, so that the FPGA logic resources can be fully utilized, the FPGA resource consumption is reduced, and the FPGA can realize other functions while performing image-text superimposing. Specifically, the image-text superposition method divides a DDR storage space into a corresponding number of DDR storage sub-spaces according to the number of the received image-text information, and configures a corresponding storage address for each image-text information so as to complete storage allocation of all the image-text information; performing clock domain conversion on the image-text data in the image-text information to obtain each image-text data in a system clock domain of the FPGA after conversion; generating reading address data and indication information corresponding to each image-text data by processing control information in each image-text information; sequentially storing the converted image-text data into corresponding DDR storage subspaces according to the image-text information receiving sequence of the storage address of each image-text information, and caching the indication information corresponding to each image-text data; reading corresponding image-text data from the DDR storage subspace according to the read address data, and searching corresponding indication information from the cached indication information according to the read image-text data; when the image-text data and the indication information corresponding to all the image-text information are read, the read image-text data are inserted into the received video stream at the same time according to the corresponding indication information, so that the corresponding image-text superposition is realized, the FPGA resource occupancy rate of the image-text superposition function is reduced, and the image-text superposition efficiency is improved. The read address data is used for reading the image-text data stored in the corresponding DDR storage subspace, and the indication information is used for indicating the position of the corresponding image-text data superposed on the video stream.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for superimposing images and texts, the method comprising:
receiving input image-text information, dividing a DDR storage space into a corresponding number of DDR storage sub-spaces according to the number of the image-text information, and configuring a storage address corresponding to the DDR storage sub-spaces for each image-text information, wherein the image-text information comprises image-text data and corresponding control information, the control information is attribute information of corresponding images and texts, and the control information comprises the size, the working mode, the insertion position, the superposition mode, the moving speed, the number of lines, the number of columns and the effectiveness of the corresponding images and texts;
performing clock domain conversion on each image-text data to obtain image-text data under a system clock domain of the FPGA after conversion;
generating reading address data and indication information corresponding to the image-text data according to the control information corresponding to the image-text data, wherein the reading address data is used for reading the image-text data stored in the corresponding DDR storage subspace, and the indication information is used for indicating the position of the corresponding image-text data superposed on the video stream;
sequentially storing each converted image-text data into a DDR storage subspace corresponding to the storage address according to the image-text information receiving sequence, and caching the indication information corresponding to each image-text data;
reading corresponding image-text data from the DDR storage subspace according to the read address data, and searching corresponding indication information from the cached indication information according to the read image-text data;
and receiving an input video stream, and inserting corresponding image-text data into the video stream according to each indication information to realize image-text superposition.
2. The method as claimed in claim 1, wherein the step of sequentially storing the converted teletext data in the DDR memory subspace of the corresponding memory addresses in the teletext information reception order comprises:
sequentially storing the converted image-text data into the same storage queue according to the image-text information receiving sequence;
and sequentially storing each image-text data into the DDR storage subspace matched with the corresponding storage address according to the distribution sequence of each image-text data in the storage queue.
3. The method according to claim 1, wherein the FPGA includes a plurality of buffer spaces, and the step of buffering the indication information corresponding to each teletext data includes:
selecting cache spaces with the same number as the number of the indication information from the plurality of cache spaces, wherein the total number of the cache spaces is not less than the number of the indication information;
and respectively storing the indication information into the selected cache space, and establishing the relation between the selected cache space and the image-text data.
4. The method as claimed in claim 3, wherein the step of finding the corresponding indication information from the cached indication information according to the read image-text data comprises:
searching a cache space corresponding to the read image-text data according to the relation between the image-text data and the cache spaces;
and reading corresponding indication information from the searched cache space.
5. Method according to any of claims 1-4, wherein the step of inserting corresponding teletext data into the video stream in dependence on the respective indication information comprises:
and if the image-text data and the indication information corresponding to all the image-text information are read, inserting the read image-text data into the video stream according to the corresponding indication information at the same time.
6. A teletext overlay arrangement, the arrangement comprising:
the space dividing module is used for receiving input image-text information, dividing a DDR storage space into a corresponding number of DDR storage sub-spaces according to the number of the image-text information, and configuring a storage address corresponding to the DDR storage sub-spaces for each image-text information, wherein the image-text information comprises image-text data and corresponding control information, the control information is attribute information of corresponding images and texts, and the control information comprises the size, the working mode, the insertion position, the superposition mode, the moving speed, the image-text line number, the image-text column number and the image-text effectiveness of the corresponding images and texts;
the clock domain conversion module is used for performing clock domain conversion on each image-text data to obtain the image-text data under the system clock domain of the FPGA after conversion;
the read address generation module is used for generating read address data and indication information corresponding to the image-text data according to control information corresponding to the image-text data, wherein the read address data is used for reading the image-text data stored in a corresponding DDR storage subspace, and the indication information is used for indicating the position of the corresponding image-text data superposed on a video stream;
the data storage module is used for sequentially storing each converted image-text data into the DDR storage subspace corresponding to the storage addresses according to the image-text information receiving sequence and caching the indication information corresponding to each image-text data;
the data reading module is used for reading corresponding image-text data from the DDR storage subspace according to the reading address data and finding corresponding indication information from the cached indication information according to the read image-text data;
and the image-text superposition module is used for receiving the input video stream and inserting the corresponding image-text data into the video stream according to the indication information so as to realize image-text superposition.
7. The apparatus as claimed in claim 6, wherein the means for storing the converted teletext data into the DDR memory sub-spaces of the corresponding memory addresses sequentially in the teletext information receiving order by the data storage module comprises:
sequentially storing the converted image-text data into the same storage queue according to the image-text information receiving sequence;
and sequentially storing each image-text data into the DDR storage subspace matched with the corresponding storage address according to the distribution sequence of each image-text data in the storage queue.
8. The apparatus according to claim 6, wherein the FPGA includes a plurality of buffer spaces, and the manner of the data storage module buffering the indication information corresponding to each teletext data includes:
selecting cache spaces with the same number as the number of the indication information from the plurality of cache spaces, wherein the total number of the cache spaces is not less than the number of the indication information;
and respectively storing the indication information into the selected cache space, and establishing the relation between the selected cache space and the image-text data.
9. The apparatus according to claim 8, wherein the manner in which the data reading module finds the corresponding indication information from the cached indication information according to the read teletext data comprises:
searching a cache space corresponding to the read image-text data according to the relation between the image-text data and the cache spaces;
and reading corresponding indication information from the searched cache space.
10. The apparatus according to any of claims 6-9, wherein the manner in which the teletext overlay module inserts corresponding teletext data into the video stream in dependence on the respective indication information comprises:
and if the image-text data and the indication information corresponding to all the image-text information are read, inserting the read image-text data into the video stream according to the corresponding indication information at the same time.
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