CN107562647A - A kind of control method and device to the extension of digital signal processor processor reliability - Google Patents
A kind of control method and device to the extension of digital signal processor processor reliability Download PDFInfo
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Abstract
The invention provides a kind of control method that reliability extension is carried out to digital signal processor processor, the data interaction that digital signal processor processor and three magnetic RAMs are completed by field programmable gate array is achieved, comprised the following steps：A. the base address of magnetic RAM operation is recorded by field programmable gate array；B. check and correct the digital signal processor of storage magnetic RAM；C. field programmable gate array is controlled to complete the read operation to magnetic RAM and write operation by digital signal processor processor.The base address of present invention record magnetic RAM operation, inspection simultaneously correct the digital signal processor processor of magnetic RAM storage, perform digital signal processor processor read operation, perform digital signal processor processor write operation, implementing to monitor and correct the SEU events of magnetic RAM, monitoring digital signal processor processor running status, the in-orbit renewal for carrying out digital signal processor processor.
Description
Technical field
It is particularly a kind of to digital signal processor processor reliability the invention belongs to microsatellite, space application field
The control method and device of extension.
Background technology
Currently, the information processing system using High Performance DSP as core is widely used in spacecraft electronic system, uses
In control management of the realization to spacecraft and data processing.Due to DSP internal storage resource-constraineds, to realize big data
Information processing is measured, it is necessary to expand its external program memory and data storage, forms DSP minimum systems.
Spacecraft is easily influenceed in space motion by high energy charged particles, including total dose effect (TID)
With single particle effect (single-particle inversion SEU+ locking single particle SEL), cause its information processing system dysfunction or failure；Together
When with memory device integrated level improve constantly, process is less and less, and supply voltage constantly reduces, and circuit node faces
Boundary's electric charge substantially reduces, it is easier to is influenceed by SEU so that the data in memory device change, and cause disabler.
Space radiation has caused very big threat to spacecraft, in the failure that the synchronous satellite of transmitting in 1971 to 1986 occurs
In, 71% is caused by space radiation, and " wind and cloud No.1 " meteorological satellite in China is defended also in that space radiation causes posture space-time
Star fails.As can be seen here, the reliability for strengthening space electronic system is significant with the actual property of engineering.
The most frequently used method of space electronic system antiradiation protection is to carry out shielding protection design, using aluminium or tantalum, to spoke
Penetrate Sensitive Apparatus and carry out radiation shield, the method can effectively eliminate influence of the TID effects to electronic device；, can for SEL effects
Process circuit is monitored by impressed current to be protected.Above-mentioned ripe scheme may be directly applied in DSP minimum systems.For
The anti-SEU designs of SEU effects, especially DSP peripheral memory devices, typically take redundancy consolidation process.Using Redundancy Design
Thinking is that software code is deposited to more parts in memory device, and the operation of two from three is carried out in loading and operation.
Patent《A kind of quick loading method of skin satellite DSP programs》In, DSP program storages are in the three SPI Flash in outside
In, FPGA is triggered by DSP when being loaded after upper electricity and serially reads data in three SPI Flash and carries out two from three and operate, is obtained
The value obtained is transmitted further to DSP by FPGA；Patent《Dsp operation method and the device for dsp operation》In, during dsp operation, by
DSP sends the data that read signal triggering FPGA reads outside three memories, and DSP is transmitted to after carrying out two from three operation.The two are special
Profit relates separately to the loading of dsp software, operation.
But the two patents also still suffer from following problem：First, pertaining only to the read operation of DSP code, DSP is not directed to
The read-write operation of data (the stack data that especially application program should not be handled), i.e., redundancy is only carried out to DSP code, it is not right
DSP data carry out redundancy；Second, in the longtime running of space SEU events can occur because of single particle effect for memory, such as
Fruit does not have timely processing, it is possible to can occur have two even three storages in identical address in DSP BOOT program codes
Value has SEU situation, so as to which two from three mistake occur, causes the loading of DSP programs unsuccessful, same situation it can also happen that
In DSP program operation process, cause DSP program run-time errors；Third, DSP programs are in During Process of Long-term Operation, DSP processing
SEU events may occur for the register of device, cause DSP read or write address it is illegal, DSP program run-time errors, but this two
The individual patent function without storage protection, can not handle such case.
And it is a kind of not simple and reliable at present, when carrying out reliability extension to DSP using FPGA, effectively to DSP generations
Code and data carry out redundancy, correct SEU events in time, effectively to the technical scheme of address protection, specifically, not a kind of
To the control method and device of digital signal processor processor reliability extension.
The content of the invention
For technological deficiency existing for prior art, it is an object of the invention to provide a kind of to digital signal processor processor
The control method of progress reliability extension and correspondingly control device, according to an aspect of the invention, there is provided a kind of logarithm
Word signal procedure processor carries out the control method of reliability extension, and digital signal processor is completed by field programmable gate array
The data interaction of processor and three magnetic RAMs is achieved, and comprises the following steps：
A. the base address of the magnetic RAM operation is recorded by field programmable gate array；
B. check and correct the digital signal processor being stored in the magnetic RAM；
C. field programmable gate array is controlled to complete the reading to magnetic RAM by digital signal processor processor
Extract operation and write operation.
Preferably, the step b starts to perform when the data-signal program processor switches on power or when resetting.
Preferably, also comprise the following steps：
D. the single-particle for being monitored in real time by the field programmable gate array and correcting the magnetic RAM turns over
Turn event.
Preferably, the step d comprises the following steps：
D1. three continuous reading data values are obtained by the read operation and judges that the magnetic RAM is
No generation single event upset, step d2 is performed if single event upset occurs；
D2. obtained based on two from three redundancy principle from three continuous reading data values and preferably read data value, and used
The preferred improper value for reading data value and refreshing appropriate address in the magnetic RAM.
Preferably, also comprise the following steps after the step d2：
D3. back up the single event upset in any register in the field programmable gate array and produce
Interrupt；
D4. register value corresponding to the digital signal processor processor reading.
Preferably, also comprise the following steps：
E. the running status of the digital signal processor processor is monitored in real time by the field programmable gate array.
Preferably, the step e is following steps：
E1. address value corresponding to the read operation is monitored by the field programmable gate array in real time and described write
Address value corresponding to entering operation, judge address value corresponding to the read operation with the presence or absence of reading address anomalous event and institute
State address value corresponding to write operation and whether there is writing address anomalous event, if the reading address anomalous event be present,
The field programmable gate array refusal, which performs the read operation and the data-signal program processor is performed, resets behaviour
Make；If said write address anomalous event be present, the field programmable gate array refusal execution said write operation is simultaneously right
The data-signal program processor, which performs, resets operation.
Wherein, it is described reading address anomalous event refer to the read operation corresponding to address value be not belonging to the magnetic random
Address value corresponding to the memory space ranges in the work at present area of memory or the read operation is not belonging to data signal journey
The scope of sequence processor running space；Said write address anomalous event refer to said write operation corresponding to address value be not belonging to institute
State the work at present area of magnetic RAM memory space ranges or said write operation corresponding to address value be not belonging to
The scope of digital signal processor processor running space.
Preferably, also comprise the following steps：
F. the online updating of digital signal processor is performed by the field programmable gate array.
Preferably, the step f comprises the following steps：
F1. the digital signal processor processor receives the online updating that ground control centre is sent and instructs and notify described
Field programmable gate array carries out online updating state；
F2. the digital signal processor processor receives the updated data package of ground transmission and verified, if verification
Correctly, then by updated data package content valid data first address Src, valid data length L and the more new procedures in the magnetic
Address D st in property random access memory is sent to the field programmable gate array；
F3. the field programmable gate array according to be carrying out operation the magnetic RAM address space
Mark, obtain the current base address BA_NOMRAM for being not carried out operating the magnetic RAM and be carrying out the institute of operation
State the base address BA_MRAM of magnetic RAM；
F4. the field programmable gate array is in three magnetic RAMs, first address BA_MRAM+Src
The data of the L byte lengths of beginning, write-in destination address are in the memory space for the L byte lengths that BA_OMRAM+Dst starts；
F5. step f2 to f4 is repeated, after the renewal work of digital signal processor is finished generation renewal
Digital signal processor instructs.
Preferably, also executed the following steps after the step f5：
F6. the digital signal processor processor receives the data signal journey enabled after renewal of ground control centre transmission
Sequence instructs, and the digital signal processor processor notifies the field programmable gate array to enable new procedures, in three magnetic
Property random access memory and the field programmable gate array program register switch to present procedure operation position after, institute
State field programmable gate array and reset the digital signal processor processor, so that digital signal processor processor operation is more
Digital signal processor after new.
Preferably, the step b comprises the following steps：
B1. the field programmable gate array is in each magnetic RAM, according to the incremental order in address
Three data in three magnetic RAMs are read simultaneously；
B2. based on two from three redundancy principle from three data acquisition preference datas, three data one by one
It is whether equal with the preference data, judge that with the unequal data of the preference data be wrong data；
B3. the wrong data is refreshed using the preference data.
Preferably, the read operation in the step c comprises the following steps：
C1. the digital signal processor processor sends the instruction for performing read operation, the field programmable gate array
Obtain the instruction of the read operation and control line signal, reading address value RA_DSP；
C2. corresponding base is obtained according to the address space mark for the magnetic RAM for being carrying out read operation
Location BA_MRAM, while value V1, V2, V3 of three magnetic RAM appropriate address (RA_DSP+BA_MRAM) are read,
According to formula RV_DSP=(V1＆V2) | (V3＆V2) | (V1＆V3), RV_DSP is output to EMIF buses by the data signal
Program processor is read.
Preferably, the said write operation in the step c comprises the following steps：
C3. the digital signal processor processor sends the instruction for performing write operation, the field programmable gate array
Obtain the instruction of said write operation and control line signal, writing address value WA_DSP and write-in data value WV_DSP；
C4. the base according to corresponding to obtaining the address space mark for the magnetic RAM for being carrying out write operation
Address BA_MRAM, while in three magnetic RAM appropriate address (WA_DSP+BA_MRAM) write-in identical numbers
Value WV_DSP.
According to another aspect of the present invention, there is provided a kind of that reliability extension is carried out to digital signal processor processor
Control device, it is used to carry out digital signal processor processor reliability extension, including digital signal processor processor 1, existing
Field programmable gate array 2 and three magnetic RAMs 3, the digital signal processor processor 1 pass through asynchronous EMIF interfaces 4
Be connected with the field programmable gate array 2, the field programmable gate array 2 with asynchronous EMIF buses 5 respectively with three institutes
Magnetic RAM 3 is stated to connect.
Preferably, the magnetic RAM 3 divides for upper half 31 and bottom half 32, the upper half 31 and it is described under
Half area 32 is used to store code and data corresponding to different digital signal processors.
The present invention completes digital signal processor processor and three magnetic RAMs by field programmable gate array
Data interaction, realize the base address of record magnetic RAM operation, digital signal processor processor just upper electricity or
During reset, check and correct the digital signal processor processor of magnetic RAM storage, perform digital signal processor processing
Device read operation；Perform digital signal processor processor write operation, implement to monitor and correct the SEU events of magnetic RAM,
Monitor the functions such as digital signal processor processor running status, the in-orbit renewal for carrying out digital signal processor processor, the present invention
It is powerful, using it is simple, there is high use value.
Brief description of the drawings
The detailed description made by reading with reference to the following drawings to non-limiting example, further feature of the invention,
Objects and advantages will become more apparent upon：
Fig. 1 shows the embodiment of the present invention, a kind of to carry out reliability expansion to digital signal processor processor
The idiographic flow schematic diagram of the control method of exhibition；
Fig. 2 shows the first embodiment of the present invention, another to carry out reliability expansion to digital signal processor processor
The idiographic flow schematic diagram of the control method of exhibition；
Fig. 3 shows the second embodiment of the present invention, and reliability extension is being carried out to digital signal processor processor
In control method, a kind of simple grain for being monitored in real time by the field programmable gate array and correcting the magnetic RAM
The idiographic flow schematic diagram of sub- rollover event；
Fig. 4 shows the third embodiment of the present invention, another to carry out reliability expansion to digital signal processor processor
The idiographic flow schematic diagram of the control method of exhibition；
Fig. 5 shows the fourth embodiment of the present invention, another to carry out reliability expansion to digital signal processor processor
The idiographic flow schematic diagram of the control method of exhibition；
Fig. 6 shows the fifth embodiment of the present invention, and reliability extension is being carried out to digital signal processor processor
In control method, a kind of idiographic flow for the online updating that digital signal processor is performed by the field programmable gate array shows
It is intended to；
Fig. 7 shows the sixth embodiment of the present invention, and reliability extension is being carried out to digital signal processor processor
In control method, a kind of idiographic flow for checking and correcting the digital signal processor being stored in the magnetic RAM shows
It is intended to；
Fig. 8 shows the seventh embodiment of the present invention, and reliability extension is being carried out to digital signal processor processor
It is a kind of to control field programmable gate array to complete to magnetic RAM by digital signal processor processor in control method
Read operation and write operation idiographic flow schematic diagram；
Fig. 9 shows another embodiment of the present invention, a kind of that digital signal processor processor is carried out reliably
Property extension control device module connection diagram；And
Figure 10 shows the eighth embodiment of the present invention, the partitioned organization schematic diagram of the magnetic RAM.
Embodiment
Fig. 1 shows the embodiment of the present invention, a kind of to carry out reliability expansion to digital signal processor processor
The idiographic flow schematic diagram of the control method of exhibition, the control method complete digital signal processor by field programmable gate array
The data interaction of processor and three magnetic RAMs is achieved, it will be appreciated by those skilled in the art that the present invention will combine
The embodiment that Fig. 1 is shown into Fig. 8 realizes that the base address of record magnetic RAM operation, digital signal processor processor are firm
When upper electricity or reset, check and correct the digital signal processor processor of magnetic RAM storage, perform data signal
Program processor read operation；Perform digital signal processor processor write operation, implement to monitor and correct magnetic RAM
SEU events, monitor the work(such as digital signal processor processor running status, the in-orbit renewal for carrying out digital signal processor processor
Can, specifically, as shown in figure 1, comprising the following steps：
First, into step S101, the base that the magnetic RAM operates is recorded by field programmable gate array
Address, the field programmable gate array are FPGA, and FPGA uses highly reliable anti-fuse FPGA or Flash type FPGA,
FPGA is DSP Processor read-write external memory storage MRAM bridge.The magnetic RAM is MRAM, described
MRAM is the magnetic RAM that a kind of non-volatile, power down is not lost, and has the high fast reading of SRAM (SRAM)
Write capability.The MRAM memory spaces are divided into upper half and bottom half two parts, and each halfth area storage is DSP different editions
Program, DSP program codes and data are operated in the MRAM, and the DSP is digital signal processor processor, the number
Word signal procedure processor is preferably the TMS320C6000 series DSP processors of TI companies, and storage mapping is MAP1 patterns,
BOOT patterns are No Boot tupes, and all codes and data run on piece in the digital signal processor processor
In outer MRAM, on-chip SRAM does not store any code and data.
Further, it will be appreciated by those skilled in the art that the field programmable gate array in the process of running, is understood at three
The position of present procedure operation is recorded in magnetic RAM and in the register of digital signal processor processor program, i.e.,
Positioned at the upper half or bottom half of magnetic RAM, during digital signal processor processor read-write magnetic RAM,
Field programmable gate array reads and writes magnetic RAM as base address.
Then, into step S102, the digital signal processor being stored in the magnetic RAM is checked and corrects,
In such embodiments, the step S102 starts when the data-signal program processor switches on power or when resetting
Perform, in such embodiments, by step S101, the magnetic RAM is recorded by field programmable gate array
The base address of operation, further, start to perform when the data-signal program processor switches on power or when resetting
Step S102.
More specifically, when the digital signal processor processor is just upper electric or resets, the field-programmable gate array
Row can drag down the external reset pin of digital signal processor processor always so that digital signal processor processor, which is in, resets shape
State, further, the digital signal processor processor stored in magnetic RAM correspondingly data are checked, and
Analysis is compared to the data, analyzes wrong data in three magnetic RAMs, and is corrected, these will
It is further described, will not be described here in embodiment described later.
Finally, into step S103, field programmable gate array is controlled to complete to magnetic by digital signal processor processor
Property random access memory read operation and write operation, it will be appreciated by those skilled in the art that this step include to magnetic random store
In terms of the read operation of device and write operation two, it is further described in these embodiments that will be described below,
It will not go into details for this.
Fig. 2 shows the first embodiment of the present invention, another to carry out reliability expansion to digital signal processor processor
The idiographic flow schematic diagram of the control method of exhibition, as the first embodiment of the present invention, described Fig. 2 increases on the basis of Fig. 1
Step S204, the step S204 can be carried out simultaneously with step S103, you can to pass through digital signal processor processor
While control field programmable gate array completes read operation and the write operation to magnetic RAM, complete step and lead to
The single event upset that the field programmable gate array monitors and corrects the magnetic RAM in real time is crossed, this is not
Influence technical scheme, more specifically, the step of step S201 to step S203 may be referred to show in Fig. 1
S101 will not be described here to step S103.
Finally, into step S204, monitored in real time by the field programmable gate array and correct the magnetic random
The single event upset of memory, the single event upset are SEU, and single-particle inversion is single high energy grain in universe
Son injects semiconductor devices sensitive volume, the phenomenon for overturning device logic state, field programmable gate array in the process of running,
Can real-time monitoring data value, in the event of SEU events, then refresh the improper value of appropriate address in magnetic RAM, and
The a certain register of field programmable gate array, fills in the state of the SEU events currently occurred, and produces interruption, is believed by numeral
Number program processor reads the register value, is further described in these embodiments that will be described below, herein
It will not go into details.
Fig. 3 shows the second embodiment of the present invention, and reliability extension is being carried out to digital signal processor processor
In control method, a kind of simple grain for being monitored in real time by the field programmable gate array and correcting the magnetic RAM
The idiographic flow schematic diagram of sub- rollover event, it will be appreciated by those skilled in the art that as the second embodiment of the present invention, it is mainly used in
It is described in detail and how is monitored in step S204 and correct the single event upset of the magnetic RAM, specifically, bag
Include following steps：
First, into step S2041, obtained by the read operation described in three continuous reading data values and judgement
Whether magnetic RAM occurs single event upset, in such embodiments, if the single-particle inversion does not occur
Event, then the magnetic RAM need not be corrected, but can be monitored in real time, turned over if single-particle occurs
Turn event and then perform step S2042, further, the read operation is the read operation in step S103.
Then, into step S2042, preferred read is obtained from three continuous data values that read based on two from three redundancy principle
Data value is taken, and uses the preferred improper value for reading data value and refreshing appropriate address in the magnetic RAM, institute
State field programmable gate array in the process of running, understand when monitoring digital signal processor processor read operation in real time from three magnetic
The data value read in random access memory, in the event of SEU events, then the numerical value after being operated according to two from three, refresh the magnetic
Property random access memory in appropriate address improper value, correct the SEU events in the magnetic RAM in time, prevent because
Multiple SEU events accumulation causes same address in three magnetic RAMs two or more improper values occur, so as to cause
The situation that two from three operation can not be corrected occurs.
It will be appreciated by those skilled in the art that the two from three redundancy is made up of three function identical modules.In three modules
Output on plus a voting machine.As long as the output of any two in three modules is consistent, the output of voting machine be exactly this two
The AND-function of the output of individual module.So, three modules are even if there is the whole system that breaks down can also normal work.
Redundancy, refer to some parts of repetition configuration system, when system jam, the part of redundant configuration is intervened and undertakes failure portion
The work of part, thus reduce the fault time of system.And two from three redundancy principle in the present invention equally applies mentioned above principle,
Refresh the improper value of appropriate address in the magnetic RAM, correct the SEU things in the magnetic RAM in time
Part.
Subsequently, into step S2043, the list is backed up in any register in the field programmable gate array
Particle rollover event simultaneously produces interruption, further, in a certain register of the field programmable gate array, fills in current hair
The state of raw SEU events, and active break connects.
Finally, into step S2044, register value corresponding to the digital signal processor processor reading, the deposit
Data in the register for the state for backing up the SEU events after single event upset, further, institute as occur for device value
State digital signal processor processor and read the data.
Fig. 4 shows the third embodiment of the present invention, another to carry out reliability expansion to digital signal processor processor
The idiographic flow schematic diagram of the control method of exhibition, as the third embodiment of the present invention, described Fig. 4 increases on the basis of Fig. 2
Step S305, the step S305 can be carried out simultaneously with step S103, you can to pass through digital signal processor processor
While control field programmable gate array completes read operation and the write operation to magnetic RAM, complete step and lead to
The running status that the field programmable gate array monitors the digital signal processor processor in real time is crossed, this has no effect on this hair
Bright technical scheme, the step S301 to step S304 may be referred to the step S201 to step S204 shown in Fig. 2, herein
It will not go into details.
Finally, into step S305, monitored in real time at the digital signal processor by the field programmable gate array
Manage the running status of device.Grasped it will be appreciated by those skilled in the art that monitoring described read in real time by the field programmable gate array
Address value corresponding to address value corresponding to work and said write operation, judges whether address value is deposited corresponding to the read operation
It whether there is writing address anomalous event in address value corresponding to reading address anomalous event and said write operation, if in the presence of
Described to read address anomalous event, then the field programmable gate array refusal performs the read operation and the data is believed
Number program processor, which performs, resets operation；If said write address anomalous event be present, the field programmable gate array is refused
Said write operation is performed absolutely and the data-signal program processor is performed resets operation.
Wherein, it is described reading address anomalous event refer to the read operation corresponding to address value be not belonging to the magnetic random
Address value corresponding to the memory space ranges in the work at present area of memory or the read operation is not belonging to data signal journey
The scope of sequence processor running space；Said write address anomalous event refer to said write operation corresponding to address value be not belonging to institute
State the work at present area of magnetic RAM memory space ranges or said write operation corresponding to address value be not belonging to
The scope of digital signal processor processor running space.
In such embodiments, the digital signal processor processor in the process of running, can be compiled in the cycle to scene
Journey gate array safeguards that, if overtime, the field programmable gate array will drag down the reset of the digital signal processor processor
After pin makes the digital signal processor processor enter reset state for a period of time, then the pin is drawn high, make the numeral letter
Number program processor reenters normal mode of operation.
Further, the field programmable gate array in the process of running, can monitor the digital signal processor in real time
Address value when processor read operation and write operation, in the event of address anomalous event, the field programmable gate array will be refused
Exhausted current operation, dragging down the reset pin of the digital signal processor processor makes the digital signal processor processor enter again
Position state for a period of time after, then draw high the pin, the digital signal processor processor is reentered normal mode of operation,
In the present embodiment, the operation as FPGA that resets will refuse current operation, and dragging down DSP reset pin makes DSP enter reset
State for a period of time after, then draw high the pin, DSP is reentered normal mode of operation.
Fig. 5 shows the fourth embodiment of the present invention, another to carry out reliability expansion to digital signal processor processor
The idiographic flow schematic diagram of the control method of exhibition, as the fourth embodiment of the present invention, described Fig. 5 increases on the basis of Fig. 4
Step S406, the step S406 can be carried out simultaneously with step S103, you can to pass through digital signal processor processor
While control field programmable gate array completes read operation and the write operation to magnetic RAM, complete step and lead to
The online updating that the field programmable gate array performs digital signal processor is crossed, this has no effect on technical scheme,
The step S301 that the step S401 to step S405 may be referred to show in Fig. 4 will not be described here to step S305.
Finally, into step S406, the online updating of digital signal processor is performed by the field programmable gate array,
It will be appreciated by those skilled in the art that the digital signal processor processor is in the process of running, can perform at digital signal processor
Manage the in-orbit renewal operation of code in device.
Further, the digital signal processor processor notifies the field programmable gate array to carry out online updating shape
State, after verification, by the updated data package content valid data first address Src, valid data length L and more new procedures exist
Address D st in the magnetic RAM is sent to the field programmable gate array, the field programmable gate array
Obtain the current base address BA_NOMRAM for being not carried out operating the magnetic RAM and be carrying out the magnetic of operation
The base address BA_MRAM of random access memory, and in three magnetic RAMs, first address BA_MRAM+Src is opened
The data of the L byte lengths of beginning, write-in destination address are in the memory space for the L byte lengths that BA_OMRAM+Dst starts.
Further, repeat the above steps, after the renewal work of digital signal processor is finished generation renewal
Digital signal processor instruction, that is, complete the online updating to the digital signal processor.
Fig. 6 shows the fifth embodiment of the present invention, and reliability extension is being carried out to digital signal processor processor
In control method, a kind of idiographic flow for the online updating that digital signal processor is performed by the field programmable gate array shows
It is intended to, it will be appreciated by those skilled in the art that Fig. 6 has been described in detail performs digital signal processor by the field programmable gate array
Online updating the step for, specifically, comprise the following steps：
First, into step S4061, the digital signal processor processor receive that ground control centre sends it is online more
New command simultaneously notifies the field programmable gate array to carry out online updating state, and the ground control centre is staff
Control carries out signal, the reception of data, the control centre that sends, the ground control for the digital information program processor
Center processed preferably produces with the digital signal processor processor and communicates and be connected, further, the ground control centre
The online updating is instructed and is sent to the digital signal processor processor, described in the digital signal processor processor reception
Online updating is instructed, and the instruction is transferred into the field programmable gate array, and the field programmable gate array enters
The SBR of online updating.
Then, into step S4062, the updated data package that the digital signal processor processor receives ground transmission is gone forward side by side
Row verification, if verification is correct, by the updated data package content valid data first address Src, valid data length L and more
Address D st of the new procedures in the magnetic RAM is sent to the field programmable gate array.
It will be appreciated by those skilled in the art that the updated data package is the more new content for version updating, the verification
Be mainly used in being authenticated the ground control centre, verify the ground control centre whether with the digital signal processor
Processor matches, and when verification fails, the digital signal processor processor acquiescence disconnects the connection with the ground control centre
System, and in other examples, the digital signal processor processor does not take any operation, when verifying successfully, then by institute
Updated data package content valid data first address Src, valid data length L and more new procedures are stated in the magnetic RAM
In address D st be sent to the field programmable gate array, be based preferably on the field programmable gate array to the number
Word signal procedure processor is updated.
And then, into step S4063, the field programmable gate array according to be carrying out the magnetic of operation with
The address space mark of machine memory, obtain the current base address BA_NOMRAM for being not carried out operating the magnetic RAM
With the base address BA_MRAM of the magnetic RAM that is carrying out operation, the operation refers to read operation or writes
Enter operation.
After execution of step S4063, step S4064 is preferably carried out, the field programmable gate array is in three institutes
State in magnetic RAM, the data of the first address BA_MRAM+Src L byte lengths started, write-in destination address is BA_
In the memory space for the L byte lengths that OMRAM+Dst starts, the first address BA_MRAM+Src updates the data from described
Bag, by the data of the first address BA_MRAM+Src L byte lengths started, write-in destination address is opened for BA_OMRAM+Dst
In the memory space of the L byte lengths of beginning, the process of the renewal work as to the digital signal processor.
Subsequently, into step S4065, step S4062 to S4064 is repeated, until the renewal of digital signal processor
Work the instruction of the digital signal processor after generating renewal that is finished, it will be appreciated by those skilled in the art that to the data signal
When program is updated, not merely in the presence of a updated data package, within a certain period of time, multiple updated data packages are had from ground
Face control centre is sent in the digital signal processor processor, further, after verification, the field programmable gate
Array is obtained and is currently not carried out described in operation according to the address space mark for the magnetic RAM for being carrying out operation
The base address BA_NOMRAM of magnetic RAM and be carrying out operation the magnetic RAM base address BA_
MRAM, further, the field programmable gate array is in three magnetic RAMs, multiple updated data packages
In the data of L byte lengths that start of first address BA_MRAM+Src, write-in destination address is the L that BA_OMRAM+Dst starts
In the memory space of byte length, the instruction of the digital signal processor after being updated is finally completed.
In another preferred embodiment, after execution of step S4065, step S4066, the numeral are continued executing with
Signal procedure processor receives the digital signal processor instruction enabled after renewal of ground control centre transmission, the data signal
Program processor notifies the field programmable gate array to enable new procedures, in three magnetic RAMs and described existing
After the register of field programmable gate array program switches to the position of present procedure operation, the field programmable gate array weight
The digital signal processor processor is put, so that the digital signal processor after digital signal processor processor operation renewal,
The replacement is that the reset pin for dragging down the digital signal processor processor enters the digital signal processor processor
Reset state for a period of time after, then draw high the pin, the digital signal processor processor is reentered normal mode of operation.
In such embodiments, the digital signal processor processor receives the new procedures that enable that ground is sent and instructed,
The digital signal processor processor notice field programmable gate array enables new procedures, and field programmable gate array is in three magnetic
Property random access memory neutralize the position for switching present procedure operation in the register of the field programmable gate array program after,
Dragging down the reset pin of the digital signal processor processor makes the digital signal processor processor enter one section of reset state
After time, then the pin is drawn high, the digital signal processor processor is reentered normal mode of operation, in such state
Under, the digital signal processor processor will run new procedures.
Fig. 7 shows the sixth embodiment of the present invention, and reliability extension is being carried out to digital signal processor processor
In control method, a kind of idiographic flow for checking and correcting the digital signal processor being stored in the magnetic RAM shows
It is intended to, specifically, comprises the following steps：
First, pressed into step S1021, the field programmable gate array in each magnetic RAM
According to the incremental order in address while three data in three magnetic RAMs are read, at the digital signal processor
When managing device just above electric or reset, the outside that the field programmable gate array can drag down digital signal processor processor always is answered
Position pin so that digital signal processor processor is in reset state, in a preferred embodiment, the field-programmable
The program of the digital signal processor processor stored in upper and lower halfth area in three magnetic RAMs of gate array inspection, i.e.,
To some half area's memory space, in the memory space of the program of digital signal processor processor, according to the incremental order in address
The data of the address in three magnetic RAMs are read simultaneously, and the data are respectively V1, V2, V3.
Then, into step S1022, based on two from three redundancy principle from three data acquisition preference datas, one by one
It is whether equal with the preference data to compare three data, judges that with the unequal data of the preference data be error number
According to reference to the preferred embodiment shown in step S1021, according to the principle acquisition RV_DSP=(V1＆V2) of two from three | (V3＆
V2) | (V1＆V3), it is whether equal with RV_DSP to be then respectively compared V1, V2, V3.
Finally, into step S1023, refresh the wrong data using the preference data, with reference to step S1021 and
The preferred embodiment shown in step S1022, the principle based on the two from three obtain RV_DSP=(V1＆V2) | and (V3＆V2) |
(V1＆V3) it is whether equal with RV_DSP that V1, V2, V3, are then respectively compared, if which is unequal, being refreshed with RV_DSP should
Improper value.
It will be appreciated by those skilled in the art that check and correct the digital signal processor of the magnetic RAM storage
The program of processor, the magnetic RAM can be corrected before the digital signal processor processor program normal work
In SEU events because it is parallel work-flow that the field programmable gate array, which reads and writes the magnetic RAM, relative to
Patent《A kind of quick loading method of skin satellite DSP programs》In required for load time, this operation required time can be more
It is short.
Fig. 8 shows the seventh embodiment of the present invention, and reliability extension is being carried out to digital signal processor processor
It is a kind of to control field programmable gate array to complete to magnetic RAM by digital signal processor processor in control method
Read operation and write operation idiographic flow schematic diagram, specifically, comprise the following steps：
First, into step S1031, the digital signal processor processor sends the instruction for performing read operation, described
Field programmable gate array obtains the instruction of the read operation and control line signal, reading address value RA_DSP, the numeral
Signal procedure processor sends the control instruction of read operation, and the field programmable gate array is received at the digital signal processor
Manage the read operation control line signal of device and read address value RA_DSP.
Then, into step S1032, according to the address space for the magnetic RAM for being carrying out read operation
Mark obtains corresponding base address BA_MRAM, while reads three magnetic RAM appropriate address (RA_DSP+BA_
MRAM value V1, V2, V3), according to formula RV_DSP=(V1＆V2) | (V3＆V2) | (V1＆V3), RV_DSP is output to EMIF
Bus is read by the digital signal processor processor, it will be appreciated by those skilled in the art that according to the two from three redundancy in foregoing
Principle, value RV_DSP is output to EMIF buses, by the digital signal processor processor read, that is, complete to the magnetic with
The read operation of machine memory.
In another embodiment, control field programmable gate array not only can be with complete by digital signal processor processor
The read operation of paired magnetic RAM, can also complete the write operation to magnetic RAM, in such reality
Apply in example, initially enter step S1033, it will be appreciated by those skilled in the art that the step S1031 to step S1034 can be divided into
Read and two operations of write-in are separately carried out, further, the digital signal processor processor sends execution write operation
Instruction, the field programmable gate array obtains the instruction of said write operation and control line signal, writing address value WA_
DSP and write-in data value WV_DSP, is preferably sent the control instruction of write-in by the digital signal processor processor, described existing
Field programmable gate array obtains the control instruction, and control line signal, writing address value WA_DSP and write-in data value WV_
DSP。
Finally, into step S1034, according to the address space for the magnetic RAM for being carrying out write operation
Base address BA_MRAM corresponding to mark acquisition, while in three magnetic RAM appropriate address (WA_DSP+BA_
MRAM identical numerical value WV_DSP) is write, so as to complete the write operation to the magnetic RAM.
Fig. 9 shows another embodiment of the present invention, a kind of that digital signal processor processor is carried out reliably
Property extension control device module connection diagram, and Figure 10 shows the eighth embodiment of the present invention, the magnetic with
The partitioned organization schematic diagram of machine memory, as the control device of the present invention, it is preferable to carry out what is shown with reference to Fig. 1 into Fig. 8
Example come to the present invention control device be further described.
Further, as shown in figure 9, Fig. 9 shows a kind of module connection of control device, specifically, including numeral letter
Number program processor 1, field programmable gate array 2 and three magnetic RAMs 3, further, the data signal journey
Sequence processor 1 is connected with the field programmable gate array 2, and field programmable gate array 2 is deposited with three magnetic randoms
Reservoir 3 is connected, and the digital signal processor processor 1 is connected by asynchronous EMIF interfaces 4 and the field programmable gate array 2
Connect, the field programmable gate array 2 is connected with three magnetic RAMs 3 respectively with asynchronous EMIF buses 5, EMIF
Interface is external memory interface, and DSP and different kinds of memory (SRAM, Flash RAM, DDR-RAM etc.) can be achieved
Connection.General EMIF is connected with FPGA, so that the connection of FP reservoirs (SRAM, Flash RAM, DDR-RAM etc.), this area skill
Art personnel understand that these belong to currently available technology, will not be described here.
Further, as shown in Figure 10, the magnetic RAM 3 divides for upper half 31 and bottom half 32, it is described on
Half area 31 and the bottom half 32 are used to store code and data corresponding to different digital signal processors.In such embodiment
In, three magnetic RAMs being related in the present invention are provided with upper half 21 and bottom half 32, wherein, it is each
Ge Ban areas include program area and data field, i.e., each magnetic RAM include Liang Ge described programs area with
And two data fields, further, what is stored in described program area is generation corresponding to the different digital signal processors
Yard, what is stored in the data field is data.
The specific embodiment of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, those skilled in the art can make various deformations or amendments within the scope of the claims, this not shadow
Ring the substantive content of the present invention.
Claims (15)
1. a kind of control method that reliability extension is carried out to digital signal processor processor, it is characterised in that can by scene
The data interaction that programming gate array completes digital signal processor processor and three magnetic RAMs is achieved, including such as
Lower step：
A. the base address of the magnetic RAM operation is recorded by field programmable gate array；
B. check and correct the digital signal processor being stored in the magnetic RAM；
C. the reading for controlling field programmable gate array to complete to magnetic RAM by digital signal processor processor is grasped
Work and write operation.
2. control method according to claim 1, it is characterised in that the step b is handled in the data-signal program
Start to perform when device switches on power or when resetting.
3. control method according to claim 1, it is characterised in that also comprise the following steps：
D. monitored in real time by the field programmable gate array and correct the single-particle inversion thing of the magnetic RAM
Part.
4. control method according to claim 3, it is characterised in that the step d comprises the following steps：
D1. three continuous reading data values are obtained by the read operation and judges whether the magnetic RAM is sent out
Raw single event upset, step d2 is performed if single event upset occurs；
D2. obtained based on two from three redundancy principle from three continuous reading data values and preferably read data value, and described in use
It is preferred that read the improper value that data value refreshes appropriate address in the magnetic RAM.
5. control method according to claim 4, it is characterised in that also comprise the following steps after the step d2：
D3. during the single event upset is backed up in any register in the field programmable gate array and is produced
It is disconnected；
D4. register value corresponding to the digital signal processor processor reading.
6. control method according to claim 1, it is characterised in that also comprise the following steps：
E. the running status of the digital signal processor processor is monitored in real time by the field programmable gate array.
7. control method according to claim 1, it is characterised in that the step e is following steps：
E1. address value corresponding to the read operation is monitored by the field programmable gate array in real time and said write is grasped
Address value corresponding to work, judge address value corresponding to the read operation with the presence or absence of reading address anomalous event and described write
Address value corresponding to entering operation whether there is writing address anomalous event, described if the reading address anomalous event be present
Field programmable gate array refusal, which performs the read operation and the data-signal program processor is performed, resets operation；If
Said write address anomalous event be present, then the field programmable gate array refusal performs said write operation and to the number
It is believed that number program processor, which performs, resets operation.
Wherein, the reading address anomalous event refer to the read operation corresponding to address value be not belonging to magnetic random storage
Address value corresponding to the memory space ranges in the work at present area of device or the read operation is not belonging at digital signal processor
Manage the scope of device running space；Said write address anomalous event refer to said write operation corresponding to address value be not belonging to the magnetic
Property random access memory work at present area memory space ranges or said write operation corresponding to address value be not belonging to numeral
The scope of signal procedure processor running space.
8. control method according to claim 1, it is characterised in that also comprise the following steps：
F. the online updating of digital signal processor is performed by the field programmable gate array.
9. control method according to claim 1, it is characterised in that the step f comprises the following steps：
F1. the digital signal processor processor receives the online updating that ground control centre is sent and instructs and notify the scene
Programmable gate array carries out online updating state；
F2. the digital signal processor processor receives the updated data package of ground transmission and verified, if verification is correct,
Then by updated data package content valid data first address Src, valid data length L and the more new procedures in the magnetic random
Address D st in memory is sent to the field programmable gate array；
F3. the field programmable gate array according to be carrying out operation the magnetic RAM address space mark
Will, obtain the current base address BA_NOMRAM for being not carried out operating the magnetic RAM and be carrying out the described of operation
The base address BA_MRAM of magnetic RAM；
F4. the field programmable gate array starts first address BA_MRAM+Src in three magnetic RAMs
L byte lengths data, write-in destination address is in the memory space of L byte lengths that BA_OMRAM+Dst starts；
F5. step f2 to f4 is repeated, the numeral after the renewal work of digital signal processor is finished generation renewal
Signal procedure instructs.
10. control method according to claim 1, it is characterised in that also executed the following steps after the step f5：
F6. the digital signal processor processor receives the digital signal processor enabled after updating that ground control centre is sent and referred to
Order, the digital signal processor processor notifies the field programmable gate array to enable new procedures, three magnetic with
It is described existing after machine memory and the register of the field programmable gate array program switch to the position of present procedure operation
Field programmable gate array resets the digital signal processor processor, so that after digital signal processor processor operation renewal
Digital signal processor.
11. control method according to any one of claim 1 to 10, it is characterised in that the step b includes following step
Suddenly：
B1. the field programmable gate array is in each magnetic RAM, according to the incremental order in address simultaneously
Read three data in three magnetic RAMs；
B2. based on two from three redundancy principle from three data acquisition preference datas, three data and institute one by one
Whether equal state preference data, judge that with the unequal data of the preference data be wrong data；
B3. the wrong data is refreshed using the preference data.
12. control method according to any one of claim 1 to 10, it is characterised in that the reading in the step c
Extract operation comprises the following steps：
C1. the digital signal processor processor sends the instruction for performing read operation, and the field programmable gate array obtains
The instruction of the read operation and control line signal, reading address value RA_DSP；
C2. corresponding base address is obtained according to the address space mark for the magnetic RAM for being carrying out read operation
BA_MRAM, while read value V1, V2, V3 of three magnetic RAM appropriate address (RA_DSP+BA_MRAM), root
According to formula RV_DSP=(V1＆V2) | (V3＆V2) | (V1＆V3), RV_DSP is output to EMIF buses by the data signal journey
Sequence processor is read.
13. control method according to any one of claim 1 to 10, it is characterised in that write described in the step c
Enter operation to comprise the following steps：
C3. the digital signal processor processor sends the instruction for performing write operation, and the field programmable gate array obtains
The instruction of said write operation and control line signal, writing address value WA_DSP and write-in data value WV_DSP；
C4. the base address according to corresponding to obtaining the address space mark for the magnetic RAM for being carrying out write operation
BA_MRAM, while in three magnetic RAM appropriate address (WA_DSP+BA_MRAM) write-in identical numerical value WV_
DSP。
14. a kind of control device that reliability extension is carried out to digital signal processor processor, it is used for digital signal processor
Processor carries out reliability extension, it is characterised in that including digital signal processor processor (1), field programmable gate array (2)
With three magnetic RAMs (3), the digital signal processor processor (1) by asynchronous EMIF interfaces (4) with it is described existing
Field programmable gate array (2) connect, the field programmable gate array (2) with asynchronous EMIF buses (5) respectively with described in three
Magnetic RAM (3) connects.
15. control device according to claim 14, it is characterised in that the magnetic RAM (3) is divided into upper half
Area (31) and bottom half (32), the upper half (31) and the bottom half (32) are used to store different digital signal processors pair
The code and data answered.
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| CN111832049A (en) * | 2020-07-09 | 2020-10-27 | 郑州信大捷安信息技术股份有限公司 | SPI-based data transmission method and system |
| CN112181711A (en) * | 2020-09-15 | 2021-01-05 | 浙江吉利控股集团有限公司 | Error correction system and method for inhibiting single event upset by low-orbit satellite-borne DSP |
| CN112304283A (en) * | 2020-10-21 | 2021-02-02 | 国网福建省电力有限公司莆田供电公司 | Pole tower state intelligent monitoring terminal and method based on Beidou and 4G dual-mode communication |
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