CN107547904B - FPGA-based YUV data 8x8block conversion method and device in video compression - Google Patents
FPGA-based YUV data 8x8block conversion method and device in video compression Download PDFInfo
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Abstract
The invention provides a method and a device for converting YUV data 8x8block in video compression based on FPGA, and relates to the field of video data processing. The conversion method comprises the following steps: converting the RGB444 format data into YUV444 format data by using a matrix conversion formula; converting YUV444 format data into YUV420 format data, storing Y components, 8 FIFO storage U components and 8 FIFO storage V components by using 16 FIFOs respectively, and recording storage queues as Y _ FIFO, U _ FIFO and V _ FIFO in sequence; sequentially reading 16Y _ FIFOs, 8U _ FIFOs and 8V _ FIFOs in the S2 to respectively obtain 256Y components, 64U components and 64V components; and sequentially transmitting the 256Y components, the 64U components and the 64V components read out in the S3 to a video compression IP (Internet protocol), and finishing the conversion of 8x8 block. The invention breaks the limitation existing in the existing video data conversion, and reduces the project cost and the system complexity.
Description
Technical Field
The invention relates to the field of video data processing, in particular to a method and a device for converting YUV data 8x8block in video compression based on FPGA.
Background
In digital video processing, a video compression technology is a key technology, and video compression maintains the quality of a restored image while reducing the code rate of a video sequence, so that real-time transmission on a given communication channel is facilitated. The FPGA uses a small lookup table to realize the combinational logic function, and the structure allows infinite reprogramming, so that the FPGA is superior to a traditional general-purpose integrated circuit or an application-specific integrated circuit for the hardware realization of a video system.
In the prior art, referring to fig. 1, a method for compressing video data by using an FPGA includes that the FPGA receives RGB video data output by a display card, reduces data volume of an original video by video compression, packs the RGB video data according to an ethernet protocol, and transmits the RGB video data through a network card. The compression process comprises the steps of firstly converting RGB444 data output by the display card into YUV444 data, converting the YUV444 data into YUV420 data in order to further reduce the video data amount, and inputting the YUV420 data into a video compression IP (Internet protocol) according to an 8x8block mode to complete data compression. The conversion from the RGB444 data to the YUV420 data and the conversion from the 8x8block are completed by using an IP inside the FPGA, but the IP inside the FPGA needs to be purchased additionally, so that the use is limited greatly, the project cost is increased, and the system complexity is increased.
In order to solve the limitation of RGB 444-YUV 4208 x8block conversion in the prior art, the invention designs a YUV data 8x8block conversion method and device in video compression based on FPGA.
Disclosure of Invention
The invention aims to provide an FPGA-based YUV data 8x8block conversion method in video compression, which converts RGB444 data output by a video card into YUV420 data and inputs the YUV420 data to a video compression IP (Internet protocol) in an 8x8block mode, thereby improving the flexibility of a system and reducing the complexity of the system.
In order to solve the technical problems, the invention adopts the following technical scheme:
an FPGA-based YUV data 8x8block conversion method in video compression comprises the following steps:
s1, converting the RGB444 format data into YUV444 format data through a multiplier by using a matrix conversion formula;
s2, converting the YUV444 format data into YUV420 format data, respectively storing Y components, 8 FIFO storage U components and 8 FIFO storage V components by using 16 FIFOs, and sequentially recording storage queues as Y _ FIFO, U _ FIFO and V _ FIFO;
s3, sequentially reading 16Y _ FIFOs, 8U _ FIFOs and 8V _ FIFOs in the S2 to respectively obtain 256Y components, 64U components and 64V components;
and S4, sequentially transmitting the 256Y components, the 64U components and the 64V components read out in the S3 to a video compression IP (Internet protocol), and completing the conversion of 8x8 block.
Based on the scheme, the invention is optimized as follows:
as an optimization, in S1, the matrix conversion formula for converting the RGB444 format into the YUV444 format is:
Y＝0.257*R+0.504*G+0.098*B+16
U＝-0.148*R-0.291*G+0.439*B+128
V＝0.439R-0.368*G-0.071*B+128
as an optimization, in S2, the Y component is written into the Y _ FIFO by sequentially writing the Y component into the ((N% 16) +1) th Y _ FIFO according to the line number N where the Y component is located; the method for writing the U component into the U _ FIFO is that for the U components of even columns and even lines, the U components are sequentially written into the ((N/2)% 16) +1) th U _ FIFO according to the line number N where the U component is located, and the U components of odd lines or odd columns are not written into the U _ FIFO; the method for writing the V component into the V _ FIFO is that for the V components of even columns and even lines, the V components are written into ((N/2)% 16) +1) th V _ FIFO according to the line number N where the V component is located, and the V components of odd lines or odd columns are not written into the V _ FIFO.
Another object of the present invention is to provide an apparatus for converting YUV data 8x8block in FPGA-based video compression, wherein the apparatus comprises:
the RGB 444-YUV 444 conversion unit is used for converting the RGB444 format data into YUV444 format data by using a matrix conversion formula;
the YUV 444-YUV 420 conversion unit is used for converting YUV444 format data into YUV420 format data, and respectively utilizing 16 FIFOs to store Y components, 8 FIFOs to store U components, 8 FIFOs to store V components, and the storage queues are sequentially marked as Y _ FIFO, U _ FIFO and V _ FIFO;
the component reading unit is used for sequentially reading 16Y _ FIFOs, 8U _ FIFOs and 8V _ FIFOs in the YUV 444-YUV 420 conversion unit to respectively obtain 256Y components, 64U components and 64V components;
and the component transmission unit is used for sequentially transmitting the 256Y components, the 64U components and the 64V components read out from the component reading unit to the video compression IP to finish the conversion of 8x8 block.
As an optimization, in the RGB444 to YUV444 conversion unit, a matrix conversion formula for converting the RGB444 format into the YUV444 format is as follows:
Y＝0.257*R+0.504*G+0.098*B+16
U＝-0.148*R-0.291*G+0.439*B+128
V＝0.439R-0.368*G-0.071*B+128
as an optimization, in the YUV444 to YUV420 conversion unit, a method for writing the Y component into the Y _ FIFO is to sequentially write the Y component into the ((N% 16) +1) th Y _ FIFO according to the line number N where the Y component is located; the method for writing the U component into the U _ FIFO is that for the U components of even columns and even lines, the U components are written into the ((N/2)% 16) +1) th U _ FIFO in sequence according to the line number N where the U component is located, and the U components of odd lines or odd columns are not written into the U _ FIFO; the method for writing the V component into the V _ FIFO is to sequentially write ((N/2)% 16) +1) th V _ FIFO for the V components of the even-numbered columns and the even-numbered lines according to the line number N where the V component is located, and the V components of the odd-numbered lines or the odd-numbered columns are not written into the V _ FIFO.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
according to the method and the device for converting the YUV data 8x8block in the FPGA-based video compression, matrix transformation, logic control and FIFO array conversion are utilized to realize the conversion from RGB444 to YUV420 data 8x8block and complete the compression processing of the video data, the whole processing process only occupies few FPGA logic resources, the purchase cost of converting by using an internal IP of the FPGA is saved, the limitation of the existing conversion mode is broken, the system design is more flexible and simple to realize, the project cost and the system complexity are greatly reduced, and the working efficiency is improved.
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FIG. 1 is a block diagram of a prior art FPGA-based video compression process;
fig. 2 is a flowchart of a YUV data 8x8block conversion method in FPGA-based video compression according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of 8 × 8block conversion provided in an embodiment of the present application;
fig. 4 is a logic block diagram of a YUV data 8x8block conversion method in video compression based on an FPGA according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an 8x8block conversion device for YUV data in FPGA-based video compression according to an embodiment of the present disclosure;
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
To facilitate an understanding of the embodiments, abbreviations and key terms referred to in the embodiments are explained and illustrated.
RGB 444: each pixel point of the pixel data output by the display card consists of R, G, B numerical values which respectively represent red, green and blue colors;
YUV 444: the RGB444 data is subjected to matrix transformation, and a component Y represents a luminance signal and a component U, V represents two color difference signals;
YUV 420: from YUV444 data, keeping all Y components in the YUV444 data unchanged, and only keeping U, V data of even rows and even columns;
8x8 block: inputting a data block to a video compression IP, wherein the length and the width of the data block are both 8;
IP: an IP core, an Intellectual Property core, a fully-named Intellectual Property core, refers to a reusable module provided by a certain party and designed in the form of a logic unit and a chip;
y _ FIFO: a FIFO storing the Y component;
u _ FIFO: a FIFO storing the U component;
v _ FIFO: a FIFO storing the V component.
As shown in fig. 2 to fig. 4, the method for converting YUV data 8x8block in FPGA-based video compression according to this embodiment includes the steps of,
s1, converting the RGB444 format data into YUV444 format data through a multiplier by using a matrix conversion formula;
s2, converting the YUV444 format data into YUV420 format data, respectively storing Y components, 8 FIFO storage U components and 8 FIFO storage V components by using 16 FIFOs, and sequentially recording storage queues as Y _ FIFO, U _ FIFO and V _ FIFO;
s3, sequentially reading 16Y _ FIFOs, 8U _ FIFOs and 8V _ FIFOs in the S2 to respectively obtain 256Y components, 64U components and 64V components;
and S4, sequentially transmitting the 256Y components, the 64U components and the 64V components read out in the S3 to a video compression IP (Internet protocol), and completing the conversion of 8x8 block.
Specifically, in S1, the RGB2YUV module converts the pixel data from RGB444 format to YUV444 format, and the specific implementation method converts the pixel data according to the following matrix conversion formula:
Y＝0.257*R+0.504*G+0.098*B+16
U＝-0.148*R-0.291*G+0.439*B+128
V＝0.439R-0.368*G-0.071*B+128
in order to conveniently use hardware language to realize the formula, the formula is transformed as follows, namely, two sides of the equation are enlarged by 1024 times to obtain:
Y<<10＝(263*R)+(516*G)+(100*B)+16384
U<<10＝(-152*R)-(298*G)+(450*B)+131072
V<<10＝(450*R)-(377*G)-(73*B)+131072
since the multiplication of negative numbers is implemented in the computer in the form of complement, the above formula is converted into:
Y<<10＝(12'h107*R)+(12'h204*G)+(12'h064*B)+20'h04000
U<<10＝(12'hF68*R)+(12'hED6*G)+(12'h1C2*B)+20'h20000
V<<10＝(12'h1C2*R)+(12'hE87*G)+(12'hFB7*B)+20'h20000
after the above formula is calculated by a multiplier, two sides of the formula are simultaneously divided by 1024 to obtain YUV444 data:
Y＝((12'h107*R)+(12'h204*G)+(12'h064*B)+20'h04000)>>10
U＝((12'hF68*R)+(12'hED6*G)+(12'h1C2*B)+20'h20000)>>10
V＝((12'h1C2*R)+(12'hE87*G)+(12'hFB7*B)+20'h20000)>>10
further, after the YUV444 data is obtained, in order to reduce the data amount of the video and not affect the compressed video effect, the YUV444 format data is converted into YUV420 format data in S2, the implementation method is implemented by using a FIFO array write control module in the logic block diagram of fig. 4, and the module learns the column number and the row where the current pixel is located in a counting manner. Wherein the content of the first and second substances,
for the Y component, the Y component is sequentially written into the ((N% 16) +1) th Y _ FIFO according to the line number N where the Y component is located;
for the U component, the U components of the even columns and the even rows are sequentially written into the (((N/2)% 16) +1) th U _ FIFO according to the row number N where the U component is located, and the U components of the odd rows or the odd columns are not written into the U _ FIFO;
for the V component, the V components of the even column and the even row are written into the (((N/2)% 16) +1) th V _ FIFO in turn according to the row number N where they are located, and the V component of the odd row or the odd column is not written into the V _ FIFO.
Further, in S3, the FIFO array read control module in the logic block diagram of fig. 4 is utilized to sequentially read the 1 st to 16 th Y _ FIFOs, respectively read 16 times, to obtain 256Y components, then sequentially read the 1 st to 8 th U _ FIFOs, respectively read 8 times, to obtain 64U components, then sequentially read the 1 st to 8 th V _ FIFOs, respectively read 8 times, to obtain 64V components.
Fig. 5 is a schematic diagram of an 8x8block conversion device for YUV data in FPGA-based video compression according to an embodiment of the present application, where the conversion device includes:
the RGB 444-YUV 444 conversion unit is used for converting the RGB444 format data into YUV444 format data by using a matrix conversion formula;
the YUV 444-YUV 420 conversion unit is used for converting YUV444 format data into YUV420 format data, and respectively utilizing 16 FIFOs to store Y components, 8 FIFOs to store U components, 8 FIFOs to store V components, and the storage queues are sequentially marked as Y _ FIFO, U _ FIFO and V _ FIFO;
the component reading unit is used for sequentially reading 16Y _ FIFOs, 8U _ FIFOs and 8V _ FIFOs in the YUV 444-YUV 420 conversion unit to respectively obtain 256Y components, 64U components and 64V components;
and the component transmission unit is used for sequentially transmitting the 256Y components, the 64U components and the 64V components read out from the component reading unit to the video compression IP to finish the conversion of 8x8 block.
Specifically, in the RGB444 to YUV444 conversion unit, the RGB2YUV module converts the pixel data from the RGB444 format to the YUV444 format, and the specific implementation method performs the conversion according to the following matrix conversion formula:
Y＝0.257*R+0.504*G+0.098*B+16
U＝-0.148*R-0.291*G+0.439*B+128
V＝0.439R-0.368*G-0.071*B+128
further, in order to reduce the data volume of the video and not affect the compressed video effect, the YUV 444-YUV 420 conversion unit converts the YUV444 format data into YUV420 format data, and specifically, the column number and the row where the current pixel point is located are obtained in a counting mode through the FIFO array write control module. Wherein, for the Y component, the Y component is sequentially written into the ((N% 16) +1) th Y _ FIFO according to the line number N where the Y component is located; for the U component, the U components of the even columns and the even rows are sequentially written into the (((N/2)% 16) +1) th U _ FIFO according to the row number N where the U component is located, and the U components of the odd rows or the odd columns are not written into the U _ FIFO; for the V component, the V components of the even column and the even row are written into the (((N/2)% 16) +1) th V _ FIFO in turn according to the row number N where they are located, and the V component of the odd row or the odd column is not written into the V _ FIFO.
Further, the component reading unit sequentially reads 1 st to 16 th Y _ FIFOs by using the FIFO array read control module, respectively reads 16 times to obtain 256Y components, then sequentially reads 1 st to 8 th U _ FIFOs, respectively reads 8 times to obtain 64U components, then sequentially reads 1 st to 8 th V _ FIFOs, respectively reads 8 times to obtain 64V components.
In the embodiment of the invention, the conversion from RGB444 to YUV420 data 8x8block is realized by utilizing matrix transformation, logic control and FIFO array conversion, the compression processing of the video data is completed, the purchase cost of conversion by using an internal IP of an FPGA is saved, the project cost and the system complexity are greatly reduced, and the flexibility of system design is improved.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and it will be apparent to those skilled in the art that any modification, improvement and equivalent substitution made without departing from the principle of the present invention are included in the protection scope of the present invention.
Claims (4)
1. An FPGA-based YUV data 8x8block conversion method in video compression is characterized by comprising the following steps:
s1, converting the RGB444 format data into YUV444 format data through a multiplier by using a matrix conversion formula;
s2, converting the YUV444 format data into YUV420 format data, respectively storing Y components, 8 FIFO storage U components and 8 FIFO storage V components by using 16 FIFOs, and sequentially recording storage queues as Y _ FIFO, U _ FIFO and V _ FIFO;
the method for writing the Y component into the Y _ FIFO is to write the Y component into the ((N% 16) +1) th Y _ FIFO in sequence according to the line number N of the Y component;
the method for writing the U component into the U _ FIFO is that for the U components of even columns and even lines, the U components are sequentially written into the (((N/2)% 16) +1) th U _ FIFO according to the line number N where the U component is located, and the U components of odd lines or odd columns are not written into the U _ FIFO;
the method for writing the V component into the V _ FIFO is that for the V component of the even-numbered columns and the even-numbered lines, the V component is sequentially written into the (((N/2)% 16) +1) th V _ FIFO according to the line number N where the V component is located, and the V component of the odd-numbered lines or the odd-numbered lines is not written into the V _ FIFO;
s3, sequentially reading the 16Y _ FIFOs in the S2, respectively reading for 16 times to obtain 256Y components, sequentially reading 8U _ FIFOs, respectively reading for 8 times to obtain 64U components, sequentially reading 8V _ FIFOs, respectively reading for 8 times to obtain 64V components;
and S4, sequentially transmitting the 256Y components, the 64U components and the 64V components read out in the S3 to a video compression IP (Internet protocol), and completing the conversion of 8x8 block.
2. The method of claim 1, wherein in S1, the matrix conversion formula for converting RGB444 format into YUV444 format is as follows:
Y＝0.257*R+0.504*G+0.098*B+16
U＝-0.148*R-0.291*G+0.439*B+128
V＝0.439R-0.368*G-0.071*B+128 。
3. an FPGA-based YUV data 8x8block conversion device in video compression is characterized in that the conversion device comprises:
the RGB 444-YUV 444 conversion unit is used for converting the RGB444 format data into YUV444 format data by using a matrix conversion formula;
the YUV 444-YUV 420 conversion unit is used for converting YUV444 format data into YUV420 format data, and respectively utilizing 16 FIFOs to store Y components, 8 FIFOs to store U components, 8 FIFOs to store V components, and the storage queues are sequentially marked as Y _ FIFO, U _ FIFO and V _ FIFO; the method for writing the Y component into the Y _ FIFO is to write the Y component into the ((N% 16) +1) th Y _ FIFO in sequence according to the line number N where the Y component is located; the method for writing the U component into the U _ FIFO is that for the U components of even columns and even rows, the U components are written into the (((N/2)% 16) +1) th U _ FIFO in sequence according to the row number N where the U component is located, and the U components of odd rows or odd columns are not written into the U _ FIFO; the method for writing the V component into the V _ FIFO is that for the V components of even-numbered columns and even-numbered lines, the V components are written into the (((N/2)% 16) +1) th V _ FIFO in sequence according to the line number N where the V component is located, and the V components of odd-numbered lines or odd-numbered columns are not written into the V _ FIFO;
a component reading unit, configured to read the 16Y _ FIFOs in the YUV444 to YUV420 conversion unit sequentially, read the 16Y _ FIFOs respectively, obtain 256Y components, read the 8U _ FIFOs sequentially, read the 8U _ FIFOs respectively, obtain 64U components, read the 8V _ FIFOs sequentially, and read the 8V _ FIFOs respectively, obtain 64V components;
and the component transmission unit is used for sequentially transmitting the 256Y components, the 64U components and the 64V components read out from the component reading unit to the video compression IP to finish the conversion of 8x8 block.
4. The apparatus of claim 3, wherein in the RGB444 to YUV444 conversion unit, the matrix conversion formula for converting RGB444 format to YUV444 format is as follows:
Y＝0.257*R+0.504*G+0.098*B+16
U＝-0.148*R-0.291*G+0.439*B+128
V＝0.439R-0.368*G-0.071*B+128 。
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