CN107547070A - Using the PMOS drive circuit and its design method of active technology of releasing - Google Patents
Using the PMOS drive circuit and its design method of active technology of releasing Download PDFInfo
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Abstract
The invention discloses a kind of PMOS drive circuit using active technology of releasing, including NPN type triode Q2, NMOS tube Q3, Schottky diode D2, electric capacity C2, resistance R1, resistance R2, resistance R3 and resistance R4, NMOS tube Q3 grid is connected with resistance R3 one end, and NMOS tube Q3 drain electrode is connected with resistance R2 one end；NPN type triode Q2 base stage is connected by electric capacity C2 with NMOS tube Q3 drain electrode, NPN type triode Q2 colelctor electrode is connected with the source electrode of PMOS to be driven, and NPN type triode Q2 emitter stage is connected with the grid of the resistance R2 other end and PMOS to be driven；The invention also discloses a kind of design method of the PMOS drive circuit using active technology of releasing.The present invention realizes that convenient and cost is low, and design method step is simple, can effectively ensure that PMOS fast conducting and shut-off.
Description
Technical field
The invention belongs to switch power technology field, and in particular to a kind of PMOS using active technology of releasing drives electricity
Road and its design method.
Background technology
It is increasing to the demand of Switching Power Supply with developing rapidly for electronic market, while to Switching Power Supply performance
It is required that also more and more higher.Full-control type power transistor is one of core of Switching Power Supply, and its running status and security are straight
Connecing influences the quality of switch converters performance.Full-control type power transistor can be divided into huge transistor (GTR), insulated gate bipolar
Transistor (IGBT), power field effect transistor (VDMOS), gate turn off thyristor (GTO).Because power MOS transistor is
Most wide one kind of wholly-controled device midband, therefore, by attention in high frequency process, and due to power MOS transistor
There is short channel, high resistant drift region and vertical conduction, its pressure-resistant and current capacity is greatly improved, therefore, opening
Conversion field is closed to be used widely.
Drive circuit is the interface between main circuit and control circuit, and drive circuit is mainly special to improve the static state of device
Property and dynamic characteristic, drive circuit should ensure that power device is fully on and damaged with reducing opening for device with shut-off with reliable turn-off
Consumption, wish to shorten switch time as power switch, reduce power attenuation.Because power MOS switch tube is a kind of most current-carrying
The monopole type voltage control device of subconductivity, have switching speed is fast, high frequency performance is good, input impedance is high, driving power is small and
Without remarkable advantages such as second breakdown problems, therefore, power MOS transistor is more advantageous as switching device.
Power MOS (Metal Oxide Semiconductor) device can be divided into nmos device and PMOS device by the type of conducting carriers, it is more in NMOS tube
Number carriers are electronics, and the majority carrier in PMOS is hole, because the mobility in the mobility ratio hole of electronics is big, institute
So that in the case where physical dimension and operating voltage absolute value are equal, the mutual conductance of NMOS tube is big, speed is fast, electric current is big.Therefore,
NMOS tube is wider than PMOS application, and the switching device in Switching Power Supply is typically all using NMOS tube as switching tube.But
It is that NMOS tube turn-on condition is that gate source voltage at least should be greater than its threshold voltage, this causes when source electrode connects input maximum level,
Just need to produce one using NMOS tube on grid than inputting higher level, this just needs to drive using boostrap circuit, isolation
Dynamic circuit or integrated form drive circuit, but volume to be present big due to it, the shortcomings of circuit structure complexity, without practical value.
It is exactly to use PMOS as switching tube to solve the most appropriate method of this problem, when source electrode connects input maximum level
When, grid level need to only be dragged down, the conducting of PMOS can.But due to grid source, grid leak and the source of power MOS transistor
Parasitic capacitance in leakage be present, time of its discharge and recharge not only delay MOS transistor open and the turn-off time, and increase
The power attenuation of circuit.Therefore, to make PMOS quickly can open and turn off in on-off circuit, not only need in grid
Apply undersuing between source electrode, while need to inject in PMOS grid and extract enough electric charges, PMOS exists
Ability fast conducting is with turning off in on-off circuit, and parasitic capacitance both end voltage could be fast within the time as short as possible in PMOS
Speed is raised and lowered into required magnitude of voltage, so as to reduce the switching loss of PMOS, improves switch efficiency.
Driven in number of patent application in the Chinese patent open source literature of " 201010509695.8 ", to disclose a kind of PMOS
Dynamic circuit and its driving method, when PMOS turns on, shunt-wound capacitance C2 is charged to store electric charge, when PMOS turns off
Shunt-wound capacitance C2 discharges electric charge, forces NPN type triode Q1 to turn on, and extracting PMOS gate charge rapidly switches off it, with this
Improve the turn-off speed of PMOS.But resistance R2 and R3 value are extremely difficult in the circuit, first, resistance R2, R3 must
Certain intrinsic standoff ratio must be met to ensure that resistance R3 both end voltages are more than the threshold voltage of PMOS, while the electricity at resistance R2 both ends
Pressure determines magnitude of voltage when shunt-wound capacitance C2 charges to stable state, and the voltage must can make NPN type triode when PMOS turns off
Q1 saturation conductions.Secondly, if resistance R2, R3 value smaller charging interval that can improve PMOS gate-source parasitic capacitance, with
The efficiency of on-off circuit is improved, but resistance R3, D1 electric current are flowed through during PMOS conducting can be increased simultaneously, so as to increase electricity
The switching loss on road.
Adjusted in number of patent application in the Chinese patent open source literature of " 200810240744.5 ", to disclose a kind of BUCK
P-channel MOSFET drive circuit in device, its drive circuit include upper tube Q1 drivings and driven with down tube Q2, when upper tube Q1 turns on the phase
Between, control down tube Q2 ends so that NPN type triode VT1 conductings, larger charging current is provided for electric capacity C1, forces down tube Q1
Fast conducting；During upper tube Q1 is turned off, control down tube Q2 is turned on so that NPN type triode VT1 ends, and upper tube Q1 is reliably closed
It is disconnected.But the drive circuit, during Q1 pipes turn off, gate-source parasitic capacitance must be discharged through resistance R1, and the velocity of discharge is slower,
And the drive circuit need to control Q1 pipes with Q2 pipes alternate conduction, it is necessary to rationally set two-way drive signal, and circuit structure is complicated.
The content of the invention
In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is that provide a kind of structure letter
Reasonable, realization single, novel in design is conveniently and cost is low, operating efficiency is high, switching loss is small, functional reliability is high, practical
The PMOS drive circuit using active technology of releasing.
In order to solve the above technical problems, the technical solution adopted by the present invention is：A kind of PMOS using active technology of releasing
Tube drive circuit, it is characterised in that：Including NPN type triode Q2, NMOS tube Q3, Schottky diode D2, electric capacity C2, resistance
R1, resistance R2, resistance R3 and resistance R4, the grid of the NMOS tube Q3 are connected with resistance R3 one end, and the resistance R3's is another
One end is the input of outside PWM drive signal, the source ground of the NMOS tube Q3, the drain electrode of the NMOS tube Q3 and resistance
R2 one end connection；The base stage of the NPN type triode Q2 is connected by electric capacity C2 with the drain electrode of the NMOS tube Q3, described
NPN type triode Q2 colelctor electrode and the cathode output end of external power source and the source electrode of PMOS to be driven connect, the NPN
Type triode Q2 emitter stage is connected with the grid of the resistance R2 other end and PMOS to be driven；The resistance R1 is attempted by
Between the colelctor electrode and emitter stage of the NPN type triode Q2, the resistance R4 is attempted by grid and the source of the NMOS tube Q3
Between pole；The anode of the Schottky diode D2 is connected with the emitter stage of the NPN type triode Q2, the pole of Schottky two
Pipe D2 negative electrode is connected with the base stage of the NPN type triode Q2.
The above-mentioned PMOS drive circuit using active technology of releasing, it is characterised in that：Also include voltage-regulator diode D1,
The anode of the voltage-regulator diode D1 is connected with the drain electrode of the NMOS tube Q3, the negative electrode of the voltage-regulator diode D1 with it is described
NPN type triode Q2 emitter stage connection.
The above-mentioned PMOS drive circuit using active technology of releasing, it is characterised in that：The NPN type triode Q2's
Model ZTX651.
The above-mentioned PMOS drive circuit using active technology of releasing, it is characterised in that：The model of the NMOS tube Q3
For IRF510.
The above-mentioned PMOS drive circuit using active technology of releasing, it is characterised in that：The Schottky diode D2
Model SS14.
Present invention also offers a kind of method and step is simple, realization is convenient, improve the operating efficiency of circuit, reduces electricity
The design method of the PMOS drive circuit using active technology of releasing of the switching loss on road, it is characterised in that this method bag
Include following steps：
Step 1: choose NPN type triode Q2, NMOS tube Q3 and the Schottky diode D2 of suitable types, detailed process
It is as follows：
Step 101, the NPN type triode of model of the multiplication factor more than 100 is chosen as NPN type triode Q2；
Step 102, selection electric current are less than 10A, and the NMOS tube conduct of model of the drain-source breakdown voltage less than or equal to 100V
NMOS tube Q3；
Step 103, selection rated current are less than 0.5A, and the pole of Schottky two of model of the reverse recovery time less than 30ns
Pipe is as Schottky diode D2；
Step 2: it is as follows to choose the resistance R1 of suitable parameters, resistance R2, resistance R3 and resistance R4, detailed process：
Step 201, between 1k Ω~10k Ω choose resistance R1 and resistance R2 resistance；
Step 202, according to formulaResistance R3 resistance is chosen, wherein, Vcc is PMOS to be driven
The supply voltage of pwm chip, I in the switching power circuit of placemaxFor in switching power circuit where PMOS to be driven
The peak point current of pwm chip, t be NMOS tube Q3 switching delay time, parasitisms of the C between NMOS tube Q3 grids and source electrode
Electric capacity；
Step 203, the resistance according to formula R4=100R3 selection resistance R4；
Step 3: choosing the electric capacity C2 of suitable parameters, detailed process is as follows：
Step 301, according to formulaCalculate collector current during NPN type triode Q2 saturation conductions
iC(Q2), wherein, β(Q2)For NPN type triode Q2 multiplication factor, VC2The steady-state value that electric capacity C2 charges when being turned on for PMOS Q1
And VC2=VD1-VD2, VD1For voltage-regulator diode D1 voltage stabilizing value, VD2For the voltage at Schottky diode D2 both ends；
Step 302, according to formulaCalculating is begun to shut off to PMOS to be driven from NMOS tube Q3
Parasitic capacitance C1 between grid and source electrode discharges into time t of the both end voltage needed for equal to zerooff1, wherein, ViTo be to be driven
The input voltage of switching power circuit where PMOS；
Step 303, according to formulaChoose electric capacity C2 capacitance；
Step 4: connection NPN type triode Q2, NMOS tube Q3, Schottky diode D2, electric capacity C2, resistance R1, resistance
R2, resistance R3 and resistance R4, form PMOS high-speed switch drive circuit；Detailed process is as follows：
Step 401, NMOS tube Q3 grid is connected with resistance R3 one end, resistance R3 other end extraction wire is made
For the input of outside PWM drive signal, by NMOS tube Q3 source ground, by NMOS tube Q3 drain electrode and resistance R2 one end
Connection；
Step 402, NPN type triode Q2 base stage is connected with electric capacity C2 one end, by the electric capacity C2 other end with
NMOS tube Q3 drain electrode connection, by the cathode output end of NPN type triode Q2 colelctor electrode and external power source and to be driven
The source electrode connection of PMOS, by NPN type triode Q2 emitter stage and the resistance R2 other end and the grid of PMOS to be driven
Pole connects；
Step 403, resistance R1 one end is connected with NPN type triode Q2 colelctor electrode, by the resistance R1 other end with
NPN type triode Q2 emitter stage connection, resistance R4 one end is connected with NMOS tube Q3 grid, by the resistance R4 other end
It is connected with NMOS tube Q3 source electrode；
Step 404, Schottky diode D2 anode is connected with NPN type triode Q2 emitter stage, by Schottky two
Pole pipe D2 negative electrode is connected with NPN type triode Q2 base stage；
Step 405, voltage-regulator diode D1 anode is connected with NMOS tube Q3 drain electrode, by voltage-regulator diode D1 negative electrode
It is connected with NPN type triode Q2 emitter stage.
Above-mentioned method, it is characterised in that：Parasitism electricity described in step 302 between PMOS grid and source electrode to be driven
The value for holding C1 is 1000pF~2000pF.
The present invention has advantages below compared with prior art：
1st, the PMOS drive circuit using active technology of releasing of the invention, circuit structure is simple, novel in design reasonable,
Realize that convenient and cost is low, it is practical.
2nd, the PMOS drive circuit using active technology of releasing of the invention, by voltage-regulator diode D1 introducing, changes
Circuit working state is become, has enabled to resistance R1 and resistance R2 value unrestricted, and ensure that PMOS Q1 turns on the phase
Between electric capacity C2 store constant energy, to prevent phenomenon that NPN type triode Q2 misleads.
3rd, the design method of the PMOS drive circuit using active technology of releasing of the invention, method and step is simple, only
Electric capacity C2 size need to be chosen emphatically, resistance R1 and resistance R2 value are unrestricted, and resistance R3 and resistance R4 value are simple,
It is convenient to realize, and can effectively ensure that PMOS is quickly opened and turned off, and improves the operating efficiency of circuit, reduces circuit
Switching loss.
4th, the PMOS drive circuit using active technology of releasing of the invention, it is easy to control, securely and reliably, effectively solve
PMOS of having determined can not quickly open the problem with shut-off so that when existing outside PWM controller is operated in high-frequency, PMOS
Effectively can reliably it work.
In summary, circuit structure of the invention is simple, realizes that convenient and cost is low, design method step is simple, can
PMOS fast conducting and shut-off is effectively ensured, circuit working effect is high, and functional reliability is high, and practical, market prospects are wide
It is wealthy.
Below by drawings and examples, technical scheme is described in further detail.
Brief description of the drawings
Fig. 1 is circuit theory diagrams of the present invention using the PMOS drive circuit of active technology of releasing.
Fig. 2 is method flow block diagram of the present invention using the design method of the PMOS drive circuit of active technology of releasing.
Fig. 3 is exemplary application map of the present invention using the PMOS drive circuit of active technology of releasing.
Fig. 4 A are oscillography when the present invention drives PMOS Q1 conductings using the PMOS drive circuit of active technology of releasing
Device tests the test waveform figure of grid and voltage between source electrodes.
Fig. 4 B are oscillography when the present invention drives PMOS Q1 shut-offs using the PMOS drive circuit of active technology of releasing
Device tests the test waveform figure of grid and voltage between source electrodes.
Fig. 4 C are oscillography when the present invention drives PMOS Q1 conductings using the PMOS drive circuit of active technology of releasing
Device tests grid with leaking the test waveform figure of voltage across poles.
Fig. 4 D are oscillography when the present invention drives PMOS Q1 shut-offs using the PMOS drive circuit of active technology of releasing
Device tests grid with leaking the test waveform figure of voltage across poles.
Embodiment
As shown in figure 1, the PMOS drive circuit using active technology of releasing of the present invention, including NPN type triode Q2,
NMOS tube Q3, Schottky diode D2, electric capacity C2, resistance R1, resistance R2, resistance R3 and resistance R4, the grid of the NMOS tube Q3
Pole is connected with resistance R3 one end, and the other end of the resistance R3 is the input of outside PWM drive signal, the NMOS tube Q3
Source ground, the drain electrode of the NMOS tube Q3 is connected with resistance R2 one end；The base stage of the NPN type triode Q2 passes through electricity
Hold C2 to be connected with the drain electrode of the NMOS tube Q3, the colelctor electrode of the NPN type triode Q2 and the cathode output end of external power source
Connected with the source electrode of PMOS to be driven, the emitter stage of the NPN type triode Q2 and the resistance R2 other end and to be driven
PMOS grid connection；The resistance R1 is attempted by between the colelctor electrode and emitter stage of the NPN type triode Q2, described
Resistance R4 is attempted by between the grid and source electrode of the NMOS tube Q3；The anode of the Schottky diode D2 and the NPN type
Triode Q2 emitter stage connection, the negative electrode of the Schottky diode D2 are connected with the base stage of the NPN type triode Q2.
When it is implemented, the drain electrode of PMOS to be driven is voltage output end Vout.
In the present embodiment, as shown in figure 1, the PMOS to be driven is PMOS Q1.C1 in Fig. 1 is PMOS Q1
Parasitic capacitance between grid and source electrode.
In the present embodiment, as shown in figure 1, the PMOS high-speed switch drive circuit also includes voltage-regulator diode D1, institute
The anode for stating voltage-regulator diode D1 is connected with the drain electrode of the NMOS tube Q3, negative electrode and the NPN of the voltage-regulator diode D1
Type triode Q2 emitter stage connection.Voltage-regulator diode D1 can when PMOS Q1 is opened filling for its internal parasitic capacitances C1
Electricity provides big Injection Current, improves PMOS Q1 conducting efficiency, reduces PMOS Q1 conduction loss；It is moreover, described
Voltage-regulator diode D1 is introduced in drive circuit, enables to resistance R1 and resistance R2 value unrestricted, and ensure that PMOS
Electric capacity C2 stores constant energy during pipe Q1 is turned on, to prevent phenomenon that NPN type triode Q2 misleads.
In the present embodiment, the model ZTX651 of the NPN type triode Q2.
In the present embodiment, the model IRF510 of the NMOS tube Q3.Because NMOS tube is that one kind relies on majority carrier
Conductive monopole type voltage control device, there is the advantages of switching speed is fast, therefore, low electricity is chosen in the drive circuit
Pressure, the NMOS tube Q3 of low current, reduce the influence to PMOS Q1 switching speeds.
In the present embodiment, the model SS14 of the Schottky diode D2.
The present invention the PMOS drive circuit for using active technology of releasing operation principle for：Believe when outside PWM drives
Number output high level when, NMOS tube Q3 saturation conductions, input voltage is not only through parasitic capacitance C1, resistance R2 and NMOS tube Q3 branch roads
Charged for parasitic capacitance C1, while be to post through parasitic capacitance C1, Schottky diode D2, electric capacity C2 and NMOS tube Q3 branch roads
Raw electric capacity C1 quick charges.In parasitic capacitance C1 charging paths, because resistance R1 resistances are larger, charge branch to parasitic capacitance C1
Road shunting action is smaller, and parasitic capacitance C1 chargings are very fast, while parasitic capacitance C1, Schottky diode D2, electric capacity C2 and NMOS
Pipe Q3 branch roads also charge to electric capacity C2.Therefore, parasitic capacitance C1 rises with electric capacity C2 both end voltages, NMOS tube Q3 drain-sources electricity
Drops；It is equal to voltage-regulator diode with Schottky diode D2 forward conduction voltages sum when electric capacity C2 rises to its both end voltage
During D1 voltage stabilizing value, electric capacity C2 both end voltages are invariable, and voltage-regulator diode D1 reverse breakdowns, now, input voltage is only through posting
Raw electric capacity C1, voltage-regulator diode D1 and NMOS tube Q3 branch roads are parasitic capacitance C1 quick charges, and parasitic capacitance C1 both end voltages are fast
Speed rises, and NMOS tube Q3 drain-source voltages continue to decline, until VA≤VC1-VTH(VAFor the electricity between NMOS tube Q3 source electrodes and drain electrode
Pressure；VC1For parasitic capacitance C1 both end voltages；VTHFor NMOS tube Q3 threshold voltage) when, NMOS tube Q3 is linearly turned on, and works as parasitism
Electric capacity C1 charges to both end voltage and is equal to Vi-VD1(ViFor the input voltage of switching power circuit where PMOS to be driven, VD1
For voltage-regulator diode D1 voltage stabilizing value) when, PMOS Q1 is fully on；When outside PWM drive signal exports low level, NMOS
Pipe Q3 ends, and shunt-wound capacitance C2 electric discharges, provides ideal base drive current for NPN type triode Q2, NPN type triode Q2 saturations are led
It is logical while resistance R1 is short-circuit, parasitic capacitance C1 repid discharges so that PMOS Q1 quickly ends.Wherein, voltage-regulator diode D1
Effect except PMOS Q1 turn on during for parasitic capacitance C1 inject electric charge make its fast conducting, make resistance R1 and resistance R2
Value it is unrestricted outer；Electric capacity C2 stores constant energy during also ensuring PMOS Q1 conductings, to prevent the pole of NPN type three
The phenomenon that pipe Q2 misleads.
As shown in Fig. 2 the design method of the PMOS drive circuit using active technology of releasing of the present invention, including it is following
Step：
Step 1: choose NPN type triode Q2, NMOS tube Q3 and the Schottky diode D2 of suitable types, detailed process
It is as follows：
Step 101, the NPN type triode of model of the multiplication factor more than 100 is chosen as NPN type triode Q2；So
Only need the base current of very little, it becomes possible to its internal parasitic capacitances C1 velocity of discharge when improving PMOS Q1 shut-offs；This implementation
In example, the model ZTX651 of the NPN type triode Q2；
Step 102, selection electric current are less than 10A, and the NMOS tube conduct of model of the drain-source breakdown voltage less than or equal to 100V
NMOS tube Q3；In the present embodiment, the model IRF510 of the NMOS tube Q3；
Step 103, selection rated current are less than 0.5A, and the pole of Schottky two of model of the reverse recovery time less than 30ns
Pipe is as Schottky diode D2；In the present embodiment, the model SS14 of the Schottky diode D2；
Step 2: it is as follows to choose the resistance R1 of suitable parameters, resistance R2, resistance R3 and resistance R4, detailed process：
Step 201, between 1k Ω~10k Ω choose resistance R1 and resistance R2 resistance；In the present embodiment, resistance is chosen
R1 and resistance R2 resistance are 1k Ω；
Step 202, according to formulaResistance R3 resistance is chosen, wherein, Vcc is PMOS to be driven
The supply voltage of pwm chip, I in the switching power circuit of placemaxFor in switching power circuit where PMOS to be driven
The peak point current of pwm chip, t be NMOS tube Q3 switching delay time, parasitisms of the C between NMOS tube Q3 grids and source electrode
Electric capacity；In the present embodiment, Vcc=15V, Imax=1A, t=50ns, C=125pF, according to formulaCalculate
To the Ω of 15 Ω ＜ R3 ＜ 400, therefore the resistance for choosing resistance R3 is 100 Ω；
Step 203, the resistance according to formula R4=100R3 selection resistance R4；The acting as of resistance R4 prevents interference signal
NMOS tube Q3 is set to mislead, in the present embodiment, the resistance for choosing resistance R4 is 10k Ω；
Step 3: choosing the electric capacity C2 of suitable parameters, detailed process is as follows：
Step 301, according to formulaCalculate collector current during NPN type triode Q2 saturation conductions
iC(Q2), wherein, β(Q2)For NPN type triode Q2 multiplication factor, VC2The steady-state value that electric capacity C2 charges when being turned on for PMOS Q1
And VC2=VD1-VD2, VD1For voltage-regulator diode D1 voltage stabilizing value, VD2For the voltage at Schottky diode D2 both ends；The present embodiment
In, β(Q2)=100, VD1=3.6V, VD2=0.7V, according to formula VC2=VD1-VD2V is calculatedC2=2.9V, according to formulaI is calculatedC(Q2)=0.29A；
Step 302, according to formulaCalculating is begun to shut off to PMOS to be driven from NMOS tube Q3
Parasitic capacitance C1 between grid and source electrode discharges into time t of the both end voltage needed for equal to zerooff1, wherein, ViTo be to be driven
The input voltage of switching power circuit where PMOS；In the present embodiment, Vi=15V, VD1=3.6V, C1=1050pF, iC(Q2)
=0.29A, according to formulaT is calculatedoff1=41ns；
Step 303, according to formulaChoose electric capacity C2 capacitance；In the present embodiment, toff1=41ns, R2
=1k Ω, according to formula41pF ＜ C are calculated2＜ 1050pF, therefore, the capacitance for choosing electric capacity C2 is
1000pF；
Step 4: connection NPN type triode Q2, NMOS tube Q3, Schottky diode D2, electric capacity C2, resistance R1, resistance
R2, resistance R3 and resistance R4, form PMOS high-speed switch drive circuit；Detailed process is as follows：
Step 401, NMOS tube Q3 grid is connected with resistance R3 one end, resistance R3 other end extraction wire is made
For the input of outside PWM drive signal, by NMOS tube Q3 source ground, by NMOS tube Q3 drain electrode and resistance R2 one end
Connection；
Step 402, NPN type triode Q2 base stage is connected with electric capacity C2 one end, by the electric capacity C2 other end with
NMOS tube Q3 drain electrode connection, by the cathode output end of NPN type triode Q2 colelctor electrode and external power source and to be driven
The source electrode connection of PMOS, by NPN type triode Q2 emitter stage and the resistance R2 other end and the grid of PMOS to be driven
Pole connects；
Step 403, resistance R1 one end is connected with NPN type triode Q2 colelctor electrode, by the resistance R1 other end with
NPN type triode Q2 emitter stage connection, resistance R4 one end is connected with NMOS tube Q3 grid, by the resistance R4 other end
It is connected with NMOS tube Q3 source electrode；
Step 404, Schottky diode D2 anode is connected with NPN type triode Q2 emitter stage, by Schottky two
Pole pipe D2 negative electrode is connected with NPN type triode Q2 base stage；
Step 405, voltage-regulator diode D1 anode is connected with NMOS tube Q3 drain electrode, by voltage-regulator diode D1 negative electrode
It is connected with NPN type triode Q2 emitter stage.
In the present embodiment, the value of the parasitic capacitance C1 described in step 302 between PMOS grid and source electrode to be driven
For 1000pF~2000pF.Preferably, parasitic capacitance C1 between PMOS grid and source electrode to be driven described in step 302
Value is 1050pF.
According to formulaCalculate the current value i that voltage-regulator diode D1 is flowed through during PMOS Q1 is turned onD1, wherein,
Rated power when P is voltage-regulator diode D1 normal works, VD1For voltage-regulator diode D1 voltage stabilizing value；In the present embodiment, P=
0.5W, VD1=3.6V, according to formulaAnd round up and i is calculatedD1=0.14A；
According to formulaCalculating is begun to turn on to parasitic capacitance C1 from NMOS tube Q3 is charged to magnitude of voltage
Equal to Vi-VD1Required time ton1, wherein, ViFor the input voltage of switching power circuit where PMOS to be driven, C1 is
Parasitic capacitance between PMOS grid to be driven and source electrode；In the present embodiment, Vi=15V, VD1=3.6V, C1=1050pF,
iD1=0.14A, according to formulaAnd round up and t is calculatedon1=86ns；Therefore, the circuit turn-on
Time is 86ns.
Calculated more than, toff1=41ns, ton1=86ns, it is seen then that PMOS, which can be realized, quickly to be opened and turn off.
For example, opened as shown in figure 3, the PMOS drive circuit using active technology of releasing of the present invention is applied in BUCK
Close in converter, BUCK switch converters include PMOS Q1, inductance L, switching diode D3 and electric capacity C3, the inductance L's
Drain electrode of one end and switching diode the D3 negative electrode with PMOS Q1 is connected, and the other end of the inductance L becomes for BUCK switches
The output end of parallel operation and it is connected with electric capacity C3 one end, the anode of the switching diode D3 and the electric capacity C3 other end connect
Ground.
The operation principle of the BUCK switch converters is：During PMOS Q1 is turned on, switching diode D3 is anti-because bearing
End to voltage, external power source provides energy by inductance L to load, while gives inductance L energy storage；The phase is turned off in PMOS Q1
Between, switching diode D3 conducting afterflows, inductance L is to load and electric capacity C3 energy supplies, to maintain output voltage stabilization.
Fig. 4 A are oscillography when the present invention drives PMOS Q1 conductings using the PMOS drive circuit of active technology of releasing
Device tests the test waveform figure of grid and voltage between source electrodes, wherein, each small lattice of ordinate represent 2V voltages；Fig. 4 B are the present invention
When being turned off using the PMOS drive circuit driving PMOS Q1 of active technology of releasing electricity between grid and source electrode is tested with oscillograph
The test waveform figure of pressure, wherein, each small lattice of ordinate represent 2V voltages；Fig. 4 C are the present invention using active technology of releasing
Grid is tested with leaking the test waveform figure of voltage across poles with oscillograph during the driving PMOS Q1 conductings of PMOS drive circuit, its
In, each small lattice of ordinate represent 5V voltages；Fig. 4 D are that the present invention is driven using the PMOS drive circuit of active technology of releasing
Grid is tested with leaking the test waveform figure of voltage across poles with oscillograph when PMOS Q1 is turned off, wherein, each small lattice table of ordinate
Show 5V voltages；In Fig. 4 A~Fig. 4 D, abscissa represents that PMOS Q1 is turning on and off twinkling signal rising edge and trailing edge
Time, indulge in summary, the PMOS drive circuit of the invention using active technology of releasing, used voltage-regulator diode and had
Source bleed-off circuit carries out switch control to PMOS, improves PMOS coordinate representation voltage amplitudes；The input condition of test is：It is defeated
Enter voltage 15V, switch operating frequency 100KHz.The present invention is in contactor working frequency it can be seen from Fig. 4 A~Fig. 4 D
During 100KHz, the PMOS Q1 time that turns on and off is respectively less than 100ns.
In summary, PMOS drive circuit of the present invention has used voltage-regulator diode and active bleed-off circuit to enter PMOS
Row switch control, improves dynamic characteristic of the PMOS as switching tube, improves the switch efficiency of PMOS.Pass through two
Large current characteristic when pole pipe and triode ON, the electric charge in injection and extraction PMOS gate-source parasitic capacitance so that PMOS
The quick charge of pipe gate-source parasitic capacitance and electric discharge, the switch efficiency of PMOS is improved, reduce the switching loss of PMOS, together
When, reduce the control complexity of PMOS drive circuit.
It is described above, only it is presently preferred embodiments of the present invention, not the present invention is imposed any restrictions, it is every according to the present invention
Any simple modification, change and the equivalent structure change that technical spirit is made to above example, still fall within skill of the present invention
In the protection domain of art scheme.
Claims (7)
- A kind of 1. PMOS drive circuit using active technology of releasing, it is characterised in that：Including NPN type triode Q2, NMOS Pipe Q3, Schottky diode D2, electric capacity C2, resistance R1, resistance R2, resistance R3 and resistance R4, the grid of the NMOS tube Q3 with Resistance R3 one end connection, the other end of the resistance R3 are the input of outside PWM drive signal, the source of the NMOS tube Q3 Pole is grounded, and the drain electrode of the NMOS tube Q3 is connected with resistance R2 one end；The base stage of the NPN type triode Q2 passes through electric capacity C2 Drain electrode with the NMOS tube Q3 is connected, and the colelctor electrode of the NPN type triode Q2 and the cathode output end of external power source and is treated The source electrode connection of the PMOS of driving, the emitter stage of the NPN type triode Q2 and the resistance R2 other end and to be driven The grid connection of PMOS；The resistance R1 is attempted by between the colelctor electrode and emitter stage of the NPN type triode Q2, the electricity Resistance R4 is attempted by between the grid and source electrode of the NMOS tube Q3；The anode of the Schottky diode D2 and the NPN type three Pole pipe Q2 emitter stage connection, the negative electrode of the Schottky diode D2 are connected with the base stage of the NPN type triode Q2.
- 2. according to the PMOS drive circuit using active technology of releasing described in claim 1, it is characterised in that：Also include steady Diode D1 is pressed, the anode of the voltage-regulator diode D1 is connected with the drain electrode of the NMOS tube Q3, the voltage-regulator diode D1's Negative electrode is connected with the emitter stage of the NPN type triode Q2.
- 3. according to the PMOS drive circuit using active technology of releasing described in claim 1 or 2, it is characterised in that：It is described NPN type triode Q2 model ZTX651.
- 4. according to the PMOS drive circuit using active technology of releasing described in claim 1 or 2, it is characterised in that：It is described NMOS tube Q3 model IRF510.
- 5. according to the PMOS drive circuit using active technology of releasing described in claim 1 or 2, it is characterised in that：It is described Schottky diode D2 model SS14.
- 6. a kind of method for designing the PMOS drive circuit using active technology of releasing as claimed in claim 2, its feature exist In this method comprises the following steps：Step 1: NPN type triode Q2, the NMOS tube Q3 and Schottky diode D2, detailed process of selection suitable types are as follows：Step 101, the NPN type triode of model of the multiplication factor more than 100 is chosen as NPN type triode Q2；Step 102, selection electric current are less than 10A, and the NMOS tube of model of the drain-source breakdown voltage less than or equal to 100V is as NMOS Pipe Q3；Step 103, selection rated current are less than 0.5A, and the Schottky diode of model of the reverse recovery time less than 30ns is made For Schottky diode D2；Step 2: it is as follows to choose the resistance R1 of suitable parameters, resistance R2, resistance R3 and resistance R4, detailed process：Step 201, between 1k Ω~10k Ω choose resistance R1 and resistance R2 resistance；Step 202, according to formulaResistance R3 resistance is chosen, wherein, Vcc is PMOS place to be driven The supply voltage of pwm chip, I in switching power circuitmaxFor PWM in switching power circuit where PMOS to be driven The peak point current of control chip, t are NMOS tube Q3 switching delay time, and parasitisms of the C between NMOS tube Q3 grids and source electrode is electric Hold；Step 203, the resistance according to formula R4=100R3 selection resistance R4；Step 3: choosing the electric capacity C2 of suitable parameters, detailed process is as follows：Step 301, according to formulaCalculate collector current i during NPN type triode Q2 saturation conductionsC(Q2), Wherein, β(Q2)For NPN type triode Q2 multiplication factor, VC2The steady-state value and V that electric capacity C2 charges when being turned on for PMOS Q1C2= VD1-VD2, VD1For voltage-regulator diode D1 voltage stabilizing value, VD2For the voltage at Schottky diode D2 both ends；Step 302, according to formulaCalculating is begun to shut off to PMOS grid to be driven from NMOS tube Q3 Parasitic capacitance C1 between source electrode discharges into time t of the both end voltage needed for equal to zerooff1, wherein, ViFor PMOS to be driven The input voltage of place switching power circuit；Step 303, according to formulaChoose electric capacity C2 capacitance；Step 4: connection NPN type triode Q2, NMOS tube Q3, Schottky diode D2, electric capacity C2, resistance R1, resistance R2, electricity R3 and resistance R4 is hindered, forms PMOS high-speed switch drive circuit；Detailed process is as follows：Step 401, NMOS tube Q3 grid is connected with resistance R3 one end, using resistance R3 other end extraction wire as outer The input of portion's PWM drive signal, NMOS tube Q3 source ground connects NMOS tube Q3 drain electrode and resistance R2 one end Connect；Step 402, NPN type triode Q2 base stage is connected with electric capacity C2 one end, by electric capacity the C2 other end and NMOS tube Q3 drain electrode connection, by the cathode output end and PMOS to be driven of NPN type triode Q2 colelctor electrode and external power source Source electrode is connected, and NPN type triode Q2 emitter stage is connected with the resistance R2 other end and the grid of PMOS to be driven；Step 403, resistance R1 one end is connected with NPN type triode Q2 colelctor electrode, by resistance the R1 other end and NPN type Triode Q2 emitter stage connection, resistance R4 one end is connected with NMOS tube Q3 grid, by the resistance R4 other end and NMOS tube Q3 source electrode connection；Step 404, Schottky diode D2 anode is connected with NPN type triode Q2 emitter stage, by Schottky diode D2 negative electrode is connected with NPN type triode Q2 base stage；Step 405, voltage-regulator diode D1 anode is connected with NMOS tube Q3 drain electrode, by voltage-regulator diode D1 negative electrode with NPN type triode Q2 emitter stage connection.
- 7. in accordance with the method for claim 6, it is characterised in that：PMOS grid to be driven and source described in step 302 The parasitic capacitance C1 of interpolar value is 1000pF~2000pF.
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