CN107546121B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN107546121B CN107546121B CN201610490311.XA CN201610490311A CN107546121B CN 107546121 B CN107546121 B CN 107546121B CN 201610490311 A CN201610490311 A CN 201610490311A CN 107546121 B CN107546121 B CN 107546121B
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. The method comprises the following steps: providing a semiconductor substrate, and forming a high-k dielectric layer on the semiconductor substrate; forming a work function metal layer on the high-k dielectric layer; forming a diffusion barrier layer on the work function metal layer, wherein the diffusion barrier layer comprises a lamination layer consisting of a first diffusion barrier layer, a metal oxide barrier layer and a second diffusion barrier layer from bottom to top; and forming a gate electrode layer on the second diffusion barrier layer. According to the manufacturing method, the diffusion barrier layer with the sandwich structure of the first diffusion barrier layer, the metal oxide barrier layer and the second diffusion barrier layer is formed on the work function metal layer, and the diffusion barrier layer can effectively prevent subsequent impurity ions from diffusing to the lower film layer, so that the work function metal layer is well protected, and the yield and the performance of the device can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
With the continued scaling of CMOS devices, the development of three-dimensional designs such as fin field effect transistors (finfets) has been promoted. Compared with the existing planar transistor, the FinFET device has more excellent performance in the aspects of channel control, short channel effect reduction and the like. As devices evolve to 14nm technology nodes, FinFET devices become mainstream devices due to their superior performance.
Due to the band edge work function (band edge work function) and the excellent gap filling capability of the metal gate, a high-K metal gate is generally used in a semiconductor device to replace a conventional polysilicon gate structure. Particularly for NMOS devices, since most of the film layers in the metal gate stack are medium gap fill and upper band edge (TaN) materials, such as TiN, TiSiN, TaN, etc. Therefore, the work function metal layer and diffusion barrier layer of the NMOS device are very critical.
For example, it is widely used in conventional processesWith WF6Forming metal W as a gate electrode layer by Chemical Vapor Deposition (CVD) using a reaction gas, forming TiN or TiSiN as a diffusion barrier layer between the W gate electrode layer and the work function metal layer by Atomic Layer Deposition (ALD), and WF during chemical vapor deposition of the metal W6The F ions generated by the decomposition are easily diffused to the lower film layer, and once the diffusion barrier layer cannot block the diffusion of the F ions, the F ions are likely to diffuse into the work function barrier layer, so that the threshold voltage (Vt) of the device is negatively affected, and the performance and yield of the device are finally affected.
Therefore, it is necessary to provide a new method for manufacturing a semiconductor device to solve the above technical problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the deficiencies of the prior art, a first embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, and forming a high-k dielectric layer on the semiconductor substrate;
forming a work function metal layer on the high-k dielectric layer;
forming a diffusion barrier layer on the work function metal layer, wherein the diffusion barrier layer comprises a lamination layer consisting of a first diffusion barrier layer, a metal oxide barrier layer and a second diffusion barrier layer from bottom to top;
and forming a gate electrode layer on the second diffusion barrier layer.
Further, the material of the first diffusion barrier layer and the second diffusion barrier layer includes one or more of tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten, and tungsten nitride.
Further, the first and second diffusion barrier layers each comprise titanium nitride.
Further, the material of the metal oxide barrier layer includes titanium oxide.
Further, the sum of the thicknesses of the first diffusion barrier layer and the second diffusion barrier layer ranges from 20 angstroms to 30 angstroms.
Furthermore, the thickness range of the metal oxide barrier layer is 2-5 angstroms.
Furthermore, the total thickness of the laminated layer formed by the first diffusion impervious layer, the metal oxide impervious layer and the second diffusion impervious layer ranges from 25 angstroms to 35 angstroms.
Further, the thickness of the first diffusion barrier layer is between one third and two thirds of the sum of the thicknesses of the first diffusion barrier layer and the second diffusion barrier layer.
Further, the method of forming the metal oxide barrier layer includes: depositing a thin film layer which is made of the same material as the first diffusion barrier layer on the work function metal layer, oxidizing the thin film layer to form the metal oxide barrier layer, and taking the rest of the thin film layer as the first diffusion barrier layer.
Further, the oxidation treatment includes: and thermally oxidizing the thin film layer by using oxygen at the temperature of 300-400 ℃.
Further, a fin is formed on the semiconductor substrate, and the high-k dielectric layer is formed on a channel region of the fin.
Further, the material of the gate electrode layer comprises tungsten and WF6The gate electrode layer is formed by a chemical vapor deposition method as a reaction gas.
Further, after forming the high-k dielectric layer and before forming the work function metal layer, the method further includes: and forming a cover layer on the high-k dielectric layer.
Another aspect of the present invention also provides a semiconductor device, including:
a semiconductor substrate, a metal gate stack disposed on the semiconductor substrate, wherein the metal gate stack comprises a high-k dielectric layer, a work function metal layer, a diffusion barrier layer, and a gate electrode layer disposed in sequence from bottom to top,
the diffusion barrier layer comprises a lamination layer consisting of a first diffusion barrier layer, a metal oxide barrier layer and a second diffusion barrier layer from bottom to top.
Further, the material of the first diffusion barrier layer and the second diffusion barrier layer includes one or more of tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten, and tungsten nitride.
Further, the material of the metal oxide barrier layer includes titanium oxide.
Further, the sum of the thicknesses of the first diffusion barrier layer and the second diffusion barrier layer ranges from 20 angstroms to 30 angstroms.
Furthermore, the thickness range of the metal oxide barrier layer is 2-5 angstroms.
Furthermore, the total thickness of the laminated layer formed by the first diffusion impervious layer, the metal oxide impervious layer and the second diffusion impervious layer ranges from 25 angstroms to 35 angstroms.
Further, the thickness of the first diffusion barrier layer is between one third and two thirds of the sum of the thicknesses of the first diffusion barrier layer and the second diffusion barrier layer.
Further, a capping layer is disposed between the high-k dielectric layer and the work function metal layer.
In summary, according to the manufacturing method of the present invention, the diffusion barrier layer having the sandwich structure of the first diffusion barrier layer, the metal oxide barrier layer and the second diffusion barrier layer is formed on the work function metal layer, and the diffusion barrier layer can effectively block the subsequent diffusion of impurity ions (e.g., F ions) to the lower film layer, so as to protect the work function metal layer well, and can also reduce the thickness of the whole film stack to increase the gap filling window of the gate electrode material (e.g., metal W).
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 illustrates a cross-sectional view of an NMOS metal gate stack structure in a conventional process;
FIG. 2 is a cross-sectional view of a structure formed at a step associated with a method of fabricating a semiconductor device in accordance with one embodiment of the present invention;
FIG. 3 is a cross-sectional view of a diffusion barrier layer formed according to a fabrication method of the present invention;
fig. 4 is a schematic flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
The manufacturing method of the NMOS metal gate stack structure in the conventional process comprises the following main steps:
as shown in fig. 1, a semiconductor substrate (not shown) is provided, and a high-k dielectric layer 101, a capping layer 102, an N-type work function metal layer 103, a diffusion barrier layer 104, and a gate electrode layer 105 are sequentially formed on the semiconductor substrate.
WF is widely used in conventional technology6A metal W is deposited by a Chemical Vapor Deposition (CVD) method as a reaction gas as the gate electrode layer 105, and TiN or TiSiN is deposited by an Atomic Layer Deposition (ALD) method as the diffusion barrier layer 104 between the W gate electrode layer 105 and the work function metal layer 103.
The threshold voltage (Vt) of an NMOS is sensitive to the thickness of TiN or TiSiN, and if the diffusion barrier layer 104 is very thin (e.g., < 40 angstroms), the diffusion barrier layer 104 will not block the diffusion of F ions from the decomposed WF, so that the threshold voltage (Vt) of an NMOS device will increase significantly6Deposition process of depositing metal W. In additionOne problem is that if there is a vacuum break between the work function metal layer 103 and the diffusion barrier layer 104 and the NMOS work function metal layer is oxidized, the threshold voltage of the NMOS will decrease, a tendency that cannot be explained by the metal oxide film work function itself, most likely due to diffusion of impurities (e.g., F ions) from W.
NMOS threshold voltage modulation of FinFET devices is a challenge in the industry because it is difficult to find low band edge (lowband edge) work function metal materials, and various approaches have been tried to improve on this. One approach is to have a thicker TiN or TiSiN diffusion barrier layer (e.g. > 40 angstroms) to avoid diffusion of F ions into the work function metal layer. However, this approach results in higher resistivity and for subsequent WF6Gap filling of the chemical vapor deposition metal W presents challenges. Alternatively, instead of WF, WC without F is used6Metal W is chemical vapor deposited as a reactive gas, but this method introduces C into the film, making the resistivity of the gate higher, and in addition, the production cost is increased due to the use of new methods and materials. There is also a method of providing an oxide film layer on the NMOS work function metal layer, but this method consumes the effective NMOS work function metal layer and also causes an increase in the total thickness of the film layer.
Therefore, in view of the above problems, the present invention proposes a method for manufacturing a semiconductor device, as shown in fig. 4, which includes the following main steps:
in step S401, a semiconductor substrate is provided, and a high-k dielectric layer is formed on the semiconductor substrate;
in step S402, forming a work function metal layer on the high-k dielectric layer;
in step S403, forming a diffusion barrier layer on the work function metal layer, wherein the diffusion barrier layer includes a stack of a first diffusion barrier layer, a metal oxide barrier layer, and a second diffusion barrier layer from bottom to top;
in step S404, a gate electrode layer is formed on the second diffusion barrier layer.
According to the manufacturing method, the diffusion barrier layer comprising the first diffusion barrier layer, the metal oxide barrier layer and the second diffusion barrier layer is formed, so that the downward diffusion of F ions generated in the deposition process of the gate electrode layer can be effectively avoided, the work function metal layer is well protected, the gap filling window of the gate electrode layer is increased, and the yield and the performance of the device are improved.
Example one
Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention is described with reference to fig. 2 and 3, in which fig. 2 is a cross-sectional view of a structure formed in a relevant step of the method for manufacturing a semiconductor device according to an embodiment of the present invention; fig. 3 is a cross-sectional view of a diffusion barrier layer formed according to a fabrication method of the present invention.
First, as shown in fig. 2, a semiconductor substrate (not shown) is provided, on which a high-k dielectric layer 201 is formed.
Specifically, the semiconductor substrate may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. Various wells, shallow trench isolation structures for defining active regions, and the like are also formed in the semiconductor substrate.
Illustratively, the semiconductor device is a FinFET device, and a fin (not shown) is formed on a surface of the semiconductor substrate, a portion of the fin serving as a channel region of the semiconductor device, the fin having a columnar structure, such as a rectangular parallelepiped shape, standing on a surface of the semiconductor substrate.
Illustratively, the method of forming the fin may include the steps of:
forming a patterned mask layer on the surface of the semiconductor substrate, wherein the patterned mask layer defines the pattern of the fin and comprises the width, the length, the position and the like of the fin; and etching the semiconductor substrate by taking the patterned mask layer as a mask to form the fin. The mask layer may generally comprise any of several mask materials, including but not limited to: a hard mask material and a photoresist mask material. In this embodiment, the mask layer comprises a hard mask material. The hard mask material may be a material known to those skilled in the art as a hard mask, and preferably, the hard mask material is silicon nitride, and the hard mask material may also be a stack of a silicon nitride material layer and other suitable films. The fin material may be Si, SiGe, Ge, or a III-V material such as gallium arsenide.
Illustratively, a high-k dielectric layer 201 is formed on a region of the surface of the semiconductor substrate where a metal gate stack is to be formed.
In one example, when a fin is formed on the semiconductor substrate, the high-k dielectric layer 201 is formed on a channel region of the fin.
High-k dielectric layer 201 typically has a k value (dielectric constant) of 3.9 or more, and is composed of hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and the like, preferably hafnium oxide, zirconium oxide, or aluminum oxide. The high-k dielectric layer 201 may be formed using a suitable process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). The thickness of high-k dielectric layer 201 ranges from 10 angstroms to 30 angstroms.
In one example, a step of forming a capping layer 202 on the high-k dielectric layer 201 is also included.
The material of the capping layer 202 may be La2O3、Al2O3、Ga2O3、In2O3MoO, Pt, Ru, TaCNO, Ir, TaC, MoN, WN, TixN1-x, TiSiN, TaN, or other suitable thin film layers. The capping layer 202 may be deposited by a suitable process such as CVD, ALD, PVD or the like, and preferably is deposited by atomic layer deposition. In this embodiment, the material of the capping layer 202 is preferably TiN.
Next, with continued reference to fig. 2, a work function metal layer 203 is formed on the high-k dielectric layer 201.
When the capping layer 202 is formed, the work function metal layer 203 is located on the capping layer 202.
In one example, for an NMOS device, the work function metal layer 203 is an N-type work function metal layer (NWF), and the material of the N-type work function metal layer may be selected from, but not limited to, TaC, Ti, Al, TixAl1-x, TaAlC, TiAlC, or other suitable thin film layers.
The work function metal layer 203 may be formed using a suitable process such as CVD, ALD, or PVD. The thickness of the N-type workfunction metal layer ranges from 10 to 80 angstroms.
Next, as shown in fig. 2 and fig. 3, a diffusion barrier layer 204 is formed on the work function metal layer 203, wherein the diffusion barrier layer 204 includes a stack of a first diffusion barrier layer 2041, a metal oxide barrier layer 2042, and a second diffusion barrier layer 2043 from bottom to top.
Specifically, the material of the first diffusion barrier layer 2041 and the second diffusion barrier layer 2043 includes one or more of tantalum, tantalum nitride, titanium nitride, zirconium titanium nitride, tungsten, and tungsten nitride. Alternatively, the first diffusion barrier layer 2041 and the second diffusion barrier layer 2043 may be made of different materials, or may be made of the same material, and may each include titanium nitride (TiN), for example.
Materials of metal oxide barrier layer 2042 include, but are not limited to, tantalum oxide (Ta)2O5) Titanium oxide (TiO)2) Tungsten oxide, and the like, and further, the material of the metal oxide barrier layer 2042 includes titanium oxide.
In one example, the first and second diffusion barrier layers 2041, 2043 each comprise titanium nitride and the material of the metal oxide barrier layer 2042 comprises titanium oxide.
The first diffusion barrier layer 2041 and the second diffusion barrier layer 2043 may be formed using any deposition method known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, and the like.
The first diffusion barrier layer 2041, the metal oxide barrier layer 2042, and the second diffusion barrier layer 2043 may also be formed in sequence by a deposition method, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like.
In this embodiment, the first diffusion barrier layer 2041 and the second diffusion barrier layer 2043 are preferably formed by using an atomic layer deposition method.
In one example, titanium nitride is formed as the first diffusion barrier layer 2041 and the second diffusion barrier layer 2043 using atomic layer deposition, a semiconductor substrate already containing a work function metal layer is placed within a deposition chamber, and the semiconductor substrate is contacted with a Ti precursor and an ammonia source precursor, which may be a plasma, gas, liquid, or solid at ambient temperature and pressure, to form a titanium nitride layer. However, within the ALD chamber, the precursor is in a volatile state. Typically, the titanium precursor may comprise TiCl4、TiBr4、TiI4、TiF4Tetradimethyl-aminotitanium, but is not particularly limited. In addition, any suitable ammonia source precursor may be used. Examples include ammonia or N2H2Or N2H4But is not particularly limited.
In one example, a method of forming the metal oxide barrier layer 2042 includes: for example, a titanium nitride thin film layer may be formed on the work function metal layer 203 by using an atomic layer deposition method, and then the titanium nitride thin film layer may be subjected to an oxidation treatment to form a metal oxide barrier layer 2042 including a titanium oxide material, and the remaining non-oxidized titanium nitride thin film layer at the bottom layer may be used as the first diffusion barrier layer 2041, and further, the oxidation treatment includes: and thermally oxidizing the thin film layer by using oxygen at the temperature of 300-400 ℃.
Preferably, the thickness of the first diffusion barrier layer 2041 is between one third and two thirds of the sum of the thicknesses of the first diffusion barrier layer 2041 and the second diffusion barrier layer 2043.
The sum of the thicknesses of the first diffusion barrier layer 2041 and the second diffusion barrier layer 2043 may be in a range of 20 to 30 angstroms, which is merely an example and may be appropriately adjusted according to a specific device.
Further, the thickness of the metal oxide barrier layer 2042 is in a range of 2 to 5 angstroms.
In addition, the total thickness of the stack of the first diffusion barrier layer 2041, the metal oxide barrier layer 2042 and the second diffusion barrier layer 2043 can be controlled to be 25 to 35 angstroms, and the total thickness can be substantially equal to the thickness of the diffusion barrier layer in the prior art or smaller than the thickness in the prior art.
Subsequently, with continued reference to fig. 2, a gate electrode layer 205 is formed on the second diffusion barrier layer 2043 to finally form a metal gate stack structure including the high-k dielectric layer 201, the work function metal layer 203, the first diffusion barrier layer 2041, the metal oxide barrier layer 2042, the second diffusion barrier layer 2043, and the gate electrode layer 205.
The material of the gate electrode layer 205 can be selected to be, but is not limited to, Al, W, or other suitable thin film layers. The gate electrode layer 205 can be formed by a suitable process such as CVD, ALD, or PVD.
In one example, a metal W is formed as the gate electrode layer 205 using a chemical vapor deposition process. Wherein the CVD process uses WF6Decomposing WF as a reaction gas6A metal W is deposited, wherein during this process F ions are also dissociated.
Since the diffusion barrier layer formed in the foregoing step includes a stack of the first diffusion barrier layer 2041, the metal oxide barrier layer 2042, and the second diffusion barrier layer 2043, the metal oxide barrier layer 2042 located in the middle can have a good blocking effect on F ions, and thus, the work function metal layer 203 can be protected from the F ions.
Thus, the introduction of the main steps of the method for manufacturing the semiconductor device of the present invention is completed, and other process steps are required for the complete device manufacturing, which is not described herein again.
The manufacturing method of the invention is not only suitable for the NMOS device, but also suitable for the manufacture of PMOS devices, and the manufacturing process refers to the NMOS device.
In summary, according to the manufacturing method of the present invention, the diffusion barrier layer having the sandwich structure of the first diffusion barrier layer, the metal oxide barrier layer and the second diffusion barrier layer is formed on the work function metal layer, and the diffusion barrier layer can effectively block the diffusion of F ions to the lower film layer, so as to provide a good protection effect for the work function metal layer, and can also reduce the thickness of the whole film stack to increase the gap filling window of the gate electrode material (e.g., metal W).
Example two
The embodiment also provides a semiconductor device obtained by the manufacturing method in the first embodiment, and the semiconductor device may be a FinFET device.
Illustratively, as shown in fig. 2, the semiconductor device of the present invention includes: a semiconductor substrate (not shown) having fins formed on a surface thereof.
Specifically, the semiconductor substrate may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. Various wells, shallow trench isolation structures for defining active regions, and the like are also formed in the semiconductor substrate.
The semiconductor device comprises a semiconductor substrate, wherein a fin is formed on the surface of the semiconductor substrate, a part of the fin is used as a channel region of the semiconductor device, and the fin is of a columnar structure such as a cuboid shape and the like which is erected on the surface of the semiconductor substrate. The fin material may be Si, SiGe, Ge, or a III-V material such as gallium arsenide.
Further comprising: and the metal gate stack is positioned on the semiconductor substrate and covers the channel region of the fin, wherein the metal gate stack comprises a high-k dielectric layer 201, a work function metal layer 203, a diffusion barrier layer 204 and a gate electrode layer 205 which are sequentially arranged from bottom to top, and the diffusion barrier layer 204 comprises a stack of a first diffusion barrier layer 2041, a metal oxide barrier layer 2042 and a second diffusion barrier layer 2043 from bottom to top.
Further, a capping layer 202 is further disposed between the high-k dielectric layer 201 and the work function metal layer 203.
High-k dielectric layer 201 typically has a k value (dielectric constant) of 3.9 or more, and is composed of hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and the like, preferably hafnium oxide, zirconium oxide, or aluminum oxide. The thickness of high-k dielectric layer 201 ranges from 10 angstroms to 30 angstroms.
The material of the capping layer 202 may be La2O3、Al2O3、Ga2O3、In2O3MoO, Pt, Ru, TaCNO, Ir, TaC, MoN, WN, TixN1-x, TiSiN, TaN, or other suitable thin film layers. In this embodiment, the material of the capping layer 202 is preferably TiN.
In one example, for an NMOS device, the work function metal layer 203 is an N-type work function metal layer (NWF), and the material of the N-type work function metal layer may be selected from, but not limited to, TaC, Ti, Al, TixAl1-x, TaAlC, TiAlC, or other suitable thin film layers. The thickness of the N-type workfunction metal layer ranges from 10 to 80 angstroms.
Specifically, the material of the first diffusion barrier layer 2041 and the second diffusion barrier layer 2043 includes one or more of tantalum, tantalum nitride, titanium nitride, zirconium titanium nitride, tungsten, and tungsten nitride. Alternatively, the first diffusion barrier layer 2041 and the second diffusion barrier layer 2043 may be made of different materials, or may be made of the same material, and may each include titanium nitride (TiN), for example.
Materials of metal oxide barrier layer 2042 include, but are not limited to, tantalum oxide (Ta)2O5) Titanium oxide (TiO)2) Tungsten oxide, and the like, and further, the material of the metal oxide barrier layer 2042 includes titanium oxide.
In one example, the first and second diffusion barrier layers 2041, 2043 each comprise titanium nitride and the material of the metal oxide barrier layer 2042 comprises titanium oxide.
Preferably, the thickness of the first diffusion barrier layer 2041 is between one third and two thirds of the sum of the thicknesses of the first diffusion barrier layer 2041 and the second diffusion barrier layer 2043.
The sum of the thicknesses of the first diffusion barrier layer 2041 and the second diffusion barrier layer 2043 may be in a range of 20 to 30 angstroms, which is merely an example and may be appropriately adjusted according to a specific device.
Further, the thickness of the metal oxide barrier layer 2042 is in a range of 2 to 5 angstroms.
In addition, the total thickness of the stack of the first diffusion barrier layer 2041, the metal oxide barrier layer 2042 and the second diffusion barrier layer 2043 can be controlled to be 25 to 35 angstroms, and the total thickness can be substantially equal to the thickness of the diffusion barrier layer in the prior art or smaller than the thickness in the prior art.
The material of the gate electrode layer 205 can be selected to be, but is not limited to, Al, W, or other suitable thin film layers. The gate electrode layer 205 can be formed by a suitable process such as CVD, ALD, or PVD.
In one example, a metal W is formed as the gate electrode layer 205 using a chemical vapor deposition process. Wherein the CVD process uses WF6Decomposing WF as a reaction gas6A metal W is deposited, wherein during this process F ions are also dissociated.
The formed diffusion barrier layer includes a stack of the first diffusion barrier layer 2041, the metal oxide barrier layer 2042, and the second diffusion barrier layer 2043, and the metal oxide barrier layer 2042 located in the middle can have a good blocking effect on F ions, so that the work function metal layer 203 can be protected from the F ions.
In summary, the semiconductor device of the present invention includes the first diffusion barrier layer, the metal oxide barrier layer, and the diffusion barrier layer of the second diffusion barrier layer sandwich structure, and the diffusion barrier layer can effectively block diffusion of F ions to the lower film layer, so as to provide a good protection effect for the work function metal layer, and can also reduce the thickness of the whole film stack to increase the gap filling window of the gate electrode material (e.g., metal W).
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (21)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, and forming a high-k dielectric layer on the semiconductor substrate;
forming a work function metal layer on the high-k dielectric layer;
forming a diffusion barrier layer on the work function metal layer, wherein the diffusion barrier layer comprises a lamination layer consisting of a first diffusion barrier layer, a metal oxide barrier layer and a second diffusion barrier layer from bottom to top;
forming a gate electrode layer on the second diffusion barrier layer;
the diffusion barrier layer protects the work function metal layer from ion downward diffusion generated during the deposition process for forming the gate electrode.
2. The method of manufacturing of claim 1 wherein the material of the first diffusion barrier layer and the second diffusion barrier layer comprises one or more of tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten, and tungsten nitride.
3. The method of manufacturing of claim 1 wherein the first diffusion barrier layer and the second diffusion barrier layer each comprise titanium nitride.
4. The method of manufacturing of claim 1, wherein the material of the metal oxide barrier layer comprises titanium oxide.
5. The method of manufacturing according to claim 1, wherein a sum of thicknesses of the first diffusion barrier layer and the second diffusion barrier layer ranges from 20 to 30 angstroms.
6. The method of claim 1, wherein the metal oxide barrier layer has a thickness in a range of 2 to 5 angstroms.
7. The method of manufacturing of claim 1, wherein a total thickness of the stack of the first diffusion barrier layer, the metal oxide barrier layer, and the second diffusion barrier layer is in a range of 25 to 35 angstroms.
8. The method of manufacturing of claim 1, wherein the thickness of the first diffusion barrier layer is between one-third and two-thirds of the sum of the thicknesses of the first diffusion barrier layer and the second diffusion barrier layer.
9. The method of manufacturing of claim 1, wherein forming the metal oxide barrier layer comprises: depositing a thin film layer which is made of the same material as the first diffusion barrier layer on the work function metal layer, oxidizing the thin film layer to form the metal oxide barrier layer, and taking the rest of the thin film layer as the first diffusion barrier layer.
10. The manufacturing method according to claim 9, wherein the oxidation treatment includes: and thermally oxidizing the thin film layer by using oxygen at the temperature of 300-400 ℃.
11. The method of manufacturing of claim 1, wherein a fin is formed on the semiconductor substrate, the high-k dielectric layer being formed on a channel region of the fin.
12. The method according to claim 1, wherein a material of the gate electrode layer includes tungsten, and WF is used as the gate electrode layer6The gate electrode layer is formed by a chemical vapor deposition method as a reaction gas.
13. The method of manufacturing of claim 1, wherein after forming the high-k dielectric layer and before forming the work function metal layer, further comprising: and forming a cover layer on the high-k dielectric layer.
14. A semiconductor device, comprising:
a semiconductor substrate, a metal gate stack disposed on the semiconductor substrate, wherein the metal gate stack comprises a high-k dielectric layer, a work function metal layer, a diffusion barrier layer, and a gate electrode layer disposed in sequence from bottom to top,
the diffusion barrier layer comprises a lamination layer consisting of a first diffusion barrier layer, a metal oxide barrier layer and a second diffusion barrier layer from bottom to top;
the diffusion barrier layer protects the work function metal layer from ion downward diffusion generated during the deposition process for forming the gate electrode.
15. The semiconductor device of claim 14, wherein the material of the first diffusion barrier layer and the second diffusion barrier layer comprises one or more of tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten, and tungsten nitride.
16. The semiconductor device of claim 14, wherein a material of the metal oxide barrier layer comprises titanium oxide.
17. The semiconductor device according to claim 14, wherein a sum of thicknesses of the first diffusion barrier layer and the second diffusion barrier layer is in a range of 20 to 30 angstroms.
18. The semiconductor device of claim 14, wherein the metal oxide barrier layer has a thickness in the range of 2 to 5 angstroms.
19. The semiconductor device of claim 14, wherein a total thickness of the stack of the first diffusion barrier layer, the metal oxide barrier layer, and the second diffusion barrier layer is in a range of 25 to 35 angstroms.
20. The semiconductor device of claim 14, in which a thickness of the first diffusion barrier layer is between one-third and two-thirds of a sum of thicknesses of the first diffusion barrier layer and the second diffusion barrier layer.
21. The semiconductor device of claim 14, wherein a capping layer is further disposed between the high-k dielectric layer and the work function metal layer.
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| CN105448831A (en) * | 2014-08-05 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | High-K metal gate CMOS device and forming method thereof |
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