CN107545081A

CN107545081A - A kind of RF spiral inductances high accuracy lumped parameter model and parameter extracting method

Info

Publication number: CN107545081A
Application number: CN201610467274.0A
Authority: CN
Inventors: 张炯; 蒋乐乐; 程玉华
Original assignee: Shanghai Research Institute of Microelectronics of Peking University
Current assignee: Shanghai Research Institute of Microelectronics of Peking University
Priority date: 2016-06-24
Filing date: 2016-06-24
Publication date: 2018-01-05

Abstract

The present invention proposes a kind of high-precision the dynamic impedance model and parameter extracting method of spiral inductance widely used in RF IC.Its key step includes：（1）The Mathematical Models of on-chip spiral inductor.Accurate RF spiral inductances RLC lumped parameter models are established, include related RF ghost effects such as eddy current effect, Kelvin effect, substrate loss etc..（2）Its physical model is established according to technology library, and the emulation of S parameter is carried out to domain.（3）Using the component parameters in the S parameter extraction inductance RLC lumped parameter models of simulation.The beneficial effects of the invention are as follows, the various ghost effects of on-chip inductor under high frequency situations can be considered in model, and component parameters are extracted so as to establish high-precision inductance lumped parameter model by the S parameter of numerical simulation, this model can easily carry out being put into the sequential and simulation in the frequency-domain for being used for doing circuit in the eda softwares such as SPICE.

Description

A kind of RF spiral inductances high accuracy lumped parameter model and parameter extracting method

Technical field

The invention belongs to the research of the model method in RFIC CMOS IC design.Specifically related to a kind of spiral electricity Feel high-precision dynamic impedance model and its parameter extracting method.Background technology

The fast development of radio communication has promoted the design of RF IC, with the progress of technique, CMOS technique transistors Cut-off frequency become more and more higher, compared with GaAs techniques, CMOS techniques are all occupied significant excellent in terms of price, power consumption Gesture.Can integrated simulation and digital circuit in CMOS technology, therefore the integrated of higher degree can be realized simultaneously.It is so that all Transceiver section, either numeral or simulation, radio frequency can use standard CMOS technique realize.On-chip inductor is it In the integrated circuit modules such as key element, high-performance voltage controlled oscillator, low-noise amplifier and passive filter be required for using To the inductance element of high-quality.Due to the characteristic of semiconductor of silicon substrate, substrate loss, silicon base spiral electricity are inevitably introduced Sense is to realize the major way of on-chip inductor, and it is made it have using the metal interconnecting wires in integrated circuit around curl The characteristic of inductance.In standard CMOS technique, because the metal connecting line resistance for forming spiral inductance is higher, high frequency silicon-based substrate Loss it is larger so that the quality factor of silicon base spiral inductance are not universal high.And spiral inductance is in complicated electromagnetic field environment Under, its model is established and emulation is also extremely difficult.Due to lacking simple and accurate component parameters formula, for spiral inductance Design and optimization obviously as one of main obstacle of RF circuit designs.On-chip inductor characteristic can accurately be characterized by working out Lumped parameter model can help we shorten design time and optimization performance.

The content of the invention

The present invention proposes a kind of high-precision lumped parameter of on-chip spiral inductor widely used in RF IC Model and parameter extracting method.Common on-chip spiral inductor is as shown in figure 1, typically by top metal spiral coiling, by secondary High-rise metal draws inner port.The lumped parameter model of invention can accurately characterize on-chip inductor characteristic, be easy in electricity Time domain and simulation in the frequency-domain are carried out in road, Radio Frequency Engineer can be helped to shorten design time and optimization performance.Concrete technical scheme It is as follows：

（1）Establish the spiral inductance high accuracy lumped parameter model for including RF associated parasitic effects.The model integrally includes embodying The series inductance and series resistance of on-chip inductor, the inductance and resistance of Kelvin effect are embodied, embody the inductance and electricity of eddy current effect Resistance, embody the electric capacity of insulating medium layer and embody the electric capacity and resistance of bulk silicon substrate.The component connection structure of whole circuit As shown in Figure 2：

（a）The series inductance and series resistance of on-chip inductor include Fig. 2 shown in input/output port between directly series connection company Resistance Rs1, inductance Ls and the resistance Rs2 connect.Embody the inductance characteristic of on-chip inductor and the resistance characteristic of wire, series inductance Series resistance schematic diagram is as shown in Figure 3.

（b）The inductive resistance of Kelvin effect include shown in Fig. 2 in inductance Lk1, resistance Rk1 series connection block and inductance Lk2, electricity Hinder Rk2 series connection block it is in parallel with resistance Rs1, Rs2, embody on-chip inductor in high frequency the inductance caused by Kelvin effect with The change of resistance.

（c）The electricity that the inductive resistance of eddy-current loss has mutual inductance to act in including shown in Fig. 2 with on-chip inductor series inductance Ls Feel Le, also embody the Re of eddy-current loss, eddy current effect schematic diagram is as shown in Figure 4.

d）Electric capacity be can not ignore in high frequency, mainly there is the electric capacity between coil and silicon substrate, inductance lead-out wire and power supply Electric capacity between ground, and silicon substrate parasitic capacitance and conducting resistance, schematic diagram are as shown in Figure 4.

（2）The physical model of on-chip inductor is set up according to technique library file, and draws domain, S is carried out using eda software The emulation of parameter；

（3）By numerical computations, in the tuning range of given component parameters, the S parameter of lumped parameter model is calculated, is found Component values when being overlapped with the analogue value, so as to the component parameters in extraction model.

Brief description of the drawings

Fig. 1：Common on-chip inductor structure.

Fig. 2：On-chip inductor dynamic impedance model.

Fig. 3：On-chip inductor series inductance series resistance source.

Fig. 4：Silicon substrate eddy-current loss and parasitic parameter.

Fig. 5：Domain S parameter contrasts with lumped parameter model S parameter.

Embodiment

Technical scheme is described further with embodiment below in conjunction with the accompanying drawings.

（1）Establish on-chip inductor lumped parameter model as shown in Figure 2.

（2）The on-chip inductor shown in Fig. 1 is set up according to technique library file such as ADS MOMENTUM using simulation software Physical model, the model include the correlatives such as the thickness, dielectric constant, resistivity of silicon substrate, insulating medium layer, metal level etc. Manage characteristic.Used here as top metal coiling inductance, secondary top-level metallic is used for bridging.

（3）The domain of on-chip inductor is planned according to required inductance value size using simulation software, designs one here The small inductor being operated under 60GHz, after painting domain, emulation obtains the S parameter of inductance.

（4）Using simulation software, wide band lumped parameter exponential model is built in the way of Fig. 2, sets each element to adjust Humorous scope, then tunes the component value of lumped parameter model automatically, while compares the S parameter and version of lumped parameter model emulation Figure simulates the S parameter come, until both S parameters are gradually overlapped as shown in figure 5, lumped parameter model can now represents The characteristic of on-chip inductor in domain.

（5）The wide band lumped parameter exponential model of on-chip inductor can be put into and be used for the sequential and frequency of doing circuit in SPICE instruments Domain simulates.

For above-described embodiment only to be made a detailed explanation to present disclosure, its object is to allow the technology of this area Personnel are familiar with the particular content of the present invention and implemented according to this.Any equivalence changes that all Spirit Essences without departing from the present invention are done Or modification, it should all belong within protection scope of the present invention.

Claims

1. a kind of silicon substrate on-chip spiral inductor high accuracy lumped parameter model and its parameter element extracting method, it is characterised in that bag Include following steps：（1）Establish the spiral inductance lumped parameter model for including RF associated parasitic effects；The model includes embodying on piece The series inductance and series resistance of inductance, the inductance and resistance of Kelvin effect are embodied, embody the inductance and resistance of eddy current effect, body The electric capacity of existing insulating medium layer and the electric capacity and resistance for embodying bulk silicon substrate；（2）Set up according to technique library file on piece The physical model of inductance, and domain is drawn, the emulation of S parameter is carried out using eda software；（3）By numerical simulation, what is given In the tuning range of component parameters, the S parameter of lumped parameter model is calculated, by identical with the analogue value, so that the S from simulation Component parameters in parameter in extraction model.

2. on-chip inductor series inductance and series resistance are embodied as claimed in claim 1, it is characterised in that in input/output terminal A resistance, an inductance and a resistance have been sequentially connected in series on mouth straight line branch road.

3. the inductance and resistance of Kelvin effect are embodied as claimed in claim 1, it is characterised in that the inductance and electricity of a pair of series Hinder two resistor coupled in parallel with being mentioned in claim 2 respectively.

4. the inductance and resistance of eddy current effect are embodied as claimed in claim 1, it is characterised in that inductance and resistance head and the tail are connected in A ring is formed together, and this inductance has interaction, mutual inductance k with the series inductance in claim 2.

5. the electric capacity of insulating medium layer is embodied as claimed in claim 1, it is characterised in that the underface of on-chip inductor serves as a contrast with silicon Parasitic capacitance between bottom be present, on-chip inductor, which is drawn between the line and ground wire of port, has parasitic capacitance.

6. the electric capacity and resistance of bulk silicon substrate as claimed in claim 1, it is characterised in that in bulk silicon substrate and ground Parasitic capacitance in parallel and resistance between line be present.