CN107533443A - Multiple are provided in the semiconductor device - Google Patents
Multiple are provided in the semiconductor device Download PDFInfo
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- CN107533443A CN107533443A CN201680025770.9A CN201680025770A CN107533443A CN 107533443 A CN107533443 A CN 107533443A CN 201680025770 A CN201680025770 A CN 201680025770A CN 107533443 A CN107533443 A CN 107533443A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/068—Hybrid storage device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
- G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Abstract
In one embodiment, a kind of system includes：First radical space associated with the first radical space identifier and including at least one first host-processor and first agent, at least one first host-processor and first agent are associated with the first radical space identifier；Second radical space associated with the second radical space identifier and including at least one second host-processor and second agent, at least one second host-processor and second agent are associated with the second radical space identifier；And shared construction, it is used to couple the first radical space and the second radical space, and the affairs are routed to first radical space or second radical space by the radical space field that shared construction is based at least partially on affairs.It is described and claimed other embodiments.
Description
The cross reference of related application
This application claims it is entitled " PROVIDING MULTIPLE ROOTS IN A SEMICONDUCTOR DEVICE ",
With Michael T.Klinglesmith, Chang Yong Kang, Robert De Gruijl, Ioannis T.Schoinas,
Darren Abramson and Khee Wooi Lee name, in the U.S. Provisional Patent Application submitted on June 4th, 2015
No.62/170, the 905 and U.S. Patent application No.14/880 that is submitted on October 12nd, 2015,443 priority, its disclosure
Content is incorporated herein by reference.
Background technology
Main flow processor chips (high-performance and low-power consumption part) are integrated with additional function more and more, such as figure,
Display engine, security engine, PCIeTMPort (that is, quickly interconnects (PCI Express according to peripheral assemblyTM(PCIeTM)) specification
(itself and related specifications are hereinafter referred to as PCIe to basic norm version 2 .0 (issuing for 2007)TMSpecification) port and other
Based on PCIeTMPeripheral components, while keep the tradition of the device to meeting PCI specification to support, such as periphery component interconnection
(PCI) local bus specification 3.0 editions (issues) (itself and related specifications are hereinafter referred to as PCI specification) for 2002).
Due to being needed from the different of server, desktop computer, movement, embedded, super movement and mobile internet device part
Ask, this design is highly split.Different market tries to use single-chip on-chip system (SoC) solution, and it will processing
At least some in device core, Memory Controller, i/o controller and the specific acceleration components of other parts are combined to
On one single chip.However, due to being difficult to integrate different intellectual properties (IP) block on a single chip, setting for these features is accumulated
The appearance of meter is very slow.This is especially true, because IP blocks can have, various requirement and design are unique, and may need
Many special wires, communication protocol etc. allow it to be incorporated to SoC.Therefore, each SoC or other of exploitation is advanced partly leads
Body device needs substantial amounts of design complexity and customization, and different IP blocks are incorporated into individual devices.Here it is in this way, because
Usually require to redesign for given IP blocks to adapt to given SoC interface and signaling request.
Brief description of the drawings
Fig. 1 is the block diagram of basic interconnection architecture according to an embodiment of the invention.
Fig. 2 is the block diagram of the further detail below of interconnection architecture according to an embodiment of the invention.
Fig. 3 is SoC according to embodiments of the present invention high level block diagram.
Fig. 4 is the block diagram of system according to another embodiment of the present invention.
Fig. 5 is the block diagram of sideband interconnection according to an embodiment of the invention.
Fig. 6 is the block diagram united according to more root systems of embodiment.
Fig. 7 is the block diagram united according to more root systems of another embodiment.
Fig. 8 is the block diagram united according to more root systems of another embodiment.
Fig. 9 is the more detailed block diagram of a SoC according to an embodiment of the invention part.
Figure 10 is another SoC according to an embodiment of the invention block diagram.
Figure 11 is the flow chart of method according to embodiments of the present invention.
Figure 12 is the block diagram for the example system that can use embodiment.
Figure 13 is the block diagram of representative computer system.
Embodiment
Embodiment can be used for many different types of systems.As an example, embodiments described herein can be tied
Semiconductor devices (such as the processor that can be manufactured on single semiconductor element or other semiconductor devices) is closed to use.
In particular implementation, the device can include various isomorphisms and/or isomery processing agency (processing agents)
On-chip system (SoC) or other advanced processors or chipset, and the additional component of such as networked components etc (such as are route
Device, controller, bridge joint device, device, memory etc.).
Some embodiments can be used for according to given specification (such as the integrated system-on-chip issued by semiconductor maker
Construct (IOSF) specification) design semiconductor devices in, with provide be used for by intellectual property (IP) block be attached to chip (including
SoC interconnection agreement on the standardization tube core in).Such IP blocks can be different types of, including general processor, such as have
Sequence or out-of-order core, fixed-function unit, graphics processor, I/O control, display controller, Media Processor etc..Pass through
Interconnection agreement is standardized, it is achieved thereby that widely using the framework of IP agencies in different types of chip.Therefore, semiconductor system
Make business not only can effectively design different types of chip throughout various customers, and can also be made by specification
The logical design of such as IP agencies etc can be incorporated to such chip by tripartite.In addition, pass through many for interconnection agreement
Aspect provides multiple options, has effectively adapted to reusing for design.Although describe implementation herein in conjunction with the IOSF specifications
Example, it should be appreciated that the scope of the present invention is not limited to this aspect, and embodiment can be used for many different types of systems
In.
Referring now to Figure 1, show the block diagram of basic interconnection architecture according to an embodiment of the invention.As shown in fig. 1,
System 10 can be a part for on-chip system or any other semiconductor devices, for example, highly integrated processor complex or
Integrated I/O hub, and including the construction 20 as the interconnection between various parts.In the embodiment shown, these parts
Including IP agencies 30 and 40, it can be independent IP blocks, to provide such as computing capability, graph ability, media processing capacity
Deng various functions.In one embodiment, these IP are acted on behalf of so as to be the IP blocks with the interface for meeting IOSF specifications or patrol
Collect device.As further seen, construction 20 is also connected with the interface of bridger 50.Although for the ease of saying in Fig. 1 embodiment
It is bright and be not shown, it should be appreciated that bridger 50 may be used as from for example on the same chip or one or more different
The interface of other system units on chip.
As described further below, each element shown in Fig. 1, i.e. construction, IP agencies and bridger can include
For the one or more interfaces for the communication for handling various signals.These interfaces can limit according to IOSF specifications, IOSF rule
Model defines：The signal that is communicated on these interfaces, the agreement exchanged for the information between agency, for initiating and managing
The arbitration of information exchange and flow control mechanism, the address decoding of support and transfer capability, disappearing for communication in band or out of band
Transmission, power management, test, checking and debugging is ceased to support.
IOSF specifications include being 3 stand-alone interfaces that each agency provides, i.e., basic interface, sideband message interface with
And testability and debugging interface (being used for the design (DFT) tested, the interface for the design (DFD) of debugging).According to IOSF
Specification, agency can support any combinations of these interfaces.Specifically, agency can support 0-N basic interfaces, 0-N sidebands
Message interface and optional DFx interfaces.However, according to specification, agency must support at least one in this 3 interfaces.
Construction 20 can be the hardware element of the mobile data between different agencies.Pay attention to, construct 20 topological structure
To be that product is specific.As an example, construction may be implemented as bus, laminar bus, cascade center etc..Referring now to Figure 2,
It is illustrated that the block diagram of the further detail below of interconnection architecture according to an embodiment of the invention.As shown in Figure 2, IOSF specifications limit
Three different constructions, i.e. basic interface construction 112, DFx constructions 114 and sideband construction 116 are determined.Basic interface construction 112
For all in-band communications between agency and memory, for example, such as CPU (CPU) or other processors it
Between the host-processor of class and agency.Basic interface construction 112 can also realize the equity between agency and the construction supported
The communication of affairs.Can be via including memory, input and output (IO), configuration and all transaction types of in-band message transmission
The transmission of basic interface construction 112.Therefore, basic interface construction may be used as with the reciprocity affairs of upstream components and/or communication
Between the high-performance interface of data that transmits.
In various embodiments, basic interface construction 112 implements the segmentation transaction protocol for realizing maximum concurrency.
That is, the agreement provides request stage, authorization stages and order and data phase.In various embodiments, basic interface constructs
112 support three kinds of basic request types：Having noticed, not noticing and completion.Generally, the affairs noticed are such things
Business：When being sent by source, it is considered what is completed by source, and source is not received by the completion about affairs or other confirms to disappear
Breath.One such example of the affairs noticed can be write-in affairs.By contrast, the affairs do not noticed are not recognized by source
To be to complete, until receiving return message, that is, complete.One example of the affairs do not noticed is to read affairs, wherein source
Proxy requests read data.Therefore, completion message provides asked data.
In addition, the concept of the support different channels of basic interface construction 112 is used for independent data stream to provide in whole system
Mechanism.As will be described further, basic interface construction 112 itself can include initiating the main interface of affairs and receive affairs
Target interface.Basic main interface can be further subdivided into request interface, command interface and data-interface.Ask interface can be with
For the order for affairs and the mobile offer control of data.In various embodiments, basic interface construction 112 can be supported
PCI ordering rules and enumerate.
And then side band interface construction 116 can be for transmitting all standard mechanisms with external information.By this way,
The industrial siding designed for given embodiment can be avoided, ability is reused on various chips so as to improve IP.
Therefore, with handling state, interruption, power management, fuse distribution, configuration shade, test pattern etc. using industrial siding
The IP blocks of out-of-band communication promote module on the contrary, according to all out-of-band communications of standardization of the side band interface of IOSF specifications construction 116
Change, and reduce the checking requirement that IP is reused in different designs.Generally, side band interface construction 116 can be used for transmitting non-
Performance-critical information, rather than for can generally construct the performance-critical data transfer of 112 transmission via basic interface.
As further shown in Figure 2, IP agencies 130,140 and 150 may each comprise corresponding basic interface, side band interface
With DFx interfaces.However, as discussed above, in certain embodiments, each agency need not include each in these interfaces
It is individual, and given IP agencies can only include individual interface.
Using IOSF specifications, various types of chips with various difference in functionalitys can be designed.Referring now to Figure 3, show
SoC according to an embodiment of the invention high level block diagram is gone out.As shown in Figure 3, SoC 200 can include various parts, institute
There are these parts to may be integrated on single semiconductor element, various disposal abilities, consumption are at full speed provided with low-power
Relatively small number of substrate area.As shown in Figure 3, SoC 200 includes multiple cores 2050-205n.In various embodiments, core
The heart 205 can be relatively simple core or more complicated out-of-order core in order.Or there may be in single SoC in order and
The combination of out-of-order core.As can be seen, core 205 can interconnect 215 via uniformity and be interconnected, and it is further coupled to
Cache memory 210, such as shared whole level cache (LLC).Although the scope of the present invention is not limited to this aspect,
But in one embodiment, uniformity interconnection 215 can according to from Intel Corporation, Santa Clara,
Quick Path Interconnect obtained by California (Quick Path Interconnect) (QPI)TMSpecification.
As in Fig. 3 it is further seen that, uniformity interconnection 215 250 can be communicated via bridger 220 with constructing,
Construction 250 can be IOSF constructions.Uniformity interconnection 215 can also be via storage outside integrated memory controller 215 and chip
Device (Fig. 3 embodiment is not shown for convenience of description) is communicated, and is further entered by bridger 230 and construction 250
Row communication.
As in Fig. 3 it is further seen that, various parts may be coupled to the construction for including content processing module (CPM) 240
250, content processing module (CPM) 240 can be used for the various operations for performing safe handling, encryption function etc..It is in addition, aobvious
It can be for a part for the media processing pipeline of related display render video to show processor 245.
As it is further seen that, construction 250 be also coupled to IP agency 255.Although it illustrate only list in Fig. 3 embodiments
Individual agency is in order to illustrate, it is to be understood that can have multiple such agencies in various embodiments.In addition, in order to realize
With the communication of other upper devices, 250 acceptable and PCIe are constructedTMController 260 and USB (USB) controller
265 are communicated, and both can be communicated according to these agreements with various devices.Finally, shown in Fig. 3 embodiment
It is bridger 270, it can be used for and such as open core protocol (OCP) or ARM Advanced Microcontroller Bus Architectures (AMBA)
The additional component of other agreements of agreement etc is communicated.Although showing these particular elements in the embodiments of figure 3,
It should be understood that the scope of the present invention is not limited in this way, and there may be in various embodiments additional or different
Part.
Although furthermore, it is to be understood that being illustrated as singulated dies SoC embodiment in figure 3, embodiment can also be more
Implement in the system that individual chip is in communication with each other via non-IOSF interfaces.Referring now to Figure 4, it is illustrated that according to the another of the present invention
The block diagram of the system of embodiment.As shown in Figure 4, system can include SoC 200', its can include with above for Fig. 3 institutes
Those the similar many parts discussed, and additional tube core external tapping 275.Therefore, SoC 200' can be with another core
Piece 280 is communicated, and chip 280 can include various functions to realize the communication between the two chips, and with various
The communication of outer device, such as the different peripheral components according to one or more different specifications.Specifically, the second chip 280
It is shown as including tube core external tapping 282 to realize the communication with SoC 200', and SoC 200' and then is carried out with construction 290
Communication, the construction 290 can be IOSF constructions according to embodiments of the present invention.As can be seen, construction 290 is also coupled to
The various controllers to be communicated with device outside piece, including PCIeTMController 292, USB controller 294 and bridger 296.
As discussed above, in various embodiments, all out-of-band communications can be via sideband message interface.With reference now to
Fig. 5, thus it is shown that the block diagram of sideband interconnection according to an embodiment of the invention.As shown in Figure 5, side band interface system 175 is wrapped
Multiple routers 180 and 190 are included, it is shown as via the coupling of point-to-point (PTP) interconnection 185 in the 5 embodiment of figure 5.And then
Each router may be coupled to various end points, and it can be other parts of such as IP agencies or given system.Specifically, road
Multiple end points 186a-186e are coupled to by device 180, and router 190 is coupled to multiple end points 196x-196z.
In various embodiments, can be provided in the single semiconductor devices of such as SoC or other processors etc more
Individual independent domain or root.More specifically, embodiment makes it possible to the boot time of the agency of device being assigned to multiple radical spaces
In one.In embodiment, these radical spaces can include safe radical space and user's radical space.Hardware in radical space and
Software is considered independent computing system.Implementing the physical hardware of multiple radical spaces has shared components (in embodiment
Include shared construction, System Agent, memory and other parts).It is empty that each order with basic interconnection can include root
Between attribute, radical space attribute can be the given field of order.
As used herein, root is to include one or more cores, main bridger, system storage, zero or more
The resource of multiple compound integrated end points, zero or more root compound event collector and zero or more root port
Set.There may be whole computer system in root.The software performed in the root, which requires no knowledge about, has more than one.
In more root systems system, software can be run in the case where not knowing other, and not need any of existing software model
Change, including microcode, basic input output system (BIOS), virtual machine monitor (VMM), operating system (OS), equipment are driven
Dynamic device and application program.
It is shared to be configured to implement sufficient address decode logic set independently of each radical space of other radical spaces.It is based on
(it is given in multiple radical spaces to identify that it may be implemented as multiple positions to radical space (RS) designator in order (CMD)
One) select the address decoder for affairs.In embodiment, System Agent can be that the radical space substituted is implemented
Limited address decoding function and implement decoding completely for main frame radical space.Various queue facilities (for example, channel) can be
Shared between radical space, or select be independent for each radical space based on SoC configurations.Therefore, embodiment provides
The expansible framework solution that can implement in the configurable construction of standard.
More root system systems include two or more roots for sharing one or more physical resources.One root can be designated
For franchise root.This franchise root is first guiding, and is responsible for configuration system.Franchise root is complete before other discharge from reset
Into the configuration of other.There is no static allocation to be configured to any resource (for example, bus or fuse) of root by franchise root.Franchise root
Any resource for being also responsible for coordinating that different can be dynamically reassigned to is redistributed.In embodiment, pass through programming
Register completes system configuration to allocate resources to different roots.In some cases, for some resources, resource allocation
Can be static, and for others, resource allocation is dynamic.Embodiment can be by by affairs and given radical space
Field (RS fields) is associated to isolate root, to realize the comparison of RS values and RS fields.
In order to support existing software model, root includes some hardware resources for being possessed and being controlled by root.Giving software
During hardware initialization before the control of root, the resource of any can be accessed or configured by franchise root.For example, CPU can be with
Gather including configuration register (CR).CR is possessed by the hardware in root, and can only be by micro- generation for being performed in the core of root
Code accesses.Similarly, each CPU gathers with machine specific register (MSR).MSR can be from the core cpu of root
The softward interview of execution.
In any given time, single root agent is assigned to single and by single use.This distribution can be
Either statically or dynamically.The dynamically distributes of single root agent can be with the software coordinates that are performed on involved root.It can pass through
The RS values acted on behalf of are set to implement distribution of the single root agent to root.Then, the RS fields in each basic command solve with address
Ink recorder system is used in combination, to ensure only for the transactions access agency associated with the root of distribution.In some cases, single
Agency can be more perception.This agency can include the machine for being used to set such as register or bus of the RS values of agency
System, it can be programmed by franchise root.Then, the address decoding logic of agency can perform the security strategy based on root.
If single root agent is not more perception, constructs and be responsible for implementing hardware logic, such as address decoding logic,
To enable the agent to be allocated RS values and perform given security strategy.
In embodiment, more root agents can be exposed to two or more.This can be by each it is special basic
Interface or shared basic interface with dedicated channel are realized.In the case of special purpose interface, each interface is allocated RS
Value.For dedicated channel, each channel can be associated with RS values.
When more root agents by more than one simultaneously in use, agency can be configured with appropriate hardware (for example, bus
Or register) so that private resource is exposed into each.In embodiment, run in root and the software that is interacted with hardware can be with
Do not know that it is interacted with more root agents.
Main bridger provides the connection between (multiple) CPU, system storage and I/O subsystems, wherein, I/O subsystems
In the southern side of main bridger, and (multiple) CPU is in the north side of main bridger.Single main bridger, which includes, is only used for a root
Resource.It is statically assigned to radical space.Root of all affairs from single main bridger north side all with main bridger
Space implicit association.Construction below main bridger or main bridger is all responsible for marking affairs using correct RS fields, and
Implement more security strategies.
If main bridger includes the bridger to sideband interconnection, the bridger is in security attribute designator (SAI) word
Section includes correct RS values.In embodiment, the system storage behind single main bridger can only utilize associated
Radical space conducts interviews.Other can only may be stored by more opaque bridgers come the system stolen using a part
Device.Affairs can be mapped in target radical space by bridger from starting radical space.
More main bridgers represent several piece-root graftings and receive and handle affairs.Division of the main bridger resource between radical space be
Static allocation in hardware, or configured with initialization time.Main bridger performs security strategy, to ensure difference
Resource isolation between root.More main bridger tracking for supporting to distribute to the various CPU in north side into different radical spaces come from north side
Incoming affairs origin, and using correct RS field marks they.By any buffer consistency stream of main bridger all
It is isolated to origin radical space.The system storage of more main bridgers can divide between multiple radical spaces.Main bridger
It is responsible for safeguarding the storage implements of the host-physical address associated from different radical spaces and the physical address as system storage
Manage the mapping between address.
In embodiment, more opaque bridgers are attached to more root agents of more.Such bridger provides
One or more communication mechanisms (for example, mailbox register, doorbell, memory conversion window etc.), in a root
Software interacts with the software in another root.
In embodiment, the agency actively decoded for whole RS fields is represented, row address decoding is held in construction.
If construction is connected to the single root agent for not supporting RS fields, the construction is responsible for representing the agency to implement more safe plans
Slightly.In embodiment, such strategy includes carrying out the RS fields in order decoding completely and by the RS fields in order
Compared with the RS values of agency.
In embodiment, sideband construction uses the single group Target id independently of the resident root of end points.Bridged from basic interconnection
Any affairs to sideband interconnection can include from underlying transaction to the RS fields in the given field of sideband message, such as SAI
Field, to enable the information to be passed to appropriate target.
Referring now to Figure 6, it is illustrated that the block diagram united according to more root systems of embodiment.In figure 6 in shown embodiment,
More root system systems 300 may be implemented as SoC or other polycaryon processors, such as implement in single processor encapsulation.At it
In the case of it, system 300 may be implemented as the set of discrete parts, such as suitable for giving the motherboard or other of computing system
Circuit board, the scope for giving computing system can be from small portable apparatus (such as smart phone, tablet personal computer etc.) to service
Device computer.As illustrated, system 300 includes first 310 and second 360.In embodiment, these different roots can be with
With different privilege levels so that one (for example, first 310) in root is configured as franchise root, and second 360 quilt
It is configured to non-privileged.Notice that term " root " and " radical space " are used interchangeably herein, and so as to which root 310 and 360 exists
Radical space is also referred to as herein.
In franchise root, it is possible to implement for configuring system and performing the franchise generation such as operating system, management program
The various operations of code, and non-privileged and then various non-privileged user applications can be performed.Pay attention to, shown with blank form
The block gone out has first 310, and 360 associated with second with the block shown in black forms.And then shared resource is in figure 6
It is shown as shaded block.
As illustrated, first 310 includes multiple CPU 315a-315b.CPU 315 is coupled to main bridger 320, main bridge
Connect device 320 and be in turn coupled to system storage 325, system storage 325 can be DRAM in embodiment.As can be seen,
Main bridger 320 can include polymerizeing safe manageability engine (CSME).Main bridger 320 is additionally coupled to construction 350, construction
350 can be the IOSF constructions as the shared resource between multiple in embodiment.Therefore, the offer of construction 350 is shared to arrive
The interconnection of the agency of two radical spaces.Referring still to first 310, construction 350 is coupled to root port 330 and multiple Composite Sets
Into end points 340a and 340b.
With reference now to second 360, single cpu 365 be present.Certainly, in other embodiments, multiple CPU can also be with
The root is associated.CPU 365 is coupled to main bridger 370, and main bridger 370 is in turn coupled to system storage 375.And then
Main bridger 370 is further coupled to shared construction 350, and is relevant to the part of second 360, and construction 350 is coupled to root
Compound integrated end points 380a and 380b.Although it should be understood that shown in the embodiment in fig 6 with the particular implementation, many
Change and alternative solution are possible.
Referring now to Figure 7, it is illustrated that the block diagram united according to more root systems of another embodiment.Shown implementation in the figure 7
In example, more root system systems 400 may be implemented as SoC or other polycaryon processors, such as implement in single processor encapsulation,
Or the set of discrete parts, such as suitable for the motherboard for giving computing system or other circuit boards.As illustrated, system 400
Including first 410 and second 460.In embodiment, these different roots can have different privilege levels so that root
In one (for example, first 410) be configured as franchise root, and second 460 is configured as non-privileged.As described above,
There is first 410 with the block shown in blank form, and it is 460 associated with second with the block shown in black forms.And then altogether
Enjoy resource and be shown as shaded block in the figure 7.
As illustrated, first 410 includes multiple CPU 415a-415b.CPU 415 is coupled to main bridger 452, main bridge
Connect device 452 and be in turn coupled to system storage 454.Main bridger 452 is further coupled to construction 450, and construction 450 is in embodiment
In can be IOSF construction.As seen in fig. 7, main bridger 452, system storage 454 and construction 450 are between more
Shared resource.Therefore, the offer of construction 450 and the interconnection of the agency of two radical spaces are provided.Referring still to first 410, structure
Make 450 and be coupled to root port 430 and multiple compound integrated end points 440a and 440b.
With reference now to second 460, single cpu 465 be present.Certainly, in other embodiments, multiple CPU can also be with
The root is associated.CPU 465 is additionally coupled to main bridger 452.The part of second 460 is relevant to, construction 450, which is coupled to root, answers
Intersection is into end points 480a and 480b.Although it should be understood that shown in Fig. 7 embodiment with the particular implementation, many changes
Change and alternative solution is possible.
Referring now to Figure 8, it is illustrated that the block diagram united according to more root systems of another embodiment.Shown implementation in fig. 8
In example, more root system systems 500 may be implemented as the set of SoC or other polycaryon processors or discrete parts.As illustrated, it is
System 500 includes first 510 and second 560.In embodiment, these different roots can have different privilege levels,
So that one (for example, first 510) in root is configured as franchise root, and second 560 is configured as non-privileged.As above
It is described, there is first 510 with the block shown in blank form, and it is 560 associated with second with the block shown in black forms.Enter
And shared resource is shown as shaded block in fig. 8.
As illustrated, first 510 includes multiple CPU 515a-515b.CPU 515 is coupled to main bridger 520, main bridge
Connect device 520 and be in turn coupled to system storage 525.Main bridger 520 is further coupled to construction 550, and construction 550 is in embodiment
In can be IOSF construction.As seen in fig. 8, main bridger 520 and system storage 525 are the resources of first 510.
Shared construction 550 provides the shared resource of interconnection by sharing the agency of bridger 555 to two radical spaces.Referring still to first
Root 510, construction 550 are coupled to root port 530 and the compound integrated end points 540a of root.
With reference now to second 560, single cpu 565 be present.Certainly, in other embodiments, multiple CPU can also be with
The root is associated.CPU 565 is coupled to the main bridger 570 and system storage 575 of the resource as second 560.It is related
In the part of second 560, construction 590 is coupled to the compound integrated end points 580b and 580c of root, and passes through bridge as shown in figure
Device 555 and construction 550 are connect, is additionally coupled to the compound integrated end points 580a of root.Although it should be understood that in the embodiment in fig. 8 with the spy
Determine embodiment to show, but many changes and alternative solution are possible.
Although above-mentioned SoC is in high-level, it should be understood that there may be additional function.With reference now to 9, thus it is shown that according to
The more detailed block diagram of the SoC of an embodiments of the invention part.As shown in Figure 9, shown SoC 700 part can be with
Corresponding to the non-core portion being coupling under Memory Controller center or other interface logics, Memory Controller center or its
Its interface logic and then it can be connected with multiple processor cores and SMI.
Therefore, as can be seen, (it can be direct media interface in one embodiment to tube core external tapping 710
(DMI) center 715, such as input/output center) are may be coupled to, itself so that the communication between various peripheral components is provided.To the greatest extent
It is not shown for convenience of description in pipe Fig. 9, it should be appreciated that the various of such as manageability engine and virtualization engine etc are drawn
Center 715 can also be directly coupled to by holding up.
In order to provide and can be the connection according to the multiple spot of IOSF specifications or multiple buses of shared bus, IOSF be controlled
Device 720 can be coupling between center 715 and bus 730, and bus 730 can therefore be incorporated to the element and route of the construction
The IOSF buses of device.In fig.9 in shown embodiment, the first IOSF buses 730 may be coupled to its various controller to carry
For the control to device outside piece.Specifically, it is seen that be pci controller 722, SATA controller 724 and USB controller 726.
And then the 2nd IOSF buses 750 may be coupled to System Management Bus 752 and real-time clock 754.
As in Fig. 9 it is further seen that, the first IOSF buses 730 may be coupled to be used for essential information and side information two
For example different associations that the IOSF bridgers 735 of person, IOSF bridgers 735 and then offer can be attached from various controllers and part
The interconnection of 3rd bus 740 of view.In fig.9 in shown embodiment, such part includes being used to provide to non-volatile
The flash controller 741 of the interface of memory, can implement such as PCI specification various traditional functions traditional devices 742, and
And interrupt control unit and timer can also be included.In addition, for audio 743, USB 744, gigabit Ethernet (GbE) 745, string
Row Peripheral Interface (SPI) 746 and PCI 747 interface are all to be provided.Although in the embodiment in fig. 9 with the specific reality
The mode of applying is shown, it should be appreciated that the scope of the present invention is not limited to this aspect.
Also other embodiment is possible.Referring now to Figure 10, it is illustrated that according to an embodiment of the invention another
One SoC block diagram.As shown in Figure 10, SoC 800 can be configurable for such as server system.As shown in Figure 10,
SoC can include platform controller hub (PCH) 840, and it can generally include the portion seen in such as Fig. 9 embodiment
Part.I.e., it is possible to multiple IOSF buses 730 and 740 and the bridger 735 for Coupling busses be present.Bus 730 can include
It is coupled to its various agencies, including PCIe controller 722, SATA controller 724 and USB controller 726.And then via
IOSF controllers 720, can via can with upstream device (such as core or other processing units (in Figure 10 embodiment in order to
Be easy to illustrate and be not shown)) communication additional busses 718 communicated.
As in Figure 10 it is further seen that, in order to provide the communication with other parts based on server, can provide attached
The IOSF buses 820 added, itself so that with IOSF controllers 822 and the upstream exchange end of upstream bus 825 can be may be coupled to
824 (for example, X16 ports) of mouth are communicated.Be also coupled to bus 820 can be multiple Hes of downstream switching port 826
828。
In addition, in order to realize the communication for example with the storage element of the system based on server, switching port 830 can be with coupling
Close between bus 820 and another IOSF bus 850, another IOSF buses 850 and then may be coupled to store controller list
Member (SCU) 855, store controller unit 855 can be the multifunction device for being coupled with various memory devices.
In order to enable more root system systems, the system is arranged to more operations.Therefore, multiple radical spaces can be limited.This
The restriction of sample can be implemented in the configuration of SoC or other processors, or can dynamically perform restriction.For example, one or
Multiple agencies can dynamically associate in different time from different radical spaces.
Referring now to Figure 11, it is illustrated that the flow chart of method according to embodiments of the present invention.As shown in Figure 11, method
1000 can perform in SoC to enable more radical space configurations and operation.As can be seen, method 1000 is by will at least
One processor and at least first agent (it can be SoC end points or other agencies) (square frame associated with the first radical space value
1010).Therefore, each such part can be by the way that set-point be stored in including in part or the storage associated with part
Come associated with the first radical space value in storage (such as configuration store).By the association, the first radical space is defined to
Including these parts.Similar operation can occur in square frame 1020, will at least second processor and at least second agent with
Second radical space value is associated, to limit the second radical space.
Referring still to Figure 11, these parts can be for example via shared tectonic coupling together, and shared construction is being implemented
IOSF constructions (square frame 1030) are may be implemented as in example.Now, SoC is arranged to normal operating.
Therefore, as shown in Figure 11, during operation, affairs (square frame 1040) can be received in the shared construction.Extremely
The radical space value of the radical space field of affairs is at least partly based on, affairs can be routed in multiple radical spaces by shared construction
One given radical space (the specific objective agency more specifically in radical space) (square frame 1050).Although it should be understood that scheming
In 11 embodiment with this it is high-level show, but it is many change and alternative solution be possible.
Referring now to Figure 12, it is illustrated that the block diagram for the example system that can use embodiment.In Figure 12 explanation,
System 1300 can be such as tablet PC, 2:1 tablet personal computer, flat board mobile phone or other convertible or independent tablet personal computer system
The mobile low-power dissipation system of system etc.As illustrated, SoC1310 exists and can be configured as the application processing as device
Device operates.SoC 1310 can be configured as including multiple radical spaces as described herein, and wherein one or more generations
Reason can dynamically associate with one or more of radical space.This more perception devices and then it can be configured as and power control
Device processed and/or construction collaboratively implement partial reset operation as described herein.
Various devices may be coupled to SoC 1310.In shown diagram, memory sub-system includes being coupled to SoC
1310 flash memories 1340 and DRAM 1345.In addition, touch panel 1320 is coupled to SoC 1310 to provide display capabilities
User's input with via touch, is included on the display of touch panel 1320 and provides dummy keyboard.In order to provide wired network
Network connectivity, SoC 1310 are coupled to Ethernet interface 1330.Peripheral center 1325 be coupled to SoC 1310 with realize with it is various
The interface connection of peripheral components, such as can be coupled to by any port in various ports or other connectors or connector
System 1300.
In addition to the internal power management circuit in SoC 1310 and function, power management integrated circuits (PMIC) 1380
Be coupled to SoC 1310 to provide the power management based on platform, for example, based on system be powered by battery 1390 or via
AC adapters 1395 are powered by AC power supplies.In addition to the power management based on power supply, PMIC 1380 is also based on environment
Platform power management activity is performed with use condition.Further, PMIC 1380 can transmit control and shape to SoC 1310
State information, to cause the various power management actions in SoC 1310.
Referring still to Figure 12, in order to provide wireless capability, WLAN unit 1350 is coupled to SoC 1310, and and then couples
To antenna 1355.In various embodiments, WLAN unit 1350 can provide communication according to one or more wireless protocols.
As further shown, multiple sensors 1360 may be coupled to SoC 1310.These sensors can include each
Kind accelerometer, environment and other sensors, including user gesture sensor.Finally, audio codec 1365 is coupled to SoC
1310 arrive the interface of audio output device 1370 to provide.It would certainly understand from, although being shown in fig. 12 with the particular implementation,
But many changes and alternative solution are possible.
Referring now to Figure 13, the block diagram of representative computer system is illustrated that, such as notebook computer, UltrabookTM
Or other small form factor systems.In one embodiment, processor 1410 includes microprocessor, polycaryon processor, multithreading
Processor, ultralow voltage processor, embeded processor or other known treatment element.In the illustrated embodiment, processor
1410 serve as Main Processor Unit and the central center to be communicated for many various parts with system 1400.As an example,
Processor 1410 is implemented as providing the SoC of multiple radical spaces and its configuration and control, as described herein.
In one embodiment, processor 1410 communicates with system storage 1415.As illustrated examples, system storage
Device 1415 is implemented via multiple storage component parts or module, to provide the system storage of specified rate.
In order to provide the lasting storage of the information of data, application, one or more operating systems etc., bulk storage
Device 1420 can also be coupled to processor 1410.In various embodiments, in order to realize thinner and lighter system design and
In order to improve system responsiveness, the bulk storage can be implemented via SSD, or bulk storage can be used mainly
Implement with the hard disk drive (HDD) of less amount of SSD holders, SSD holders are used as SSD caches to realize
The nonvolatile storage of background state and other this type of informations during power cut-off incident, so as to can be with restarting systems activity
Carry out fast powering-up.Equally shown in fig. 13, flush memory device 1422 can be coupled for example via Serial Peripheral Interface (SPI) (SPI)
To processor 1410.The flush memory device can provide the nonvolatile storage of system software, including basic input/output software
(BIOS) and system other firmwares.
There may be various input/output (I/O) device in system 1400.What is specifically illustrated in Figure 13 embodiment is aobvious
Show device 1424, it can be the fine definition LCD or LED panel for further providing for touch-screen 1425.In one embodiment, show
Show that device 1424 can interconnect via display and be coupled to processor 1410, it is mutual that display interconnection may be implemented as high performance graphicses
Even.Touch-screen 1425 can be coupled to processor 1410 via another interconnection, and in embodiment, another interconnection can be I2C
Interconnection.As further shown in Figure 13, can also be via touch pad by user's input of touch in addition to touch-screen 1425
1430 are carried out, and touch pad 1430 can be configured in bottom plate, and is also coupled to and the identical I of touch-screen 14252C is mutual
Even.
It is may reside in perceive to calculate with other purposes, various sensors in system, and can be with different sides
Formula is coupled to processor 1410.Some inertia and environmental sensor can be (such as mutual via I2C by center sensor 1440
Even) it is coupled to processor 1410.In fig. 13 in shown embodiment, these sensors can include accelerometer 1441, ring
Border optical sensor (ALS) 1442, compass 1443 and gyroscope 1444.Other environmental sensors can include one or more heat and pass
Sensor 1446, it is coupled to processor 1410 via System Management Bus (SMBus) bus in certain embodiments.
As seen in Figure 13, various peripheral components can interconnect via low pin count (LPC) is coupled to processor 1410.
In an illustrated embodiment, various parts can be coupled by embedded controller 1435.This part can include keyboard
1436 (for example, being coupled via PS2 interfaces), fan 1437 and heat sensor 1439.In certain embodiments, touch pad 1430 is gone back
EC 1435 can be coupled to via PS2 interfaces.In addition, such as safe processor of credible platform module (TPM) 1438 etc
It can be interconnected via the LPC and be coupled to processor 1410.
System 1400 (including wirelessly) can communicate with external devices in a variety of ways.Shown embodiment in fig. 13
In, the various wireless modules that can correspond to the wireless device for particular wireless communication protocols configuration be present.It is a kind of short
Communication in distance (such as near field) can in one embodiment may be used via NFC unit 1445, NFC unit 1445
To be communicated via SMBus with processor 1410.Pay attention to, via the NFC unit 1445, device very close to each other can be with
Communication.
As in Figure 13 it is further seen that, additional radio-cell can include other short-distance wireless engines, including
WLAN unit 1450 and BluetoothTM1452.Use WLAN unit 1450, it is possible to achieve Wi-FiTMCommunication, and via
BluetoothTMUnit 1452, short distance Bluetooth can be carried outTMCommunication.These units can be via given link and place
Reason device 1410 is communicated.
In addition, for example can be via WWAN units 1456 according to the wireless wide-area communication of honeycomb or other wireless wide-area agreements
Carry out, WWAN units 1456 and then may be coupled to subscriber identification module (SIM) 1457.In addition, in order to realize positional information
Receive and use, there can also be GPS module 1455.Pay attention to, in fig. 13 in shown embodiment, WWAN units 1456 and all
Integrated collecting device such as camera model 1454 etc can be communicated via given link.
In order to provide audio input and output, audio frequency process can be implemented via digital signal processor (DSP) 1460
Device, digital signal processor (DSP) 1460 can link via high definition audio (HDA) is coupled to processor 1410.It is similar
Ground, DSP 1460 can be communicated with integrated encoder/decoder (CODEC) and amplifier 1462, the integrated encoder/solution
Code device (CODEC) and amplifier 1462 and then it may be coupled to the output loudspeaker 1463 that can implement in bottom plate.Similarly,
Amplifier can be coupled to receive audio input from microphone 1465 with CODEC 1462, can be via double battle arrays in embodiment
Row microphone (such as digital microphone array) implements microphone 1465, to provide the audio input of high quality, to realize pair
The voice activation control of various operations in system.It is furthermore noted that audio output can be supplied to from amplifier/CODEC 1462
Earphone jack 1464.Although showing these particular elements in Figure 13 embodiment, it should be understood that the scope of the present invention is unlimited
In this aspect.
Pay attention to, said system may be implemented as single-chip SoC, or it may be implemented as one group of chip.
Following examples are related to further embodiment.
In one example, a kind of system includes：At least one first processor and first agent, described at least one
One processor and the first agent are associated with the first radical space value to limit the first radical space；At least one second processor
And second agent, at least one second processor and the second agent are associated with the second radical space value to limit second
Radical space；And shared construction, its be used to being coupled at least one first processor, the first agent, it is described at least
One second processor and the second agent, the shared construction are based at least partially on the root in the radical space field of affairs
The affairs are routed to first radical space or second radical space by spatial value.
In this example, first radical space includes being used to guide prior to second radical space and configure system
Franchise root.
In this example, the first agent is dynamically allocated to the first radical space value, and hereafter by dynamic point
Second radical space value described in dispensing is so that the first agent is included in second radical space.
In this example, described share is configured to keep apart first radical space and second radical space.
In this example, the system further comprises main bridger, and host bridge, which connects device, to be included and first radical space
The associated main bridger of the first logic and the second logic main bridger associated with second radical space.
In this example, the system further comprises by the shared system of first radical space and second radical space
Memory, the system storage have first subregion associated with first radical space and with the second radical space phase
Second subregion of association.
In this example, system bridges device is used to include the shared tectonic coupling to the second construction, second construction
In first radical space.
In this example, the first agent includes root logic, and described logic is used to prevent the access to being passed to affairs, institute
State incoming affairs has the radical space value for being different from the first radical space value in the radical space field of the incoming affairs.
In this example, the holder that the first agent is programmed using the first radical space value.
In this example, the system includes SoC.
In another example, a kind of method includes：By SoC at least one first processor and the SoC at least
One first agent is associated with the first radical space value, to limit the first radical space of the SoC；By at least the one of the SoC
Individual second processor and the SoC at least one second agent are associated with the second radical space value, to limit the of the SoC
Two radical spaces；Affairs are received in the shared construction for being coupled to first radical space and second radical space；And at least
It is based in part on the radical space value of the radical space field of the affairs and the affairs is routed to first radical space and described
One selected in second radical space.
In this example, methods described further comprises guiding first radical space to configure including the SoC's first
System, wherein, first radical space includes franchise root.
In this example, methods described further comprises by making at least one first agent and second radical space
Value is associated is reassigned to second radical space by least one first agent from first radical space.
In this example, methods described further comprises the root that radical space value is inserted into the first affairs for pointing to target proxy
In space field, it is inserted into the security attribute indicator field of the second affairs, wherein, via connecing substantially for the shared construction
Mouth received in the shared construction first affairs and via the shared construction side band interface by second thing
Business is sent to the target proxy.
In this example, methods described further comprises：By at least one first agent and the first radical space value
Dynamically be associated, with cause it is described it is at least one agency be included in first radical space, and hereafter will described at least
One first agent and the second radical space value are dynamically associated, to cause at least one first agent to be included in institute
State in the second radical space.
In this example, methods described further comprises first radical space and described second via the shared construction
Radical space is kept apart.
In another example, a kind of computer-readable medium, including for performing the side of any one in above-mentioned example
The instruction of method.
In another example, a kind of computer-readable medium, including for by least one machine using with manufacture to
Lack an integrated circuit to perform the data of the method for any one in above-mentioned example.
In another example, a kind of device includes being used for the module for performing the method for any one in above-mentioned example.
In this example, a kind of device includes semiconductor element, and it includes but is not limited to various circuits.In this example, so
Circuit can include：Multiple agencies, at least the first subset of the multiple agency are associated with the first radical space value with restriction
First radical space, and at least yield in the second subset of the multiple agency is associated with the second radical space value to limit second sky
Between；And it is coupled to the construction of the multiple agency via construction basic interface, the construction basic interface includes being used to initiate
At least one main interface of affairs and at least one target interface for receiving affairs, wherein, it is described to be configured at least portion
Affairs are routed to first radical space or described second by the radical space value in point radical space field of the ground based on affairs
Space.
In this example, the individual reset for being configured to realize first radical space and second radical space.
In this example, described device includes SoC, and it may further include：It is associated extremely with first radical space
Few first core and at least one second core associated with second radical space；It is coupled to described at least one
The first uniformity interconnection of one core；It is coupled to the second uniformity interconnection of at least one second core；And via side
It is coupled to the router of at least some agencies in the multiple agency with interconnection.
In this example, described device further comprises at least one part for being coupled to the construction via bridger, its
In, at least one part has open core protocol (OCP) or ARM Advanced Microcontroller Bus Architectures (AMBA) agreement.
It should be understood that the various combinations of above-mentioned example are possible.
Embodiment can be used in many different types of systems.For example, in one embodiment, communication equipment can be by
It is arranged to perform various methods described herein and technology.Certainly, the scope of the present invention is not limited to communication equipment, but other realities
The other types of device for being used for process instruction, or one or more machine readable medias can be directed to by applying example, and it includes referring to
Order, the instruction is in response to being executed to cause equipment to perform one kind in method described herein and technology on the computing device
It is or a variety of.
Embodiment can use code implementation, and can be stored on non-transitory storage medium, and non-transitory storage is situated between
Instruction is stored with matter, and it can be used for system is programmed with execute instruction.Embodiment can also with data implement and
It can be stored on non-transitory storage medium, if it is used by least one machine, cause at least one machine manufacture
At least one integrated circuit is to perform one or more operations.Further embodiment can use computer-readable storage media
Implement, computer-readable storage media includes information, and when being manufactured into SoC or other processors, described information is used to configure SoC
Or other processors are to perform one or more operations.Storage medium can include but is not limited to：Including floppy disk, CD, solid-state
Driver (SSD), compact disc read-only memory (CD-ROM), Ray Disc Rewritable (CD-RW) and magneto-optic disk it is any kind of
Disk；Such as read-only storage (ROM), random access memory (RAM) (such as dynamic random access memory (DRAM), static state
Random access memory (SRAM)), Erasable Programmable Read Only Memory EPROM (EPROM), flash memory, electrically erasable
The semiconductor of read-only storage (EEPROM), magnetically or optically card or the medium of any other type etc suitable for storing e-command
Device.
Although describing the present invention for the embodiment of limited quantity, it will be appreciated by persons skilled in the art that by
This obtained many modifications and variations.Appended claims are intended to fall into all in true spirit and scope of the present invention
These modifications and variations.
Claims (22)
1. a kind of system, including：
At least one first processor and first agent, at least one first processor and the first agent with first
Spatial value is associated to limit the first radical space；
At least one second processor and second agent, at least one second processor and the second agent with second
Spatial value is associated to limit the second radical space；And
Shared construction, it is used to be coupled at least one first processor, the first agent, described at least one second
Processor and the second agent, the radical space value that the shared construction is based at least partially in the radical space field of affairs will
The affairs are routed to first radical space or second radical space.
2. system according to claim 1, wherein, first radical space includes being used to enter prior to second radical space
Row guides and configures the franchise root of the system.
3. system according to claim 1, wherein, the first agent is dynamically allocated to first radical space
Value, and hereafter the first agent be dynamically allocated to the second radical space value so that the first agent be included in it is described
In second radical space.
4. system according to claim 1, wherein, described share is configured to first radical space and described second
Radical space is kept apart.
5. system according to claim 1, further comprise main bridger, host bridge, which connects device, to be included and described first
The main bridger of the first logic and the second logic main bridger associated with second radical space of space correlation connection.
6. system according to claim 5, further comprise being shared by first radical space and second radical space
System storage, the system storage have first subregion associated with first radical space and with described second
Second subregion of space correlation connection.
7. system according to claim 1, further comprise system bridges device, the system bridges device is used for will be described common
Tectonic coupling is enjoyed to the second construction, second construction to be included in first radical space.
8. system according to claim 1, wherein, the first agent includes root logic, and described logic is used to prevent
Access to being passed to affairs, the incoming affairs have in the radical space field of the incoming affairs is different from described first
The radical space value of spatial value.
9. system according to claim 1, wherein, the first agent is compiled using the first radical space value
The holder of journey.
10. system according to claim 1, wherein, the system includes on-chip system (SoC).
11. a kind of method, including：
By at least one first processor of on-chip system (SoC) and the SoC at least one first agent and first sky
Between be worth it is associated, to limit the first radical space of the SoC；
By at least one second processor of the SoC and the SoC at least one second agent and the second radical space value phase
Association, to limit the second radical space of the SoC；
Affairs are received in the shared construction for being coupled to first radical space and second radical space；And
The affairs are routed to first sky by the radical space value for being based at least partially on the radical space field of the affairs
Between and second radical space selected in one.
12. according to the method for claim 11, further comprise guiding first radical space to configure including institute first
The system for stating SoC, wherein, first radical space includes franchise root.
13. according to the method for claim 11, further comprise by making at least one first agent and described the
Two radical space values are associated is reassigned to described second by least one first agent from first radical space
Space.
14. according to the method for claim 11, further comprise radical space value being inserted into and point to the first of target proxy
In the radical space field of affairs, it is inserted into the security attribute indicator field of the second affairs, wherein, via the shared construction
Basic interface received in the shared construction first affairs and via the shared construction side band interface by institute
State the second affairs and be sent to the target proxy.
15. according to the method for claim 11, further comprise：
At least one first agent and the first radical space value is dynamically associated, to cause at least one generation
Reason is included in first radical space；And
Hereafter it is at least one first agent and the second radical space value is dynamically associated, to cause described at least one
Individual first agent is included in second radical space.
16. according to the method for claim 11, further comprise via the shared construction will first radical space and
Second radical space is kept apart.
17. a kind of computer-readable storage media, including machine readable instructions, upon being performed, the machine readable instructions are real
Apply the method according to any one of claim 11 to 16.
18. a kind of device, including for performing the module according to any one of claim 11 to 16.
19. a kind of device, including：
Semiconductor element, the semiconductor element include but is not limited to：
Multiple agencies, at least the first subset of the multiple agency is associated with the first radical space value to limit the first radical space,
And at least yield in the second subset of the multiple agency is associated with the second radical space value to limit the second radical space；And
It is coupled to the construction of the multiple agency via construction basic interface, the construction basic interface includes being used to initiate affairs
At least one main interface and at least one target interface for receiving affairs, wherein, it is described to be configured at least in part
The affairs are routed to first radical space or described second by radical space value in the radical space field based on affairs
Space.
20. device according to claim 19, wherein, it is described to be configured to realize first radical space and described second
The individual reset of radical space.
21. device according to claim 19, wherein, described device includes on-chip system (SoC), the on-chip system
(SoC) further comprise：
At least one first core associated with first radical space and associated with second radical space at least one
Individual second core；
It is coupled to the first uniformity interconnection of at least one first core；
It is coupled to the second uniformity interconnection of at least one second core；And
It is coupled to the router of at least some agencies in the multiple agency via sideband interconnection.
22. device according to claim 19, further comprise being coupled at least one of the construction via bridger
Part, wherein, at least one part has open core protocol (OCP) or ARM Advanced Microcontroller Bus Architectures
(AMBA) agreement.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562170905P | 2015-06-04 | 2015-06-04 | |
| US62/170,905 | 2015-06-04 | ||
| US14/880,443 | 2015-10-12 | ||
| US14/880,443 US9990327B2 (en) | 2015-06-04 | 2015-10-12 | Providing multiple roots in a semiconductor device |
| PCT/US2016/030951 WO2016195904A1 (en) | 2015-06-04 | 2016-05-05 | Providing multiple roots in a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107533443A true CN107533443A (en) | 2018-01-02 |
| CN107533443B CN107533443B (en) | 2021-08-03 |
Family
ID=57441185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680025770.9A Active CN107533443B (en) | 2015-06-04 | 2016-05-05 | Providing multiple roots in a semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9990327B2 (en) |
| EP (1) | EP3304328B1 (en) |
| CN (1) | CN107533443B (en) |
| WO (1) | WO2016195904A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2016195904A1 (en) | 2016-12-08 |
| US9990327B2 (en) | 2018-06-05 |
| EP3304328B1 (en) | 2021-09-29 |
| EP3304328A1 (en) | 2018-04-11 |
| CN107533443B (en) | 2021-08-03 |
| US20160357700A1 (en) | 2016-12-08 |
| EP3304328A4 (en) | 2019-01-23 |
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