CN107528568B - TSPC flip-flop with data retention feedback loop - Google Patents
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Abstract
The invention relates to the field of integrated circuits, and provides a technical scheme of a TSPC trigger, so that a new TSPC circuit has the capability of data maintenance, and the circuit structure can keep the integrity of data when running in a high-speed circuit. The technical scheme adopted by the invention is that the TSPC trigger with a data retention feedback loop comprises 8 PMOS tubes, namely P1, P2, P3, P4, P5, P6, P7 and P8; the NMOS transistors are 7 and are respectively composed of N1, N2, N3, N4, N5, N6 and N7, and 3 inverters INV1, INV2 and INV 3. The invention is mainly applied to the integrated circuit design and manufacture occasions.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to high speed digital circuit design. And more particularly to TSPC flip-flops with data retention feedback loops.
Background
In digital circuits, the very important circuit structures of D flip-flops are commonly used in circuit structures of frequency dividers, data recovery, and the like. A general TSPC circuit configuration is composed of nine transistors, and is often applied to a high-speed circuit configuration. The speed at which digital circuits operate has now increased considerably due to the reduction in process size. If the traditional TSPC circuit structure is used, data loss occurs at low level, and the function of the circuit is greatly influenced. On the basis of the traditional nine-tube circuit structure, the invention adds a data holding feedback loop at the output, so that a data holding loop is provided at the time of low level, the integrity of data is ensured, and the realization of the circuit function is further ensured.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a technical scheme of a TSPC trigger, so that a new TSPC circuit has the capability of data maintenance, and the circuit structure can keep the integrity of data when running in a high-speed circuit. The technical scheme adopted by the invention is that the TSPC trigger with a data retention feedback loop comprises 8 PMOS tubes, namely P1, P2, P3, P4, P5, P6, P7 and P8; the NMOS transistors are 7 and respectively composed of N1, N2, N3, N4, N5, N6, N7 and 3 inverters INV1, INV2 and INV3, the grid electrode of the PMOS transistor P1 is connected with an input signal D, the drain electrode of the PMOS transistor P2 is connected with the source electrode of the PMOS transistor P2, and the source electrode and the substrate of the PMOS transistor P2 are connected with a power supply; the grid electrode of the PMOS pipe P2 is connected with a clock signal CLK, the source electrode is connected with the drain electrode of the P1, the drain electrode is connected with the node A, and the substrate is connected with a power supply; the gate of the NMOS transistor N1 is connected with an input signal D, the source is connected with the drain of the N2, the drain is connected with the node A, and the substrate is connected with the ground; the gate of the NMOS transistor N2 is connected with the reset signal Rb, the drain is connected with the source of N1, and the source is connected with the ground; the grid electrode of the PMOS pipe P3 is connected with a reset signal Rb, the source electrode and the substrate are connected with a power supply, and the drain electrode is connected with a node A; the grid electrode of the PMOS pipe P4 is connected with a reset signal R, the source electrode and the substrate are connected with a power supply, and the drain electrode is connected with the source electrode of the P5; the grid electrode of the PMOS pipe P5 is connected with a clock signal CLK, the source electrode is connected with the drain electrode of the P4, the drain electrode is connected with the node B, and the substrate is grounded; the grid electrode of the NMOS tube N3 is connected with the node A, the source electrode is connected with the drain electrode of the N4, the drain electrode is connected with the node B, and the substrate is grounded; the grid electrode of the NMOS tube N4 is connected with a clock signal CLK, the source electrode and the substrate are grounded, and the drain electrode is connected with the source electrode of the N3; the grid electrode of the NMOS tube N5 is connected with a reset signal R, the source electrode is connected with the substrate and the ground, and the drain electrode is connected with a node B; the grid electrode of the PMOS tube P6 is connected with the node B, the source electrode and the substrate are connected with the power supply, the drain electrode is connected with the node C, the grid electrode of the NMOS tube N6 is connected with the clock signal CLK, the source electrode is connected with the drain electrode of the N7, the drain electrode is connected with the node C, and the substrate is grounded; the gate of the NMOS transistor N7 is connected with the node B, the source electrode and the substrate are connected with the ground, and the drain electrode is connected with the source electrode of the N6; the grid electrode of the PNOS tube P7 is connected with a reset signal R, the source electrode and the substrate are connected with a power supply, and the drain electrode is connected with a node C; the grid electrode of the PNOS tube P8 is connected with a clock signal CLK, the source electrode is connected with the output of the inverter INV3, the drain electrode is connected with the node C, and the substrate is connected with a power supply; the input of the inverter INV1 is connected with the node C, and the output is connected with the output end Q; the input of the inverter INV2 is connected to the node C, and the output is connected to the input of the inverter INV 3; the input of the inverter INV3 is connected to the output of the inverter INV2, and the output is connected to the source of P8. The reset signals Rb and R are a pair of differential signals, that is, when R is high, Rb is low, and when R is low, Rb is high, for controlling the operation state of the TSPC.
When the reset signal Rb is at a high level and R is at a low level, the flip-flop is in a reset state, and at this time, regardless of the values of the clock signal CLK and the input D, the node a is at a high level, the node B is at a low level, the node C is at a high level, and the output Q is at a low level; when the reset signal Rb is at a low level and R is at a high level, the flip-flop is in a working state, when the input signal D is at a low level and the clock signal CLK is at a low level, the node A is at a high level, the node B is at a high level, the node C is at a high level, the low level during reset is output and maintained, when the clock signal CLK is changed from the low level to the high level, the node A is at a high level, the node B is at a low level, the node C is at a high level, and the output Q is at a low level;
when the clock CLK becomes low and the input D becomes high, the node a becomes low, the node B becomes high, the node C becomes high, and the output Q becomes low.
The invention has the characteristics and beneficial effects that:
the present invention proposes a circuit structure in which a TSPC flip-flop having a data retention feedback loop can operate at high speed, and the integrity of data is ensured due to the introduction of a maintenance data loop.
Description of the drawings:
fig. 1 is a circuit diagram of a TSPC flip-flop structure according to the present invention.
Fig. 2 is a timing diagram of the operation of the TSPC flip-flop proposed by the present invention.
Detailed Description
Because the traditional TSPC trigger circuit structure is in a high-speed circuit, if the clock is a low-level clock and the data loss occurs after the clock is maintained for a period of time, the invention carries out certain innovation on the basis of the traditional TSPC trigger, so that the new TSPC circuit has the data maintaining capability, and the circuit structure can keep the integrity of the data when running in the high-speed circuit.
The circuit diagram of the TSPC trigger structure proposed by the invention is shown in FIG. 1. The TSPC trigger provided by the invention has 8 PMOS tubes which are respectively P1, P2, P3, P4, P5, P6, P7 and P8; the NMOS transistors are 7, N1, N2, N3, N4, N5, N6, N7, and 3 inverters INV1, INV2, and INV 3. The connection relationship of each component of the invention is as follows: the grid electrode of the PMOS pipe P1 is connected with an input signal D, the drain electrode is connected with the source electrode of the P2, and the source electrode and the substrate are connected with a power supply; the grid electrode of the PMOS pipe P2 is connected with a clock signal CLK, the source electrode is connected with the drain electrode of the P1, the drain electrode node A is connected, and the substrate is connected with a power supply; the gate of the NMOS transistor N1 is connected with an input signal D, the source is connected with the drain of N2, the drain node A is connected, and the substrate is connected with the ground; the gate of the NMOS transistor N2 is connected with the reset signal Rb, the drain is connected with the source of N1, and the source is connected with the ground; the grid electrode of the PMOS pipe P3 is connected with a reset signal Rb, the source electrode and the substrate are connected with a power supply, and the drain electrode is connected with a node A; the grid electrode of the PMOS pipe P4 is connected with a reset signal R, the source electrode and the substrate are connected with a power supply, and the drain electrode is connected with the source electrode of the P5; the grid electrode of the PMOS pipe P5 is connected with a clock signal CLK, the source electrode is connected with the drain electrode of the P4, the drain electrode is connected with the node B, and the substrate is grounded; the grid electrode of the NMOS tube N3 is connected with the node A, the source electrode is connected with the drain electrode of the N4, the drain electrode is connected with the node B, and the substrate is grounded; the grid electrode of the NMOS tube N4 is connected with a clock signal CLK, the source electrode and the substrate are grounded, and the drain electrode is connected with the source electrode of the N3; the grid electrode of the NMOS tube N5 is connected with a reset signal R, the source electrode is connected with the substrate and the ground, and the drain electrode is connected with a node B; the grid electrode of the PMOS tube P6 is connected with the node B, the source electrode and the substrate are connected with the power supply, the drain electrode is connected with the node C, the grid electrode of the NMOS tube N6 is connected with the clock signal CLK, the source electrode is connected with the drain electrode of the N7, the drain electrode is connected with the node C, and the substrate is grounded; the gate of the NMOS transistor N7 is connected with the node B, the source electrode and the substrate are connected with the ground, and the drain electrode is connected with the source electrode of the N6; the grid electrode of the PNOS tube P7 is connected with a reset signal R, the source electrode and the substrate are connected with a power supply, and the drain electrode is connected with a node C; the grid electrode of the PNOS tube P8 is connected with a clock signal CLK, the source electrode is connected with the output of the inverter INV3, the drain electrode is connected with the node C, and the substrate is connected with a power supply; the input of the inverter INV1 is connected with the node C, and the output is connected with the output end Q; the input of the inverter INV2 is connected to the node C, and the output is connected to the input of the inverter INV 3; the input of the inverter INV3 is connected to the output of the inverter INV2, and the output is connected to the source of P8. The reset signals Rb and R are a pair of differential signals, that is, when R is high, Rb is low, and when R is low, Rb is high, for controlling the operation state of the TSPC.
The timing diagram of the operation of the TSPC trigger provided by the invention is shown in FIG. 2, and the basic principle is as follows: when the reset signal Rb is at a high level and R is at a low level, the flip-flop is in a reset state, and at this time, regardless of the values of the clock signal CLK and the input D, the node a is at a high level, the node B is at a low level, the node C is at a high level, and the output Q is at a low level; when the reset signal Rb is at a low level and R is at a high level, the flip-flop is in an operating state, when the input signal D is at a low level and the clock signal CLK is at a low level, the node a is at a high level, the node B is at a high level, the node C is at a high level, the output maintains the low level at the time of reset, when the clock signal CLK changes from the low level to the high level, the node a is at a high level, the node B is at a low level, and the node C is at a high level, the output Q is at a low level.
When the clock CLK becomes low and the input D becomes high, the node a becomes low, the node B becomes high, the node C becomes high, and the output Q becomes low.
From the above analysis, it can be seen that the clock jumps in data when the rising edge comes, and at low level the data maintains the loop operation, maintaining the level of the node C, so that the TSPC flip-flop can be in a high-speed circuit. Since at low levels the data of the flip-flop is lost after a while if no data is maintained in the loop, which is detrimental for high speed applications of the circuit.
In order to make the objects, technical solutions and advantages of the present invention more apparent, some details of the embodiments of the present invention should be taken into consideration in conjunction with some practical applications. We know by a rationale analysis of the operation of the flip-flops.
The high speed of the flip-flop is represented by: the low level is propagated to the output Q from the node A, B, C after the input D passes through, the propagation delay is composed of the inverter delay formed by the input D to the node A, the node B to the node C and the node C to the output Q and the discharge time from the node A to the node B, the inverter delay and the discharge time are both very short, so the propagation delay is very small, namely the propagation speed is very high; the high level is also propagated to the output Q from the node A, B, C after being respectively passed by the input D, the propagation delay is very small as the low level, and the propagation speed is very high;
but less discharge time from node a to node B than propagation of the low high level, which causes the duty cycle of the output data to change. Once fast, short clock cycles can cause errors in the logic of the output signal, where the discharge time is determined by N3 and N4, the dimensions of the N3 and N4 transistors are adjusted so that the discharge time from node a to node B is small enough to ensure that the low and high voltages are transmitted from input D to Q equally, thereby ensuring data correctness.
In addition, the integrity of the data is realized in that if no data maintaining loop exists, the data is lost after the low level lasts for a period of time, so that the data is incomplete, but after the data maintaining loop is added, when the low level is reached, the P8 is turned on, and the inverters INV2 and INV3 latch the data of the node C, so that the data is not lost, and the integrity of the data is ensured.
Claims (2)
1. A TSPC trigger with a data retention feedback loop is characterized in that 8 PMOS transistors are used, namely P1, P2, P3, P4, P5, P6, P7 and P8; the NMOS transistors are 7 and respectively composed of N1, N2, N3, N4, N5, N6, N7 and 3 inverters INV1, INV2 and INV3, the grid electrode of the PMOS transistor P1 is connected with an input signal D, the drain electrode of the PMOS transistor P2 is connected with the source electrode of the PMOS transistor P2, and the source electrode and the substrate of the PMOS transistor P2 are connected with a power supply; the grid electrode of the PMOS pipe P2 is connected with a clock signal CLK, the source electrode is connected with the drain electrode of the P1, the drain electrode is connected with the node A, and the substrate is connected with a power supply; the gate of the NMOS transistor N1 is connected with an input signal D, the source is connected with the drain of the N2, the drain is connected with the node A, and the substrate is connected with the ground; the gate of the NMOS transistor N2 is connected with the reset signal Rb, the drain is connected with the source of N1, and the source is connected with the ground; the grid electrode of the PMOS pipe P3 is connected with a reset signal Rb, the source electrode and the substrate are connected with a power supply, and the drain electrode is connected with a node A; the grid electrode of the PMOS pipe P4 is connected with a reset signal R, the source electrode and the substrate are connected with a power supply, and the drain electrode is connected with the source electrode of the P5; the grid electrode of the PMOS pipe P5 is connected with a clock signal CLK, the source electrode is connected with the drain electrode of the P4, the drain electrode is connected with the node B, and the substrate is grounded; the grid electrode of the NMOS tube N3 is connected with the node A, the source electrode is connected with the drain electrode of the N4, the drain electrode is connected with the node B, and the substrate is grounded; the grid electrode of the NMOS tube N4 is connected with a clock signal CLK, the source electrode and the substrate are grounded, and the drain electrode is connected with the source electrode of the N3; the grid electrode of the NMOS tube N5 is connected with a reset signal R, the source electrode is connected with the substrate and the ground, and the drain electrode is connected with a node B; the grid electrode of the PMOS tube P6 is connected with the node B, the source electrode and the substrate are connected with the power supply, the drain electrode is connected with the node C, the grid electrode of the NMOS tube N6 is connected with the clock signal CLK, the source electrode is connected with the drain electrode of the N7, the drain electrode is connected with the node C, and the substrate is grounded; the gate of the NMOS transistor N7 is connected with the node B, the source electrode and the substrate are connected with the ground, and the drain electrode is connected with the source electrode of the N6; the grid electrode of the PMOS pipe P7 is connected with a reset signal R, the source electrode and the substrate are connected with a power supply, and the drain electrode is connected with a node C; the grid electrode of the PMOS pipe P8 is connected with a clock signal CLK, the source electrode is connected with the output of the inverter INV3, the drain electrode is connected with a node C, and the substrate is connected with a power supply; the input of the inverter INV1 is connected with the node C, and the output is connected with the output end Q; the input of the inverter INV2 is connected to the node C, and the output is connected to the input of the inverter INV 3; the input of the inverter INV3 is connected to the output of the inverter INV2, and the output is connected to the source of P8, wherein the reset signals Rb and R are a pair of differential signals, that is, Rb is low when R is high, and Rb is high when R is low, for controlling the operation state of TSPC.
2. The TSPC flip-flop with a data retention feedback loop of claim 1, wherein when the reset signal Rb is high and R is low, the flip-flop is in a reset state, when node a is high, node B is low, node C is high, and the output Q is low, regardless of the values of the clock signal CLK and the input D; when the reset signal Rb is at a low level and R is at a high level, the flip-flop is in a working state, when the input signal D is at a low level and the clock signal CLK is at a low level, the node A is at a high level, the node B is at a high level, the node C is at a high level, the low level during reset is output and maintained, when the clock signal CLK is changed from the low level to the high level, the node A is at a high level, the node B is at a low level, the node C is at a high level, and the output Q is at a low level;
when the clock CLK becomes low and the input D becomes high, the node a becomes low, the node B becomes high, the node C becomes high, and the output Q becomes low.
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| CN109088618B (en) * | 2018-09-29 | 2022-05-20 | 上海华虹宏力半导体制造有限公司 | C2MOS trigger |
| CN110429922B (en) * | 2019-07-17 | 2023-07-04 | 上海华虹宏力半导体制造有限公司 | Trigger device |
| CN111917397B (en) * | 2020-06-18 | 2021-08-10 | 华南理工大学 | Trigger circuit and chip based on unipolar transistor |
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| US8975949B2 (en) * | 2013-03-14 | 2015-03-10 | Samsung Electronics Co., Ltd. | Integrated clock gater (ICG) using clock cascode complimentary switch logic |
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| CN101222217A (en) * | 2006-12-08 | 2008-07-16 | 索尼株式会社 | Trigger and semiconductor integrated circuit |
| CN106992769A (en) * | 2017-02-16 | 2017-07-28 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | A kind of E TSPC triggers |
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