CN107517058A - A kind of segmented current steer type DAC and its Background calibration method with calibration function - Google Patents
A kind of segmented current steer type DAC and its Background calibration method with calibration function Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1004—Calibration or testing without interrupting normal operation, e.g. by providing an additional component for temporarily replacing components to be tested or calibrated
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Abstract
A kind of segmented current steer type DAC and its Background calibration method with calibration function, belong to integrated circuit fields.Segmented current steer type DAC provided by the invention with the addition of a redundant current source unit in the array of high side current source, and its correction principle is：Utilize the high position data switch arrays in the array of first switch selection circuit control high side current source, utilize the selecting switch array in the array of second switch selection circuit control high side current source, select a current source cell to be corrected, remaining current source cell works on；Another current source is selected to correct after one calibration cycle, original is corrected current source and is switched to working condition, and each trimming process corrects a current source, and after the correction once of all current sources, second-order correction is proceeded by from first current source.Correction in the present invention is interspersed in whole work process, it is possible to correction caused error in DAC work, so as to further improve DAC performance.
Description
Technical field
The invention belongs to digital-to-analogue conversion field, relate generally to a kind of segmented current steer type DAC with calibration function and
Background calibration method based on segmented current steer type DAC.
Background technology
With the raising of technological level, MOSFET (Metal-Oxide-Semiconductor Field-Effect
Transistor, i.e. Metal-Oxide Semiconductor field-effect transistor) threshold voltage mismatch constant Avt it is less and less, electric current
Matching degree more and more higher between source, however as DAC (Digital to Analog Converter, i.e. digital-to-analogue conversion
Device) resolution ratio raising, meet 99.7% yield and INL (Integral nonlinearity, i.e. integral nonlinearity) it is small
Under conditions of 1/2LSB (Least Siginificant Bit, i.e. least significant bit), requirements of the DAC to electric current source error is got over
Come it is higher, DAC work when temperature and environmental change can cause threshold voltage and mobility as temperature changes, thus introduce
New threshold voltage mismatch, and then result in new current source mismatch problems.
Existing document proposes the front desk correction algorithm based on amplitude error and dynamic error, solves because technique is lost
With caused error, but do not solve the new current source mismatch error introduced in the DAC courses of work.
The content of the invention
For above-mentioned problem, to solve the problems, such as the new current source mismatch error of DAC operations introducing, this hair
It is bright to provide a kind of segmented current steer type DAC and its Background calibration method with calibration function.
The technical scheme is that：
A kind of segmented current steer type DAC with calibration function, including time delay module 101, the first latch 102, translate
Code device 103, first switch selection circuit 104, the second latch 105, shift register 106, second switch selection circuit 107,
3rd latch 108, low level current source array 109, high side current source array 110 and load blocks 111,
The input connection DAC low level input codes of the time delay module 101, its output end connect first latch
102 input；
The input of the low level current source array 109 connects the output end of first latch 102, and its output end connects
Connect the load blocks 111；
The input connection DAC high position input codes of the decoder 103, its output end connect the first switch selection electricity
The data input pin on road 104；
The input connection low level of the shift register 106, its clock end connection correction clock signal, its output end
The selection input of the first switch selection circuit 104 and the selection input of second switch selection circuit 107 are connected, it is described
The data input pin connection high level of second switch selection circuit 107；
The input of second latch 105 connects the output end of the first switch selection circuit 104, its output end
Connect the data input pin of high side current source array 110；
The input of 3rd latch 108 connects the output end of the second switch selection circuit 107, its output end
Connect the selection input of high side current source array 110；
High side current source array 110 is opened including high side current source unit array, high position data switch arrays and selection
Array, the termination power of high side current source unit array one are closed, the other end passes sequentially through selecting switch array and high position data
Switch arrays；
High side current source array includes output end and correction end, and the high side current source unit array is opened by described
Close array and high position data switch arrays selection connection output end or correction end, the output of high side current source array
End connection load blocks 111；
The high side current source unit array includes multiple high side current source units and a redundant current source unit, described
High side current source unit includes high side current source and correcting current source in parallel, the redundant current source unit and the high-order electricity
Stream source unit has identical structure；
The segmented current steer type DAC also includes current comparator 112 and reference current source 113, and the electric current compares
The correction end of the first input end connection high side current source array 110 of device 112, its second input connection reference current source
113, its output end output calibration fiducial value.
Specifically, the low level current source array includes low level current source cell array and low data switch arrays, institute
The termination power of low level current source cell array one is stated, the other end is by being used as the low level current source after low data switch arrays
The output end of array；The low level current source cell array includes multiple low level current source cells, the low level current source cell
Including low level current source.
Specifically, the first switch selection circuit 104 is identical including more with the structure of second switch selection circuit 107
Individual phase inverter, multiple nor gates and multiple alternative circuit units,
Data input pin of the input of the alternative circuit unit as the switch selection circuit, its Enable Pin are made
For the selection input of the switch selection circuit, its first output end connects the second input of a nor gate, and it second
Output end connects the first input end of another nor gate, wherein the first output end in first alternative circuit unit passes through
The output end of the switch selection circuit is connected after two phase inverters, the second output end in last alternative circuit unit
By connecting the output end of the switch selection circuit after two phase inverters, the output end of the nor gate passes through a phase inverter
The output end of the switch selection circuit is connected afterwards.
A kind of Background calibration method based on segmented current steer type DAC, the segmented current steer type DAC include a high position
Current source array 110, current comparator 112 and reference voltage source,
High side current source array 110 is opened including high side current source unit array, high position data switch arrays and selection
Array, the termination power of high side current source unit array one are closed, the other end passes sequentially through selecting switch array and high position data
Switch arrays；
High side current source array includes output end and correction end, and the high side current source unit array is opened by described
Close array and high position data switch arrays selection connection output end or correction end, the output of high side current source array
End connection load blocks 111；
The high side current source unit array includes multiple high side current source units and a redundant current source unit, described
High side current source unit includes high side current source and correcting current source in parallel, the redundant current source unit and the high-order electricity
Stream source unit has identical structure；
The correction end of the first input end connection high side current source array 110 of the current comparator 112, it second
Input connects reference current source 113, its output end output calibration fiducial value；
The Background calibration method comprises the following steps：
Step 1：By the high position data switch arrays in high side current source array 110 and selecting switch array from
One is selected in the high side current source unit array to be corrected current source cell and be connected to high side current source array
End is corrected, by the high side current source being corrected in current source cell compared with reference current source 113；
Step 2：Judge the difference for the high side current source and reference current source 113 being corrected in current source cell whether pre-
If in precision, i.e., whether described correction fiducial value returns in default precision when the correction fiducial value is in default precision
Step 1, step 3 is gone to when the correction fiducial value is not in default precision；
Step 3：When the electric current in the high side current source in current source cell that is corrected is more than reference current source 113, by this
Extract the one part of current in high side current source in the correcting current source being corrected in current source cell；When being corrected in current source cell
When the electric current in high side current source is less than reference current source 113, correcting current source in current source cell is corrected to height by this
Position current source mends electric current；
Step 4：By the high side current source being corrected in current source cell after step 3 corrects and reference current source
Whether 113 are compared, judge the difference for the high side current source and reference current source 113 being corrected in current source cell in default essence
In degree, the return to step one when less than default precision, the return to step three when more than default precision.
Beneficial effects of the present invention are：Real time correction is completed by way of adding redundant current source, improves DAC work
When the current source mismatch error that is introduced due to temperature change, improve DAC performance.
Brief description of the drawings
Fig. 1 is a kind of structural representation of the segmented current steer type DAC with calibration function proposed by the present invention.
Fig. 2 is the schematic flow sheet of the Background calibration method proposed by the present invention based on segmented current steer type DAC.
Fig. 3 is the circuit diagram of first switch selection circuit 104 and second switch selection circuit 107 in embodiment.
Fig. 4 is the circuit diagram of lowest order current source in embodiment.
Embodiment
The present invention is described in detail below according to the drawings and specific embodiments.
It is a kind of structural representation of the segmented current steer type DAC with calibration function proposed by the present invention as shown in Figure 1
Figure, time delay module 101 are connected with DAC low level input codes, the output end LSB_IN of time delay module 101<M-1:0>(wherein M is M+N points
Lower bit number in segmentation current steering DAC, upper bit number N) it is connected with the input of the first latch 102, the first latch 102
Output end LSB_OUTN<M-1:0>And LSB_OUTP<M-1:0>, it is respectively used to assign the lower-order digit of low level current source array 109
According to the LSB_OUTN of switch arrays<M-1:0>And LSB_OUTP<M-1:0>Signal value, the value flow to for control electric current ource electric current
OUTN ends or OUTP ends；Load blocks 111 include first resistor R1 and second resistance R2, low level current source array 109
OUTN is connected with the second resistance R2 upper ends in load blocks 111, OUTP and the load blocks 111 of low level current source array 109
In first resistor R1 upper ends be connected；The first resistor R1 and second resistance R2 of load blocks 111 lower end are all grounded；Decoder
103 inputs are connected with DAC high-order input code, the output end MSB_IN_A of decoder 103<n-1:0>(wherein n=2N- 1) connect
The data input pin IN of first switch selection circuit 104, the output end MSB_OUT_A of first switch selection circuit 104<n:0>With
The input of second latch 105 is connected, the output end MSB_OUTN of the second latch 105<n:0>And MSB_OUTP<n:0>Respectively
For the MSB_OUTN for the high position data switch arrays for assigning high side current source array 110<n:0>And MSB_OUTP<n:0>Signal
Value, the value flow to OUTN ends or OUTP ends for control electric current ource electric current；The input connection low level of shift register 106
DGND, the connection correction of its input end of clock clock signal CLK_CAL, the output end SEL of shift register 106<n-1:0>Connect
The selection input SEL of the one switch selection circuit 104 and selection input SEL of second switch selection circuit 107, second switch
The data input pin IN of selection circuit 107 meets high level DVDD, the output end SEL_OUT_A of second switch selection circuit 107<n:
0>Meet the input of the 3rd latch 108, the output end SEL_OUT of the 3rd latch 108<n:0>With
It is respectively used to assign the SEL_OUT of the selecting switch array of high side current source array 110<n:0>AndLetter
Number value, the value flows to output end for control electric current ource electric current and still corrects end；The output end OUTN of high side current source array 110
Connect the second resistance R2 upper ends in load blocks 111 and be connected with the OUTN of low level current source array 109, high side current source array
110 OUTP ends are connected with the OUTP ends of the first resistor R1 upper ends in load blocks 111 and low level current source array 109, high
The output end OUT_CAL of position current source array 110 is connected with the first input end of current comparator 112, current comparator 112
The I_REF that second input exports with reference current source 113 is connected.
Wherein high side current source array 110 includes high side current source unit array, high position data switch arrays MSB_
OUTN<n:0>And MSB_OUTP<n:0>And selecting switch array SEL_OUT<n:0>WithHigh-order electricity
Stream source unit array includes multiple high side current source units and a redundant current source unit, and high side current source unit includes parallel connection
High side current source I_MSB and correcting current source I_CAL, redundant current source unit and the high side current source unit have identical
Structure.Traditional N positions high position DAC current source amounts to n, and the present invention will set a redundant current source to be used to correct more, high-order
Data switch array MSB_OUTN<n:0>And MSB_OUTP<n:0>Control electric current source switch is turned on and off, selecting switch array
SEL_OUT<n:0>,Control electric current source is operated in correcting state or working condition.
DAC provided by the invention with the addition of a redundant current source unit, its correction principle in the array of high side current source
For：The high position data switch arrays in the array of high side current source are controlled using first switch selection circuit 104, utilize second switch
Selection circuit 107 controls the selecting switch array in the array of high side current source, selects a current source cell and is corrected, its
Aftercurrent source unit works on；Another current source is selected to correct after one calibration cycle, original is corrected current source and is switched to
Working condition, each trimming process correct a current source, after the correction once of all current sources, since first current source
Carry out second-order correction.The selection of the selection input input of first switch selection circuit 104 and second switch selection circuit 107
Signal SEL<n-1:0>It is to be produced by shift register 106, shift register 106 often shifts once just selects one not successively
Same current source cell is corrected, and the current source cell chosen terminates to the first of current comparator 112 by correction
The reference current source that input connects with the input of current comparator 112 second is corrected by the method for Approach by inchmeal more afterwards.
Using segmented 8+6 (i.e. highest significant position is 6bit, least significant bit 8bit) current steer type DAC in the present embodiment
Exemplified by further illustrate the present invention.
Illustrate that lowest order current source is 1 PMOS (p-type Metal-Oxide Semiconductor field effect transistor in the DAC at this
Pipe) composition current source, as shown in figure 4, the grid end of PMOS meets bias voltage VBIAS, source meets supply voltage VDD, and drain terminal connects
Switched accordingly in low data switch arrays.
Each high side current source structure in the present embodiment in high side current source array 110 is identical, current value is equal, adopts
With 28Individual lowest order current source is in parallel；Correcting current source is unique step or binary current source；High side current source array 110 by
26- 1 high side current set of source into.
Correcting process is as shown in Fig. 2 it is concretely comprised the following steps：
Step 201：Decoder 103 carries out thermometer decoded to DAC high positions input code and is input to first switch selection electricity
The data input pin on road 104；The data input pin of second switch selection circuit 107 puts high level.
Step 202：The output control first switch selection circuit 104 and second switch selection circuit of shift register 106
107 selection input, two switch selection circuits control the seniority top digit of high side current source array by two latch respectively
According to switch arrays and selecting switch array, a current source cell is selected to be corrected, remaining current source cell works on, its
In be corrected the first input end that current source cell is connected to correction end connection current comparator, remaining current source cell is connected to output
End.
Step 203：By the high side current source being corrected in current source cell compared with reference current source, wherein reference current
Source size is 256 times of low level current source current value size.
Step 204：Judge be corrected current source cell high side current source and reference current source difference between currents whether
In predetermined accuracy, select in next calibration cycle return to step 202 next to be corrected electric current if in predetermined accuracy
Source unit；If the continuation step 205 without if.
Step 205 passes through when the high side current ource electric current being corrected in current source cell is more than reference current ource electric current
The one part of current in the high side current source in current source cell that is corrected is extracted in the correcting current source being corrected in current source cell, when
When being corrected the electric current in high side current source in current source cell and being less than reference current source, corrected by being corrected in current source cell
Current source gives the high side current source being corrected in current source cell to mend electric current.
Step 206：The high side current source being corrected in current source cell and the reference electricity of electric current will be increased and decreased by step 205
Stream source is compared, and judges that its difference between currents whether in predetermined accuracy, is returned if in predetermined accuracy in next calibration cycle
Step 202 is returned to select next to be corrected current source cell；If without if return to step 205 to being corrected in current source cell
High side current source carry out plus-minus current practice again.
Trimming process unlike traditional front desk correction, correction be it is lasting in the DAC courses of work, so can be with
Caused error correction is returned during DAC is worked.Therefore, under this correcting algorithm, the performance of current steering DAC can be shown
Write and improve.
Fig. 3 is the circuit diagram of first switch selection circuit 104 and second switch selection circuit 107 in the present embodiment, including
Multiple phase inverters, multiple nor gates and multiple alternative circuit units, described in the input of the alternative circuit unit is used as
The data input pin of switch selection circuit, selection input of its Enable Pin as the switch selection circuit, its first output
Second input of one nor gate of end connection, its second output end connect the first input end of another nor gate, wherein the
The first output end in one alternative circuit unit by connecting the output end of the switch selection circuit after two phase inverters,
The second output end in last alternative circuit unit after two phase inverters by connecting the defeated of the switch selection circuit
Go out end, the output end of the nor gate is by connecting the output end of the switch selection circuit after a phase inverter.
IN<0>Connect first alternative unit, first alternative circuit unit OUTA output two phase inverter structure of termination
Into buffer buffer input, buffer buffer output end is OUT<0>；First alternative circuit unit
OUTB ends export the A inputs for connecing first nor gate, B input second alternative circuit unit of termination of first nor gate
OUTA ends, the output end of first nor gate connects the input of phase inverter, and the output end of the phase inverter is OUT<1>；Second
The input of alternative circuit unit is IN<1>, the A ends of OUTB second nor gate of termination of second alternative circuit unit,
The output of second nor gate connects phase inverter, and the output of the phase inverter is OUT<2>；63rd alternative circuit list by that analogy
The input of member is IN<62>, the B ends of OUTA output the 62nd nor gate of termination of the 63rd alternative circuit unit, the 62nd or
The output end of NOT gate connects phase inverter, and the output of the phase inverter is OUT<62>, the OUTB output ends of the 63rd alternative circuit unit
The buffer buffer that two phase inverters are formed is met, buffer buffer outputs are OUT<63>；Wherein from first to the 63rd
The Enable Pin of individual alternative circuit unit meets the output SEL of shift register 106 successively<62:0>.
Handoff procedure in switch selection circuit trimming process is as follows：
The IN of second switch selection circuit 107<62:0>One direct power supply, the second switch selection electricity before correction starts
The signal SEL of the selection input input on road 107<62:0>High level all is set to, now the OUTB=of alternative circuit unit
IN, OUTA=0；Now OUT<0>=0, OUT<1>=IN<0>, OUT<2>=IN<1>... ..., OUT<63>=IN<62>, under
SEL when one correction clock edge is arrived<0>Level is set low, now OUT<0>=IN<0>, OUT<1>=0, remaining output is constant,
The SEL when next clock edge is arrived again<1>Set low level, SEL<0>Keep low level constant, now, OUT<1>=IN<1>,
OUT<2>=0, the like by 63 times switching after SEL<0:62>All it is low level, now OUT<0>=IN<0>, OUT<1
>=IN<1>... ..., OUT<62>=IN<62>, OUT<63>=0.
The fresh flower IN of the data input pin of first switch selection circuit 104<62:0>For the output of decoder 103, it is selected
The signal SEL of input<0:62>Handoff procedure it is identical with second switch selection circuit 107.
The output of second switch selection circuit 107 and first switch selection circuit 104 is synchronous, second switch selection circuit
107 output is used for the SEL_OUT for assigning high side current source array 110<63:0>Signal value, work as SEL_OUT<N>Value to be low
N-th current source is switched to correcting state during level, remaining normal work.In once complete trimming process, from first
Corrected successively to last one, work as SEL<62:0>All current sources are completed once to correct when being all switched to low level, SEL<
62:0>High level is set to, second-order correction is carried out when next correction clock edge is arrived.
In summary, Background calibration method proposed by the present invention can accomplish real time correction, correct and produced when DAC works
Electric current source error so that DAC performance is significantly improved.
Above example is used merely to explain technical scheme, it will be apparent to those skilled in the art that not departing from
In the case of the principle of the invention and to a certain module or some modules are improved or equivalent substitution, the protection model in the present invention
Among enclosing.
Claims (4)
1. a kind of segmented current steer type DAC with calibration function, including time delay module (101), the first latch (102),
Decoder (103), first switch selection circuit (104), the second latch (105), shift register (106), second switch choosing
Select circuit (107), the 3rd latch (108), low level current source array (109), high side current source array (110) and load blocks
(111),
The input connection DAC low level input codes of the time delay module (101), its output end connect first latch
(102) input；
The input of the low level current source array (109) connects the output end of first latch (102), and its output end connects
Connect the load blocks (111)；
The input connection DAC high position input codes of the decoder (103), its output end connect the first switch selection circuit
(104) data input pin；
The input connection low level of the shift register (106), its clock end connection correction clock signal, its output end connect
Meet the selection input of the first switch selection circuit (104) and the selection input of second switch selection circuit (107), institute
State the data input pin connection high level of second switch selection circuit (107)；
The input of second latch (105) connects the output end of the first switch selection circuit (104), its output end
Connect the data input pin of high side current source array (110)；
The input of 3rd latch (108) connects the output end of the second switch selection circuit (107), its output end
Connect the selection input of high side current source array (110)；
Characterized in that, high side current source array (110) includes high side current source unit array, high position data switch arrays
With selecting switch array, the termination power of high side current source unit array one, the other end pass sequentially through selecting switch array and
High position data switch arrays；
High side current source array includes output end and correction end, and the high side current source unit array passes through the switch arrays
Row and high position data switch arrays selection connection output end or correction end, the output end of high side current source array connect
Connect load blocks (111)；
The high side current source unit array includes multiple high side current source units and a redundant current source unit, the high position
Current source cell includes high side current source and correcting current source in parallel, the redundant current source unit and the high side current source
Unit has identical structure；
The segmented current steer type DAC also includes current comparator (112) and reference current source (113), the electric current compare
The correction end of the first input end connection high side current source array (110) of device (112), the connection of its second input is with reference to electricity
Stream source (113), its output end output calibration fiducial value.
2. the segmented current steer type DAC according to claim 1 with calibration function, it is characterised in that the low level
Current source array includes low level current source cell array and low data switch arrays, described low level current source cell array one end
Connect power supply, the other end is by being used as the output end of the low level current source array after low data switch arrays；The low level electricity
Stream source unit array includes multiple low level current source cells, and the low level current source cell includes low level current source.
3. the segmented current steer type DAC according to claim 1 with calibration function, it is characterised in that described first
Switch selection circuit (104) is identical with the structure of second switch selection circuit (107), including multiple phase inverters, multiple nor gates
With multiple alternative circuit units,
Data input pin of the input of the alternative circuit unit as the switch selection circuit, its Enable Pin is as institute
The selection input of switch selection circuit is stated, its first output end connects the second input of a nor gate, its second output
End connects the first input end of another nor gate, wherein the first output end in first alternative circuit unit passes through two
The output end of the switch selection circuit is connected after phase inverter, the second output end in last alternative circuit unit passes through
The output end of the switch selection circuit is connected after two phase inverters, the output end of the nor gate after a phase inverter by connecting
Connect the output end of the switch selection circuit.
A kind of 4. Background calibration method based on segmented current steer type DAC, it is characterised in that the segmented current steer type
DAC includes high side current source array (110), current comparator (112) and reference voltage source,
High side current source array (110) includes high side current source unit array, high position data switch arrays and selecting switch
Array, the termination power of high side current source unit array one, the other end passes sequentially through selecting switch array and high position data is opened
Close array；
High side current source array includes output end and correction end, and the high side current source unit array passes through the switch arrays
Row and high position data switch arrays selection connection output end or correction end, the output end of high side current source array connect
Connect load blocks (111)；
The high side current source unit array includes multiple high side current source units and a redundant current source unit, the high position
Current source cell includes high side current source and correcting current source in parallel, the redundant current source unit and the high side current source
Unit has identical structure；
The correction end of the first input end connection high side current source array (110) of the current comparator (112), it second
Input connection reference current source (113), its output end output calibration fiducial value；
The Background calibration method comprises the following steps：
Step 1：By the high position data switch arrays in high side current source array (110) and selecting switch array from institute
Selection one in high side current source unit array is stated to be corrected current source cell and be connected to the school of high side current source array
Anode, by the high side current source being corrected in current source cell compared with reference current source (113)；
Step 2：Judge the difference for the high side current source and reference current source (113) being corrected in current source cell whether default
In precision, i.e., described correction fiducial value returns to step whether in default precision when the correction fiducial value is in default precision
Rapid one, go to step 3 when the correction fiducial value is not in default precision；
Step 3：When the electric current in the high side current source in current source cell that is corrected is more than reference current source (113), pass through the quilt
Extract the one part of current in high side current source in correcting current source in correcting current source unit；It is high when being corrected in current source cell
The electric current of position current source is when being less than reference current source (113), and correcting current source in current source cell is corrected to high by this
Position current source mends electric current；
Step 4：By the high side current source being corrected in current source cell after step 3 corrects and reference current source
(113) it is compared, judges the difference for the high side current source and reference current source (113) being corrected in current source cell whether pre-
If in precision, the return to step one when less than default precision, the return to step three when more than default precision.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108449089A (en) * | 2018-03-23 | 2018-08-24 | 上海唯捷创芯电子技术有限公司 | Realize current steering digital-to-analog converter, chip and the communication terminal of digital calibration |
| CN109639276A (en) * | 2018-11-23 | 2019-04-16 | 华中科技大学 | DT Doubling Time intertexture current steer type DAC with DDRZ calibration function |
| CN109921798A (en) * | 2019-03-20 | 2019-06-21 | 成都振芯科技股份有限公司 | Segmented current-steering digital-to-analog converter circuit and calibration method |
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| CN110910824A (en) * | 2019-11-29 | 2020-03-24 | 西安理工大学 | Non-linear Gamma curve generation system and method for improving OLED display effect |
| CN110910824B (en) * | 2019-11-29 | 2022-02-25 | 西安理工大学 | Non-linear Gamma curve generation system and method for improving OLED display effect |
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| CN112468153B (en) * | 2020-11-26 | 2022-10-28 | 南京邮电大学 | Segmented current rudder DAC structure |
| WO2024117779A1 (en) * | 2022-11-30 | 2024-06-06 | 삼성전자 주식회사 | Current-steering digital-to-analog converter device for performing calibration function, and operating method therefor |
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