CN107505971A - A kind of LDO adjuster frequency compensation schemes for driving large current load - Google Patents
A kind of LDO adjuster frequency compensation schemes for driving large current load Download PDFInfo
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- CN107505971A CN107505971A CN201710821127.3A CN201710821127A CN107505971A CN 107505971 A CN107505971 A CN 107505971A CN 201710821127 A CN201710821127 A CN 201710821127A CN 107505971 A CN107505971 A CN 107505971A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/461—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using an operational amplifier as final control device
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- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The invention belongs to field of analog integrated circuit, specifically proposes a kind of LDO adjuster frequency compensation schemes for driving large current load.Including the two stage amplifer with approximate first order pole, buffer stage, output stage.The two-stage error amplifier that the present invention innovatively introduces capacitance compensation and makes two relatively low limits of frequency to be present originally is changed into approximate one-pole system, and the pole location can manual control, the present invention is set to the higher secondary limit of frequency, after parasitic zero point is introduced using output capacitance dead resistance (ESR), the limit must be compensated by appropriate.With the output limit of load change still for dominant pole, by reasonably selecting output end filter capacitor size its caused zero point is located at maximum loop gain G BW frequencies.Other internal parasitic zero points are because special circuit structure is located at high frequency.Finally, the frequency stabilization in total current load excursion is realized on whole low pressure difference linear voltage regulator feedback control loop, and phase margin is more than 50 degree.
Description
Technical field
The present invention relates to field of power management, is mended more particularly to a kind of LDO adjusters frequency for driving large current load
Repay scheme.
Background technology
In recent years, widely using due to various electronic products, it is essential as the power-supply management system for providing power,
Power management section is most important for the normal use of product.The linear voltage-stablizer of the adjuster of main flow and switch voltage-stabilizing at present
The class of device two, specific application scenario generally require to compromise.Due to low pressure difference linear voltage regulator LDO (Low Dropout Linear
Regulator) there is lower output voltage noise, ripple compared with Switching Power Supply, and circuit structure is simpler, needs more
Few peripheral components, a kind of selection of high performance-price ratio so LDO still can yet be regarded as.
In LDO design process, good frequency response is the precondition of adjuster steady operation.And in some drivings
In the system of large current load, because load impedance excursion is very big (several ohm to several kilohms) so that output limit
It is violent with power tube change in gain, it may occur however that system oscillation, to cause frequency stabilization sex chromosome mosaicism.It is traditional it is miller-compensated can not
Effectively cope with so big excursion.Therefore, find the high reliability frequency compensation schemes under large current load and
Realized with simple structure as far as possible and be not take up excessive chip area and be particularly important.
The content of the invention
The technical problem to be solved in the present invention is to provide the low pressure difference linear voltage regulator under a kind of change of large current load
Frequency compensation schemes, the frequency stabilization of system and quick reply load changing can be realized, while circuit structure is simple, not excessively
Increase the area and power consumption of low pressure difference linear voltage regulator.
A kind of frequency compensation schemes of low pressure difference linear voltage regulator under large current load change, it is characterised in that including with
Lower module：Bandgap voltage reference, the two-stage error amplifier with first order pole, buffer stage, output stage.Bandgap voltage reference
Stable reference voltage is provided for pre-adjustment module；Pre-adjustment module includes error amplifier, buffer stage, output stage, band gap base
Quasi- voltage is adjusted to the voltage to be exported after pre-adjustment module；Filter capacitor is followed by prevent locking system responsive load to change
When, output voltage excessive drift；The output voltage after electric capacity is input to error amplifier block after filtering, former using negative-feedback
Reason, there is provided not with input supply voltage and the output voltage of load change.
The novelty of patent of the present invention is that the two-stage error amplifier for making two relatively low limits of frequency to be present originally is changed into
Approximate one-pole system, and the pole location can manual control, the higher secondary limit of frequency is arranged in this patent of invention, in profit
After introducing parasitic zero point with output capacitance dead resistance (ESR), the limit must be compensated by appropriate.In addition, with the defeated of load change
Go out limit and be still arranged on for dominant pole, the limit of output end filter capacitor at maximum loop gain G BW frequencies.Finally, realize
Frequency stabilization in total current load excursion, and phase margin is more than 50 degree.
Therefore, patent of the present invention has the following advantages：(1) even if under large current load change, linear regulator system
It is sufficiently stable；(2) by setting the higher secondary limit of frequency, and parasitic capacitance zero point is suitably introduced into, is advantageous to extend unit ring
Road gain bandwidth, so as to improve system response time；(3) in total current load excursion, more than 50 degree of phase margin has
Help improve output transient response, including smaller overshoot and undershoot voltage；(4) filter capacitor that output end adds helps to change
Kind output voltage ripple；
Brief description of the drawings
The two-stage error amplifier physical circuit that it is approximately one-pole system that Fig. 1, which is,；
Fig. 2 is the small-signal model figure of the two-stage error amplifier second level；
Fig. 3 is the integrated circuit for realizing driving large current load LDO frequency compensation schemes；
Fig. 4 is the Bode diagram of compensation scheme zero pole point approximate location；
Fig. 5 is Figure of abstract；
Embodiment
To become apparent from the features described above of the present invention and advantage, below in conjunction with the accompanying drawings to the embodiment of the present invention
It is described in detail.
The inside two-stage error amplifier of the LDO linear voltage regulators of driving large current load shown in Fig. 1, including first order band
The fully differential input stage of the double-width grinding both-end output of ohmic load, the second level are the amplifier of wide linear input range, wherein
Q10, Q11 pipe both provided suitable bias current for the second level, while were used as the small-signal of the second level in the form of emitter follower again
Input, Q10 is second level inverting input, and Q11 is in-phase input end.Two branch current sums where Q6, Q9 pipe are Q12
The bias current that pipe provides, the pipe of Q4, Q7 two respectively by Q5, go over by the branch current mirror image where Q6 pipes, and Q4, Q5, Q6, Q7 are managed
The mismatch penetrated grade degeneration resistance R4, R5, R6, a R7, can effectively improve image current.Q4, Q7 are the difference of base stage coupling
Divide input, Q8, Q9 make mirror current source load, to improve the second stage gain.Emitter-base bandgap grading degeneration resistance R4, R7 can also be significantly increased
The linear input range of two level amplifier, resistance Rz and electric capacity C effect are to carry out frequency compensation, and the frequency for establishing system is higher
Secondary limit.
Fig. 2 show the small-signal model figure of the two-stage error amplifier second level, for the sake of simplicity, might as well not consider first
Q4, Q5, Q6, Q7 pipe penetrate grade degeneration resistance R4, R5, R6, a R7, and both ends Differential Input is respectively-vid/2, vid/2, wherein, two
The transistor Q5, Q6 of pole pipe connection are under the conditions of small-signal, and its parallel resistance is much larger than 1/gm5,1/gm6, and resistance is directly designated as
1/gm5、1/gm6.Q4, Q5, Q6, Q7 pipe are identical matching transistor, and Q8, Q9 are the image current source transistor of matching, are made
Gm8=gm9=gm, c π 8=c π 9=c π, equal ro8, ro9 are designated as ro1, ro2 respectively.A points are mirror current source input section
Point and current potential are designated as v1, and B points are output node and voltage is designated as vo, and bias current sources resistance ro13 voltage is designated as Vp.Assuming that
Differential Input pipe is perfect symmetry, and the input voltage of two inputs is equivalent anti-phase, when a polygonal voltage rises, another side
Voltage declines, so the voltage constant at bias current sources Q13 small-signal resistance ro13 both ends is constant, so Vp is AC deposition.
V4=-vid/2, v5=vid/2 are apparent from, ro4, ro5 ignore in addition, and Q4 colelctor electrodes small-signal current is-gm4vid/2,
By gm7=gm4, Q5 colelctor electrodes small-signal current is gm4vid/2.Formula (1) is that error amplifier second level small-signal compensates net
Transfer function after network simplification：
The zero pole point of the error amplifier second level is：
z1For Left half-plane image current zero point caused by A points, in high frequency treatment；Z2 is left partly flat caused by current-limiting resistance Rz
Face current limliting zero point, also in high frequency treatment, the alleviation a large amount of parasitic poles of high frequency are contributed to cause phase bust；pEAFor error amplifier
Dominant pole, pmirrorFor high frequency images limit caused by A points；Therefore, whole error amplifier is similar to one-pole system, and pole
Point pEACan be by adjusting CcManual control.
Fig. 3 is the integrated circuit for realizing driving large current load LDO frequency compensation schemes, shown：Two-stage error amplifier,
Buffer stage, output stage.In buffer stage, Q15 is penetrates a grade follower, and Q13 is current source, and Q14 is connected using diode, put in error
The damage to prevent Q15 is turned on when device output voltage swing is excessive greatly；Q16, Q17 can improve current gain to collect cascode driving stage altogether
With driving power pipe.In output stage, the Q10 and resistance R2 of diode connection provide biasing for power tube Q11, and in power tube base
Pole forms a low-impedance node, the node is corresponded to limit and moves on to high frequency so that negligible；RE2、RE2It is anti-for series connection partial pressure
Present network, COFor output capacitance, RESRFor output capacitance dead resistance, CBYFor filter capacitor.
Fig. 3 output node impedances are
Wherein, R=ro//(RE2+RE2)//RL, CB=CL+CPCBY, C is setO＞ ＞ CB, R ＞ ＞ RESR, two limits are very open,
Output end pole dead-center position can be obtained：
Low frequency output capacitance dominant pole
High-frequency bypass capacitor limit
Dead resistance zero point
Fig. 4 is the Bode diagram of compensation scheme zero pole point approximate location, must set each zero pole point parameter by reasonable, can obtain
To effect as shown in Figure 4.Dominant pole poWith load current iLChange, but dominant pole position is always positioned at, parasitic zero point zESRThan secondary
Limit pEASlightly by preceding contributing to spread bandwidth.pBFor limit caused by filter capacitor, maximum loop gain G BW frequencies can be arranged on
Near rate.Finally, the frequency stabilization in total current load excursion is realized, and phase margin is more than 50 degree.
The above described is only a preferred embodiment of the present invention, any formal limitation not is made to the present invention.Appoint
What those skilled in the art, without departing from the scope of the technical proposal of the invention, all using the side of the disclosure above
Method and technology contents make many possible changes and modifications to technical solution of the present invention, or are revised as the equivalent reality of equivalent variations
Apply example.Therefore, every content without departing from technical solution of the present invention, the technical spirit according to the present invention are done to above example
Any simple modifications, equivalents, and modifications, still fall within technical solution of the present invention protection in the range of.
Claims (5)
- A kind of 1. LDO adjuster frequency compensation schemes for driving large current load, it is characterised in that including：Error amplifier, delay Rush level and output stage.
- 2. a kind of LDO adjuster frequency compensation schemes for driving large current load according to claim 1, its feature exist In the error amplifier includes：The first order is the fully differential input stage with ohmic load R1 and R2；The second level uses mirror image Current source Q4, Q5, Q6, Q7, Q8, Q9 are biased, and Q5, Q6, the Q8 connected using diode makes respective nodes be changed into low-impedance node, So that corresponding limit is respectively high frequency poles, compensating electric capacity Cc is added in Q9 both ends.
- 3. a kind of LDO adjuster frequency compensation schemes for driving large current load according to claim 1, its feature exist In the buffer stage includes：Q15 is connected to Q15 both ends and shielded as a grade follower, the Q14 of diode connection is penetrated, Q14 colelctor electrode is connected to Q15 base stage and emitter stage is connected to Q15 emitter stage, and Q13 provides biasing as current source；Q16 Common collection common-emitter configuration is formed with Q17, there is provided high current gain, the Q18 of diode connection connects with resistance R9 to be provided partially for Q17 Put.
- 4. a kind of LDO adjuster frequency compensation schemes for driving large current load according to claim 1, its feature exist In the output stage includes：For Q20 as power tube, emitter stage meets Vin, and colelctor electrode connects output；The Q19 and R10 of diode connection Series connection, Q19 emitter stage meet Vin, and base stage meets R10, R10 another termination Q20；R11 termination Q20 base stage, a termination Q17 colelctor electrode；Resistance RE1 and RE2 are connected between output and ground and serve as partial pressure feedback network, RE1 and RE2 common connection Place connects the negative input end of buffer amplifier.
- 5. a kind of LDO adjuster frequency compensation schemes for driving large current load, it is characterised in that two-stage error amplifier passes through Compensating electric capacity Cc forms approximate one-pole system, and by its caused limit set with the secondary limit in loop gain 0dB bandwidth, Reset caused by output capacitance dead resistance is in its slightly forward position.Limit caused by output end filter capacitor CBY is set Near loop gain maximum 0dB bandwidth.
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| CN201710821127.3A CN107505971A (en) | 2017-09-13 | 2017-09-13 | A kind of LDO adjuster frequency compensation schemes for driving large current load |
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| CN201710821127.3A CN107505971A (en) | 2017-09-13 | 2017-09-13 | A kind of LDO adjuster frequency compensation schemes for driving large current load |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111026230A (en) * | 2019-12-16 | 2020-04-17 | 成都海光微电子技术有限公司 | LDO device and storage equipment |
| CN111221373A (en) * | 2020-01-16 | 2020-06-02 | 东南大学 | Low dropout power supply ripple suppression linear voltage regulator |
| CN111221374A (en) * | 2020-01-16 | 2020-06-02 | 东南大学 | Full-integrated load pole compensation linear voltage regulator |
| CN112564644A (en) * | 2020-11-24 | 2021-03-26 | 华南理工大学 | Unipolar transistor-based amplifier, chip and method |
| CN112947670A (en) * | 2021-04-01 | 2021-06-11 | 苏州喻芯半导体有限公司 | LDO circuit capable of fast responding |
| CN113849033A (en) * | 2021-09-27 | 2021-12-28 | 电子科技大学 | Linear voltage stabilizer with impedance attenuation compensation |
-
2017
- 2017-09-13 CN CN201710821127.3A patent/CN107505971A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111026230A (en) * | 2019-12-16 | 2020-04-17 | 成都海光微电子技术有限公司 | LDO device and storage equipment |
| CN111026230B (en) * | 2019-12-16 | 2021-05-28 | 成都海光微电子技术有限公司 | LDO device and storage equipment |
| CN111221373A (en) * | 2020-01-16 | 2020-06-02 | 东南大学 | Low dropout power supply ripple suppression linear voltage regulator |
| CN111221374A (en) * | 2020-01-16 | 2020-06-02 | 东南大学 | Full-integrated load pole compensation linear voltage regulator |
| CN111221374B (en) * | 2020-01-16 | 2022-01-28 | 东南大学 | Full-integrated load pole compensation linear voltage regulator |
| CN112564644A (en) * | 2020-11-24 | 2021-03-26 | 华南理工大学 | Unipolar transistor-based amplifier, chip and method |
| CN112947670A (en) * | 2021-04-01 | 2021-06-11 | 苏州喻芯半导体有限公司 | LDO circuit capable of fast responding |
| CN113849033A (en) * | 2021-09-27 | 2021-12-28 | 电子科技大学 | Linear voltage stabilizer with impedance attenuation compensation |
| CN113849033B (en) * | 2021-09-27 | 2022-10-04 | 电子科技大学 | Linear voltage stabilizer with impedance attenuation compensation |
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