CN107493105B - Gyro moment current high-resolution conversion circuit - Google Patents
Gyro moment current high-resolution conversion circuit Download PDFInfo
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- CN107493105B CN107493105B CN201710594936.5A CN201710594936A CN107493105B CN 107493105 B CN107493105 B CN 107493105B CN 201710594936 A CN201710594936 A CN 201710594936A CN 107493105 B CN107493105 B CN 107493105B
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Abstract
A gyro moment current high resolution conversion circuit is characterized in that a moment current integrating circuit generates an integrating voltage according to gyro moment current and outputs the integrating voltage to an analog-to-digital conversion circuit, the analog-to-digital conversion circuit generates a first data input and a saturation overflow signal input and outputs the first data input and the saturation overflow signal input to an FPGA control circuit, the FPGA control circuit generates a second data input, a digital-to-analog conversion circuit clock control signal and a DA control signal and outputs the second data input, the digital-to-analog conversion circuit clock control signal and the DA control signal to the digital-to-analog conversion circuit, and the digital-to-analog conversion circuit generates current output and sends the current. Compared with the prior art, the circuit is realized by changing an analog switch current feedback type circuit consisting of a traditional precise voltage source and a switch into a digital-to-analog conversion circuit, is not limited by the switching frequency, improves the output maximum frequency value and has good use value.
Description
Technical Field
The invention relates to the field of circuit design, in particular to a gyro moment current high-resolution conversion circuit.
Background
The traditional wide-range three-floating inertial attitude sensor has the pulse equivalent (DEG/pulse) of 10-5The order of the pulse equivalent technical index of the optical cabin type for the very high-precision three-floating gyroscope reaches 10-7The improvement is nearly two orders of magnitude. The existing double-scale analog-to-digital conversion technology based on the scheme of analog feedback and VF conversion is limited by two factors of switching frequency and scale gear in VF conversion, so that high-resolution output is difficult to realize. In order to further improve the pulse equivalent and solve the problem of high-resolution digital output, a new gyro moment current high-resolution conversion circuit scheme needs to be provided to realize conversion between high-output resolution and a large dynamic range and meet the requirements of model tasks.
Disclosure of Invention
The technical problem solved by the invention is as follows: the defects of the prior art are overcome, and the gyro moment current high-resolution conversion circuit is provided.
The technical solution of the invention is as follows: a gyro moment current high resolution conversion circuit comprises a moment current integrating circuit, an analog-to-digital conversion circuit, an FPGA control circuit and a digital-to-analog conversion circuit, wherein:
the moment current integrating circuit generates an integrating voltage according to the gyro moment current and outputs the integrating voltage to the analog-digital conversion circuit, the analog-digital conversion circuit generates a first data input and a saturation overflow signal input and outputs the first data input and the saturation overflow signal input to the FPGA control circuit, the FPGA control circuit generates a second data input, a clock control signal of the digital-analog conversion circuit and a DA control signal and outputs the second data input, the clock control signal of the digital-analog conversion circuit and the DA control signal to the digital-analog conversion circuit, the clock control signal of the analog-digital conversion circuit is generated to the analog-digital conversion circuit, and the.
The moment current integration circuit comprises a capacitor C101, a capacitor C104, an integrated operational amplifier U101, a resistor R102, a resistor R103, a resistor R104, a resistor R105, a resistor R106, a resistor R107 and a resistor R108;
the gyro moment current signal TQ-is filtered by a capacitor C104 and then sent to a circuit formed by resistors R103 and R105 for shunt, the shunted signal is connected to the reverse end of the integrated operational amplifier U101, an A-end current output signal DAC _ IA of the digital-to-analog conversion circuit is shunted by a circuit formed by resistors R101 and R102, the shunted signal is connected to the reverse end of the integrated operational amplifier U101, a B-end current output signal DAC _ IB of the digital-to-analog conversion circuit is shunted by a circuit formed by resistors R106, R104, R107 and R108, the shunted signal is connected to the forward end of the integrated operational amplifier U101, the capacitor C101 is connected with the reverse end and the output end of the integrated operational amplifier U101, and the output end of the integrated operational amplifier U101 generates an integral voltage and sends the integral voltage to the analog-to-digital conversion.
The analog-to-digital conversion circuit comprises resistors R201, R202 and R203, diodes D201 and D202, capacitors C202, C203, C204, C205, C206 and C207, and a chip AD9243 AS;
the integrated voltage is limited by a circuit composed of resistors R201 and R202, and then is connected with a VINA pin of a chip AD9243AS, diodes D201 and D202 form a voltage clamp circuit, the cathode of D201 is connected with a positive voltage, the anode of D201 is connected with the cathode of D202, the anode of D202 is grounded, capacitors C202, C203, C204 and C205 form a filter circuit, the two ends of C203 are respectively connected with CAPT pins and CAPB pins of AD92 AS, C203 and C205 are connected in parallel, the two ends of C205 are respectively connected with C202 and C204, the other ends of C202 and C204 are grounded, the resistor R203 is connected with a VINB pin and a VREF pin of AD92 AS, the capacitors C206 and C207 are connected in parallel and then connected with a VREF pin of AD92 AS and grounded, the REFCOM pin, the SENSE pin, AVSS pin, the DRVSS pin, the DVSS pin, the DVDD pin, the AVDD pin, the DDVDD pin, the DD pin, the CM L pin is grounded through capacitors C201, the C L K, the analog-to-digital conversion circuit, the clock control circuit, BIT, TFT 4629.
The FPGA control circuit comprises an FPGA chip U401, an EPC 2L C20 chip U402, a serial port conversion chip U403, a capacitor C401, a resistor R409, a crystal oscillator chip X401 and R401, resistors R402, R403, R404, R408 and R409, an FPGA download port P401 and a DB9 serial port J401;
the nWS, nRS, nCS, CS, DEV _ C L Rn, DEV _ OE, INIT _ DONE, RDYnBSY, C L KUSR, DC L K, TRST, nCE, MSE 6311, MSE L, INPUT pins are grounded, DC L K pin is connected to DC L K pin of chip U402, DATA0 pin of U401 is connected to DATA pin of U402, TDI pin of U401 is connected to TDO pin of U402, TCK pin of U401 is connected to TCK pin of U402, TMS pin of U401 is connected to TMS pin of U402, TDO pin of U401 is connected to 3 pin of P401, C L K pin of U401 is connected to resistor R408, one end of capacitor C401, R408, the other end of R408 is connected to positive voltage, the other end of capacitor C401 is connected to ground, C L K pin of U401 is connected to resistor R409, the other end of R401, VCC, GND 3K pin is connected to GND 3, GND 3N pin 401, GND 3 pin is connected to GND pin 401, GND _ NODE pin of chip 401, GND _ NOT _ 3, NOT _.
The digital-to-analog conversion circuit comprises an AD9762AR, a capacitor C301, a capacitor C302, a capacitor C303 and a resistor R301;
DA _ D0, DA _ D1, DA _ D2, DA _ D3, DA _ D4, DA _ D5, DA _ D6, DA _ D7, DA _ D8, DA _ D9, DA _ D10, DA _ D11 of the FPGA control circuit are respectively connected with DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7, DB8, DB9, DB10, DB11 pins of AD9762AR, ACOM, DCOM, REF 9762AR O pin of AD9762AR is connected with ground, COMP AR of AD9762AR is connected with positive voltage through a capacitor C301, COMP AR is connected with ground through a capacitor C302, REFIO is connected with ground through a capacitor C303, ADFSJ is connected with ground through a resistor R301, DA _ C AR K is connected with C369762 OCK, DA _ S72 is connected with AD 9772 pins, DVAD _ AD 9772, AD 9772 is connected with positive voltage, and AD 9772 pins of AD 9772, and output torque of AD 97IA, AVIA and AVIA.
Compared with the prior art, the invention has the advantages that:
(1) compared with the prior art, the conversion scale is converted from double scales into 2nThe scale conversion greatly improves the pulse equivalent resolution;
(2) the circuit is realized by changing an analog switch current feedback type circuit consisting of a traditional precision voltage source and a switch into a digital-to-analog conversion circuit, is not limited by the switching frequency compared with the prior art, and improves the output maximum frequency value.
Drawings
FIG. 1 is a schematic diagram of a gyro moment current high resolution conversion circuit according to the present invention;
FIG. 2 is a schematic diagram of a moment current integration circuit in a gyro moment current high resolution conversion circuit according to the present invention;
FIG. 3 is a schematic diagram of an analog-to-digital conversion circuit in a gyro moment current high resolution conversion circuit according to the present invention;
FIG. 4 is a schematic diagram of the structure of an FPGA control circuit in the gyro moment current high-resolution conversion circuit according to the present invention;
fig. 5 is a schematic diagram of a digital-to-analog conversion circuit in the gyro moment current high resolution conversion circuit according to the present invention.
Detailed Description
The invention provides a gyro moment current high-resolution conversion circuit aiming at the defects of the prior art, a moment current integrating circuit, an analog-to-digital conversion circuit, an FPGA control circuit and a digital-to-analog conversion circuit are connected in series to form a current closed-loop feedback system, so that the conversion of gyro moment current high-output resolution and large dynamic range is realized, and the invention is further described in detail by combining the attached drawings and specific embodiments.
As shown in fig. 1, the gyro moment current high resolution conversion circuit of the present invention is schematically configured, and it can be known that the gyro moment current high resolution conversion circuit of the present invention includes a moment current integrating circuit 1, an analog-to-digital conversion circuit 2, an FPGA control circuit 3, and a digital-to-analog conversion circuit 4, wherein the moment current integrating circuit 1 inputs gyro moment current TQ —, outputs an integrated voltage to the analog-to-digital conversion circuit 2, an output of the analog-to-digital conversion circuit 2 is connected to a 14-bit data input AD _ D [13..0] and a saturation overflow signal input AD _ OTR of the FPGA control circuit 3, an output of the FPGA control circuit 3 is connected to a digital-to-analog conversion circuit 4 12, which is a data input DA _ D [11..0], a clock control signal DA _ C L K, DA control signal DA _ S L P and a clock control signal AD _ C L K of the analog-to analog conversion circuit 2, and an output of the digital-to analog-to-digital.
The structure diagram of the control circuit of the moment current integrating circuit 1 is shown in fig. 2, a gyro moment current signal TQ-is filtered by a capacitor C104, the filtered signal is shunted by a circuit composed of resistors R103 and R105, the shunted signal is connected to the reverse end of the integrated operational amplifier U101, an a-end current output signal DAC _ IA of the digital-to-analog conversion circuit 4 is shunted by a circuit composed of resistors R101 and R102, the processed signal is connected to the reverse end of the integrated operational amplifier U101, a B-end current output signal DAC _ IB of the digital-to-analog conversion circuit 4 is shunted by a circuit composed of resistors R106, R104, R107 and R108, the processed signal is connected to the forward end of the integrated operational amplifier U101, the capacitor C101 is connected to the reverse end and the output end of the integrated operational amplifier U101, and an output-end voltage signal INT _ VO of the integrated operational amplifier U101 is connected to a voltage input end AD _ VI of the analog-.
The circuit structure diagram of the analog-to-digital conversion circuit 2 is shown in fig. 3, an input voltage AD _ VI of the analog-to-digital conversion circuit 2 is limited by a circuit composed of resistors R201 and R202, the limited current is connected with a VINA pin of a chip AD9243, diodes D201 and D202 constitute a voltage clamp circuit, a cathode of D201 is connected with +5V, an anode of D202 is connected with a cathode of D202, an anode of D202 is grounded, capacitors C202, C203, C204 and C205 constitute a filter circuit, two ends of C203 are connected with a cap pin and a CAPB pin of AD9243 respectively, C203 and C205 are connected in parallel, two ends of C205 are connected with C202, C204, the other ends of C202 and C204 are grounded, a resistor R203 is connected with a VINB pin and a VREF pin of AD9243, capacitors C206 and C207 are connected with VREF pin of AD9243 in parallel, a REFCOM pin, a pin, SENSE pin, AVSS pin, a DRVSS pin and DVSS pin of AD9243 are grounded, an avom pin, a drad 9243 pin, a signal output pin, a voltage signal is connected with a voltage, a voltage.
The circuit structure of the FPGA control circuit 3 is shown in FIG. 4, the nWS, nRS, nCS, CS, DEV _ C Rn, DEV _ OE, INIT _ DONE, RDYnBSY, C KUSR, DC 0K, TRST, nCE, MSE 11, MSE 20, INPUT pins of the FPGA U401 are grounded through nSD/NOT pins of a clock-to-DATA conversion circuit 401, the TCK pin of the U401 is connected to the TCK pin of the U402, the TMS pin of the U401 is connected to the TMS pin of the U402, the TDO pin of the U401 is connected to the DATA-to-ground pin of the FPGA 4, the TDO pin of the FPGA download port P401(P401 is connected to the FPGA download port P401, the FPGA download port P401 is connected to the TMS pin 401, the FPGA download port P pin 401(P pin 401 is 2-line 5-column, 2-column 2.54-pin, the inter-pin space 2.54, the FPGA download port P pin is connected to the FPGA program download port P pin 401, the FPGA 3 pin is connected to the download port P pin, the FPGA 4, the FPGA program download port, the FPGA program is connected to the FPGA 4, the FPGA 4-to the FPGA-to the ground, the FPGA-to the ground pin, the FPGA-to the ground, the FPGA-to convert the output interface, the analog-to-D interface 12, the analog-D interface, the analog-D interface, the.
The circuit structure diagram of the digital-to-analog conversion circuit 4 is shown in fig. 5, DA _ D of the FPGA control circuit 3 are respectively connected to DB, DB pins, and the ACOM, DCOM, and REF O pins of the AD9762 are grounded, COMP of the AD9762 is connected to +5V through a capacitor C301, COMP of the AD9762 is connected to ground through a capacitor C302, REFIO of the AD9762 is connected to ground through a capacitor C303, FSADJ of the AD9762 is connected to ground through a resistor R301, DA _ C K of the FPGA control circuit 3 is connected to C OCK pin of the AD9762, DA _ S P of the FPGA control circuit 3 is connected to the S EEP pin of the AD9762, AVDD, iodd pin of the AD9762 is connected to +5V, ioa pin of the integrated torque of the AD 97a, and the DAC _ IA _ IB are respectively connected to the integrated current output of the DAC _.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (4)
1. The gyro moment current high-resolution conversion circuit is characterized by comprising a moment current integrating circuit, an analog-to-digital conversion circuit, an FPGA control circuit and a digital-to-analog conversion circuit, wherein:
the moment current integrating circuit generates an integrating voltage according to the gyro moment current and outputs the integrating voltage to the analog-digital conversion circuit, the analog-digital conversion circuit generates a first data input and a saturation overflow signal input and outputs the first data input and the saturation overflow signal input to the FPGA control circuit, the FPGA control circuit generates a second data input, a clock control signal of the digital-analog conversion circuit and a DA control signal and outputs the second data input, the clock control signal of the digital-analog conversion circuit and the DA control signal to the digital-analog conversion circuit, the digital-analog conversion circuit generates a current output and sends the current output to the moment current integrating circuit;
the FPGA control circuit comprises an FPGA chip U401, an EPC 2L C20 chip U402, a serial port conversion chip U403, a capacitor C401, a resistor R409, a crystal oscillator chip X401, resistors R401, R402, R403, R404, R408, R409, an FPGA download port P401 and a DB9 serial port J401, wherein the chip U401 comprises a U401A, a U401B and a U401C;
the nWS, nRS, nCS, CS, DEV _ C Rn, DEV _ OE, INIT _ DONE, RDYnBSY, C KUSR, TRST, nCE, MSE 01, MSE 10, INPUT pins are grounded, the DC 2K pin of chip U401 is connected with the DC 4K pin of EPC 3C configuration chip U402, the DATA pin of chip U401 is connected with the DATA pin of chip U402, the TDI pin of chip U401 is connected with the TDO pin of chip U402, the TCK pin of chip U401 is connected with the TCK pin of chip U402, the TMS pin of chip U401 is connected with the TMS pin of chip U402, the TDO pin of chip U401 is connected with the F _ TDO pin of FPGA download port P401, the C K pin of chip U401 is connected with the resistor R408, the capacitor C401, the other end of resistor R408 is connected with the GND pin of chip U401, the other end of capacitor C401 is connected with the GND 5C + GND pin of chip, the chip C pin of FPGA RQ + C pin of FPGA RQ + C pin is connected with the ground terminal of the chip, the TCK pin of the chip, the chip I + C pin of FPGA RQ + C pin of the chip, the TCK pin of the chip, the TCK pin of the chip, the chip is connected with the TCK pin of the chip 12, the TCK pin of the chip, the chip U401, the TCK pin of the chip U401, the TCK pin of the chip, the chip U401, the TCK pin of the chip, the TCK pin of the TCU 401, the TCK pin of the chip, the TCK pin of the chip, the TCK pin of the chip, the TCK pin of the TCU 401, the TCK pin of the TCU 401, the TCK pin of the TCU 401, the TCU + C.
2. The gyro moment current high resolution conversion circuit according to claim 1, characterized in that: the moment current integration circuit comprises a capacitor C101, a capacitor C104, an integrated operational amplifier U101, a resistor R102, a resistor R103, a resistor R104, a resistor R105, a resistor R106, a resistor R107 and a resistor R108;
the gyro moment current signal TQ-is filtered by a capacitor C104 and then sent to a circuit formed by resistors R103 and R105 for shunt, the shunted signal is connected to the reverse end of the integrated operational amplifier U101, an A-end current output signal DAC _ IA of the digital-to-analog conversion circuit is shunted by a circuit formed by resistors R101 and R102, the shunted signal is connected to the reverse end of the integrated operational amplifier U101, a B-end current output signal DAC _ IB of the digital-to-analog conversion circuit is shunted by a circuit formed by resistors R106, R104, R107 and R108, the shunted signal is connected to the forward end of the integrated operational amplifier U101, the capacitor C101 is connected with the reverse end and the output end of the integrated operational amplifier U101, and the output end of the integrated operational amplifier U101 generates an integral voltage and sends the integral voltage to the analog-to-digital conversion.
3. The gyro moment current high resolution conversion circuit according to claim 1 or 2, characterized in that: the analog-to-digital conversion circuit comprises resistors R201, R202 and R203, diodes D201 and D202, capacitors C202, C203, C204, C205, C206 and C207 and a chip AD9243 AS;
the integrated voltage is limited by a circuit composed of resistors R201 and R202 and then is connected with a VINA pin of a chip AD9243AS, diodes D201 and D202 form a voltage clamp circuit, the cathode of the diode D201 is connected with a positive voltage, the anode of the diode D201 is connected with the cathode of the diode D202, the anode of the diode D202 is grounded, capacitors C202, C203, C204 and C205 form a filter circuit, two ends of the capacitor C203 are respectively connected with a CAPT pin and a CAPB pin of AD9243AS, the capacitors C203 and C205 are connected in parallel, two ends of the capacitor C205 are respectively connected with capacitors C202 and C204, the other ends of the capacitors C202 and C204 are grounded, the resistor R203 is connected with a VINB pin VREF and a pin of an AD92 AS, the capacitors C206 and C207 are connected with a VREF pin of the AD92 AS and grounded, the REFCOM pin of the AD9243 and the REFCOM pin of the AD 923638 are respectively connected with the ground, the REFCOM pin, the AVSS pin, the DRSS pin, the DVSS pin is grounded, the AVDD pin, the DRDD pin, the DVDD 6348, the DVDD pin is connected with a ground through capacitors C201, the capacitor C26K 4626, the clock signal conversion circuit, the FPGA 6327.
4. The gyro moment current high resolution conversion circuit according to claim 1 or 2, characterized in that: the digital-to-analog conversion circuit comprises an AD9762AR, a capacitor C301, a capacitor C302, a capacitor C303 and a resistor R301;
DA _ D0, DA _ D1, DA _ D2, DA _ D3, DA _ D4, DA _ D5, DA _ D6, DA _ D7, DA _ D8, DA _ D9, DA _ D10, DA _ D11 of the FPGA control circuit are respectively connected with DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7, DB8, DB9, DB10, DB11 pins of AD9762AR, ACOM, DCOM, REF 9762AR O pin of AD9762AR is connected with ground, COMP AR pin of AD9762AR is connected with positive voltage through C301, COMP AR pin is connected with ground through C302, REFIO is connected with ground through C303, FSADJ is connected with ground through resistor R301, DA _ C AR K is connected with C AR of AD 9762K AR, IOP 72 is connected with positive voltage through AD 9772, EEP 72, and signal output from AVAD 97IA, AVIB, AVP 72, AD 97IA and AVDD 72.
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| CN102539831A (en) * | 2012-02-17 | 2012-07-04 | 北京航天自动控制研究所 | Signal conversion device for accelerometer in strapdown inertial navigation system |
| CN103338042A (en) * | 2013-06-24 | 2013-10-02 | 北京航天控制仪器研究所 | Analog-digital conversion circuit for dynamically tuned gyroscope |
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| CN107925415A (en) * | 2015-09-03 | 2018-04-17 | 株式会社电装 | A/d converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101919635B1 (en) * | 2014-02-24 | 2018-11-19 | 매그나칩 반도체 유한회사 | Integrating Analog- Digital Converter |
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| CN102539831A (en) * | 2012-02-17 | 2012-07-04 | 北京航天自动控制研究所 | Signal conversion device for accelerometer in strapdown inertial navigation system |
| CN103338042A (en) * | 2013-06-24 | 2013-10-02 | 北京航天控制仪器研究所 | Analog-digital conversion circuit for dynamically tuned gyroscope |
| CN104155510A (en) * | 2014-09-02 | 2014-11-19 | 湖北航天技术研究院总体设计所 | Closed loop integral type accelerometer dynamic current measuring device and method |
| CN107925415A (en) * | 2015-09-03 | 2018-04-17 | 株式会社电装 | A/d converter |
| CN106949781A (en) * | 2017-03-22 | 2017-07-14 | 贾长治 | A kind of self-propelled gun gun rotated accuracy method of testing and equipment |
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