CN107492395B - Conditional access chip, built-in self-test circuit and test method thereof - Google Patents
Conditional access chip, built-in self-test circuit and test method thereof Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
- G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/40—Response verification devices using compression techniques
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1206—Location of test circuitry on chip or wafer
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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Abstract
The invention relates to a self-test circuit built in a conditional access chip, the conditional access chip utilizes a plurality of logic units to decrypt a video data, the self-test circuit comprises: a storage unit for storing a test data and a comparison data; and a control unit, coupled to the logic units, for: controlling the logic units to receive a clock pulse to perform a test; reading the test data from the storage unit; inputting the test data into a scan chain composed of the logic units according to the clock pulse; and comparing output data of the scan chain with the comparison data to obtain a test result.
Description
Technical Field
The present invention relates to a Conditional Access (CA) chip, and more particularly, to an on-chip test circuit and a test method for a CA chip.
Background
Conditional access is often used to protect digital content by storing keys in a functional chip to decrypt the protected data. Generally, to protect a key, an active shield layer (active shield) is formed on the top metal layer of a semiconductor structure implementing a conditional access chip, and when the chip is hacked (e.g., by a Focused Ion Beam (FIB) attack), the active shield layer is likely to be damaged, so that the chip can check the state of the active shield layer to determine whether the key is secure.
However, the active shielding layer is easily known and evaded by a person with a mind because the active shielding layer is manufactured on the surface of the chip; furthermore, the attack may come from the side of the chip rather than the surface. This all too may cause the situation that the internal key has been stolen although the active shielding layer remains intact as before. Therefore, it is necessary to provide a better method for securing data of the conditional access chip.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a built-in self-test circuit and a test method for a conditional access chip, so as to improve the security of the conditional access chip.
The invention discloses a self-test circuit built in a conditional access chip, the conditional access chip utilizes a plurality of logic units to decrypt a video data, the self-test circuit comprises: a storage unit for storing a test data and a comparison data; and a control unit, coupled to the logic units, for: controlling the logic units to receive a clock pulse to perform a test; reading the test data from the storage unit; inputting the test data into a scan chain composed of the logic units according to the clock pulse; and comparing output data of the scan chain with the comparison data to obtain a test result.
The invention also discloses a self-testing method of a conditional access chip, the conditional access chip utilizes a plurality of logic units to decrypt an audio-visual data and comprises a storage unit for storing a testing data and a comparison data, the self-testing method comprises: controlling the logic units to receive a clock pulse to perform a test; reading the test data from the storage unit; inputting the test data into a scan chain composed of the logic units according to the clock pulse; and comparing output data of the scan chain with the comparison data to obtain a test result.
The conditional access chip, the built-in self-test circuit and the test method directly test the logic unit and the logic circuit in the chip, and the test data is prestored in the chip to improve the test safety, so that whether the chip is damaged or not can be known. Compared with the prior art, the invention improves the safety of the conditional access chip and is easy to implement.
The features, implementations and effects of the present invention will be described in detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a partial circuit diagram of a conditional access chip according to an embodiment of the present invention;
FIG. 2 is a flow chart of a self-test method for a conditional access chip according to the present invention;
FIG. 3 is a detailed flowchart of the scan chain test of step S250 in FIG. 2;
FIG. 4 is a schematic diagram of the connection of the logic unit of the present invention; and
FIG. 5 is a schematic diagram of another logic cell in the scan chain of the present invention.
Description of the symbols
110 scan chain
120 control unit
130 storage unit
140. 165, 420, 510 multiplexer
150 oscillating circuit
170 decompression circuit
180 compression circuit
400. 500 logic cell
410 trigger
450 logic circuit
S210 to S280
Detailed Description
The disclosure of the present invention includes a conditional access chip, a built-in self-test circuit and a test method thereof. The apparatus and method can be applied to the receiving end of a digital television or set-top box, and those skilled in the art can select equivalent elements or steps to implement the present invention according to the disclosure of the present specification, where the implementation is possible, i.e., the implementation of the present invention is not limited to the embodiments described below.
The conditional access chip can be operated in a working mode and a testing mode. In the working mode, the conditional access chip executes the general function (for example, the chip is applied to digital TV, and the general function is to decrypt the video data); in the test mode, the logic units forming each functional module inside the conditional access chip are connected in series to form a scan chain (scan chain), and test data is input into the scan chain to detect whether the chip is damaged. The test data and the corresponding test result of the invention are all pre-stored in the chip. FIG. 1 is a partial circuit diagram of a conditional access chip according to an embodiment of the present invention. In addition to the logic units forming the scan chains 110-1 to 110-N, the rest of the circuits in FIG. 1 can be regarded as built-in self-test circuits of the conditional access chip. The storage unit 130 stores the Test data and the corresponding Test result, and the control unit 120 is coupled to the storage unit 130, and configured to read the Test data Test _ in and the corresponding Test result, input the Test data Test _ in into the scan chains 110-1 to 110-N (N is a positive integer), and compare the output result Test _ out of the scan chain 110 with the corresponding Test result to determine whether the chip is damaged. In one embodiment, the control unit 120 may be, for example, a micro control unit or a microprocessor, and the functions thereof are realized by executing the processes or algorithms of fig. 2 and 3, and the storage unit 130 may be a built-in rom of the micro control unit or the microprocessor.
Fig. 2 is a flow chart of the self-testing method of the conditional access chip according to the present invention, and please refer to fig. 1 and fig. 2 for operation details of the present invention. At the beginning of the test, the system is initialized (step S210), for example, the logic units of the scan chain, the counters and registers of the control unit are reset. After the initialization is completed, the control unit 120 switches the clock according to which the chip operates from the system clock to the test clock (step S220), that is, switches the chip from the working mode to the test mode. More specifically, when the chip performs a general function in the working mode, each functional module may perform its task with a different working clock, which is generated by a phase locked loop using, for example, the system clock of the chip; in the test mode, all logic units operate at the same test clock. As shown in FIG. 1, the control unit 120 controls the multiplexer 140 to select the system clock CLK _ sys or the test clock CLK _ test as the operation clock CLK of the scan chains 110-1 to 110-N according to the control signal Ctrl. In the present embodiment, when the control signal Ctrl is switched from disabled to enabled (or vice versa), it represents that the chip enters the test mode from the working mode, and the multiplexer 140 switches the working clock CLK from the system clock CLK _ sys to the test clock CLK _ test. In one embodiment, the test clock CLK _ test is generated by an oscillation circuit 150 built inside the chip. The design has the advantage of improving the safety and reliability during testing, because if the test clock is provided from the outside of the chip, the test clock is easy to be altered, resulting in the manipulation of the test result.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating the connection of two logic units in a scan chain according to the present invention. In addition to the logic cells 400 connected in series, the scan chain further includes a logic circuit 450 located between two consecutive logic cells 400. The logic circuit 450 is a circuit for providing input signals to a logic unit 400 during normal operation of the conditional access chip. Each logic cell 400 includes a flip-flop 410 and a multiplexer 420. The flip-flop 410 operates according to the clock CLK and RESETs its stored data according to the signal RESET. The input end D has two data sources, i.e. data SI and data CA, and the multiplexer 420 determines which data is input to the flip-flop 410 according to a control signal SE generated by a control unit (not shown in fig. 1). The data SI is data directly output by the previous logic unit 400 in the scan chain, and actually, the data SI is Test data Test _ in or data generated according to the Test _ in. The data CA is the output of the logic circuit 450. The output Q of the flip-flop 410 is coupled to the next logic circuit 450 and the multiplexer 420 of the next logic unit 400. Taking the scan chain 110-1 as an example, when the control signal SE controls the multiplexers 420 of all logic units 400 to switch to receive the data SI (step S230), the data SI can be sequentially transmitted to each logic unit 400 in the scan chain 110-1. Similarly, the operation of scan chains 110-2 through 110-N is the same as scan chain 110-1.
With continued reference to FIG. 1, the output ends of the scan chains 110-1 to 110-N switch the working outputs Data _ out 1-Data _ outN to the Test outputs by controlling the multiplexers 165-1 to 165-N (step S240), so that the subsequent control unit 120 receives the integrated Test result Test _ out for comparing with the corresponding Test result. In the next step S250, the control unit 120 performs a scan chain test according to the period of the test clock. The scan chain test proposed by the present invention includes a shift stage and a capture stage of the scan chain, and further details of the test will be described later. After the test is completed, the control unit 120 changes the control signal Ctrl from an enabled state to an disabled state, so the multiplexers 165-1 to 165-N switch the outputs of the scan chains 110-1 to 110-N from the test outputs to the working outputs Data _ out1 to Data _ out (step S260), and the multiplexer 140 switches the clocks of the scan chains 110-1 to 110-N from the test clock CLK _ test back to the system clock CLK _ sys (step S280), and in addition, the control unit 120 controls the multiplexers 420 of all the logic units 400 to switch to receive the Data CA through the control signal SE (step S270), so that the test of the chip is completed, the chip can return to a normal working state, and each functional module executes the original function.
In one embodiment, to save the storage space of the storage unit 130 and reduce the number of pins between the control unit 120 and the scan chains 110-1 to 110-N, the Test data Test _ in is stored in the storage unit 130 in a compressed form, the data is decompressed by the decompression circuit 170 before being input into the scan chains 110-1 to 110-N, and all the Test outputs are compressed into the Test result Test _ out at the output terminals of the scan chains 110-1 to 110-N by the compression circuit 180. In one embodiment, decompression circuit 170 and compression circuit 180 are implemented in hardware, and decompression circuit 170 has output pins equal to the number of scan chains 110-1-110-N, but input pins less than the number of scan chains 110-1-110-N, and similarly compression circuit 180 has input pins equal to the number of scan chains 110-1-110-N, but output pins less than the number of scan chains 110-1-110-N. The decompression circuit 170 and the compression circuit 180 may be implemented using DFTMAX compression/decompression circuits, but not limited thereto.
Fig. 3 is a detailed flow of the scan chain test of step S250 in fig. 2. When the scan chain test is started, the control unit 120 first reads the test data from the storage unit 130 (step S252). The read test data may be partially or completely stored in a register (not shown) inside the control unit 120, so as to be quickly provided to the scan chains 110-1 to 110-N during the test process. Next, the data SI generated by decompression according to the Test data Test _ in is input into the scan chain (step S254). Please note that, since the test data of the present invention can also be stored in the storage unit 130 in an uncompressed form, the decompression circuit 170 and the compression circuit 180 are not required in this case, and the test data can be directly inputted into the scan chain as the data SI. Referring to step S220 of fig. 2, since the operating clock CLK is switched from the system clock CLK _ sys to the test clock CLK _ test in step S220, the data SI is transmitted to the output terminals of the scan chains 110-1 to 110-N at a speed of one test clock cycle to forward one logic unit in the scan chains 110-1 to 110-N.
As mentioned above, the testing of the scan chain can be subdivided into a shift stage and an extraction stage. The shift stage is used to fill all flip-flops 410 with data SI, and the fetch stage is used to test all logic cells and the logic circuits 450 between logic cells for correct operation. In one embodiment, the control signal SE is asserted when the control signal Ctrl is asserted, that is, the current scan chain test can be controlled to be a shift stage or a capture stage when the control signal Ctrl is asserted. The following describes the testing of the shift stage and the fetch stage by taking one scan chain 110-1 as an example. Assuming that the length of the scan chain 110-1 is 400 logic units and the length of the data SI is 400 bits, the data SI will be sequentially transmitted forward between the logic units in consecutive cycles of 400 test clocks CLK _ test until all the logic units temporarily store the data SI, so as to complete the data input in the shift stage (step S256), in short, the shift stage is used to make all the flip-flops 410 on the scan chain 110-1 temporarily store the data SI; then, the control signal SE controls all multiplexers 420 on the scan chain 110-1 to select the data CA and perform a cycle of input of the test clock CLK _ test, and all flip-flops 410 on the scan chain 110-1 obtain a new value corresponding to the respective received data CA to complete the capturing in the capturing stage (step S257). Next, the control signal SE controls all multiplexers 420 on the scan chain 110-1 to re-select the data SI, and the shift stage is entered again, so that the data SI is input into the scan chain 110-1 again in the following consecutive 400 cycles of the Test clock CLK _ Test until all logic units temporarily store the data SI, and thus all new values obtained by the flip-flops 410 in the step S257 can be sequentially pushed out of the scan chain 110-1, and the new values are the Test results Test _ out, so that the data input in the shift stage is completed again (step S258). Please note that, the second shift stage is to obtain the new values of all multiplexers 420 on the scan chain 110-1 at the output end of the scan chain, and the present invention utilizes the new values to determine whether all multiplexers 420 and the related logic circuits on the scan chain 110-1 are normal. In addition, in another embodiment, all multiplexers 420 on the scan chain 110-1 may also perform the test clock CLK _ test for more than one cycle after selecting the data CA in the fetch stage. In another embodiment, the self-test circuit of the present invention can continuously test different data SIs by repeatedly operating in the shift stage and the capture stage.
In order to save the comparison times, the control unit 120 may not check the Test result Test _ out every Test clock cycle, but first perform the operation on the Test result Test _ out and then compare the Test result with the expected Test result. There are many ways to operate, such as using Cyclic Redundancy Check (CRC), but not limited to this. The control unit 120 continuously performs the crc operation on the newly generated Test result and the existing Test result, and uses the final operation result as the Test result Test _ out and compares the Test result with the corresponding Test result.
Please refer to fig. 5. Fig. 5 is a schematic diagram of another logic cell 500 in the scan chain of the present invention. In addition to logic unit 400, logic unit 500 also includes a multiplexer 510. The multiplexer 510 has a first receiving end for receiving CA _ O, which is an output of the logic circuit corresponding to the logic unit 500 under normal use, and the multiplexer 510 also has a second receiving end for receiving CA _ P, which is a predetermined logic signal. Since many logic units in the whole conditional access chip are related to other circuits outside the chip, in order to effectively isolate other circuits outside the chip in the test stage, the logic unit 500 receives a predetermined logic signal CA _ P according to the control signal CA _ SE during the self-test, so that the CA _ P can be provided as the data CA in the access stage, thereby avoiding the interference from the outside of the chip. When the test is finished, the logic unit receives the CA _ O according to the control of the control signal CA _ SE, and the normal operation is recovered.
In summary, the logic units in the chip are combined into the scan chain, and the scan chain is directly tested. If the key in the chip is tampered or stolen, the chip is damaged according to the test result, and then the chip can stop working normally. The test data used in the test process of the invention is stored in the chip in advance, but not input from the outside, thus ensuring the test safety. In addition, the oscillation circuit 150 additionally provided in the chip is used as a source of the test clock, so that the sealing performance of the test system can be improved, and the test process can be prevented from being interfered. In addition, the test process of the invention can compare the test result with the preset data after the test result is operated without checking the test result in each test clock cycle, which is beneficial to reducing the comparison times and improving the test efficiency. The decompression circuit 170 and the compression circuit 180 located between the scan chain and the control unit 120 help to reduce the storage space of the storage unit 130 and the pin count of the control unit 120.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can apply variations to the technical features of the present invention according to the explicit or implicit contents of the present invention, which may fall within the scope of the patent protection sought by the present invention, in other words, the scope of the patent protection sought by the present invention is defined by the claims.
Claims (14)
1. A self-test circuit built in a conditional access chip, the conditional access chip decrypting an audio-visual data using a plurality of logic units, the self-test circuit comprising:
a storage unit for storing a test data and a comparison data; and
a control unit, coupled to the logic units, for:
controlling the logic units to receive a clock pulse to perform a test, wherein the test comprises a shifting stage and a capturing stage;
reading the test data from the storage unit;
inputting the test data into a scan chain composed of the logic units according to the clock pulse; and
comparing an output data of the scan chain with the comparison data to obtain a test result, wherein one of the logic units comprises:
a flip-flop, comprising:
a first input terminal;
a second input terminal for receiving the clock; and
a first output end coupled to a subsequent logic unit of the logic unit;
a first multiplexer, comprising:
a third input end for receiving the test data output by the previous logic unit of the logic unit;
a fourth input terminal for receiving a normal data; and
a second output terminal for outputting the test data to the first input terminal in the shift stage and outputting the normal data to the first input terminal in the capture stage; and
a second multiplexer, comprising:
a fifth input for receiving a security data;
a sixth input for receiving an unsecured data; and
a third output end for outputting the safety data as the normal data in the capturing stage and outputting the non-safety data as the normal data at the end of the test.
2. The self-test circuit of claim 1, wherein the clock is a first clock, and when the test is completed, the control unit controls the logic units to receive a second clock, the second clock being different from the first clock.
3. The self-test circuit of claim 1, further comprising:
an oscillation circuit coupled to the control unit and the logic units for generating the clock.
4. The self-test circuit of claim 1, wherein the scan chain outputs a plurality of test results corresponding to successive cycles of the clock, and the output data is an operation result of the test results.
5. The self-test circuit of claim 1, wherein the normal data is provided by a logic circuit.
6. The self-test circuit of claim 1, wherein the logic cells form a plurality of scan chains, the self-test circuit further comprising:
the decompression circuit is provided with at least one decompression circuit input end and a plurality of decompression circuit output ends, the at least one decompression circuit input end is coupled with the control unit, the decompression circuit output ends are coupled with the scan chains, and the number of the decompression circuit input ends is less than that of the decompression circuit output ends.
7. The self-test circuit of claim 1, wherein the logic cells form a plurality of scan chains, the self-test circuit further comprising:
the compression circuit is used for compressing the output data of the scan chains and is provided with at least one compression circuit output end and a plurality of compression circuit input ends, the at least one compression circuit output end is coupled with the control unit, the compression circuit input ends are coupled with the scan chains, and the number of the compression circuit output ends is less than that of the compression circuit input ends.
8. A self-test method for conditional access chip, the conditional access chip utilizes multiple logic units to decrypt a video data, and includes a storage unit for storing a test data and a comparison data, the self-test method includes:
controlling the logic units to receive a clock pulse to perform a test, wherein the test comprises a shifting stage and a capturing stage;
reading the test data from the storage unit;
inputting the test data into a scan chain composed of the logic units according to the clock pulse; and
comparing an output data of the scan chain with the comparison data to obtain a test result, wherein one of the logic units comprises:
a flip-flop, comprising:
a first input terminal;
a second input terminal for receiving the clock; and
a first output end coupled to a subsequent logic unit of the logic unit;
a first multiplexer, comprising:
a third input terminal for receiving the test data outputted from the previous logic unit of the logic unit;
a fourth input terminal for receiving a normal data; and
a second output terminal for outputting the test data to the first input terminal in the shift stage and outputting the normal data to the first input terminal in the capture stage; and a second multiplexer, comprising:
a fifth input for receiving a security data;
a sixth input for receiving an unsecured data; and
a third output end for outputting the safety data as the normal data in the capturing stage and outputting the non-safety data as the normal data at the end of the test.
9. The self-test method of claim 8, wherein the clock is a first clock, the self-test method further comprising:
when the test is finished, controlling the logic units to receive a second clock pulse;
wherein the second clock is not equal to the first clock.
10. The self-test method of claim 8, wherein the conditional access chip further comprises an oscillation circuit for generating the clock, and the test is performed with reference to only the clock and not to an external clock of the conditional access chip.
11. The self-testing method of claim 8, further comprising:
the scan chain outputs a plurality of test results corresponding to the continuous periods of the clock;
wherein, the output data is an operation result of the test results.
12. The self-test method as claimed in claim 8, wherein the normal data is provided by a logic circuit.
13. The self-test method of claim 8, wherein the logic units form a plurality of scan chains, the test data is a compressed data, the self-test method further comprising:
the test data is decompressed before being input into the scan chains.
14. The self-test method of claim 8, wherein the logic units form a plurality of scan chains, the test data is a compressed data, the self-test method further comprising:
before comparing the output data with a preset data, the output data of the scan chains are compressed.
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| CN110031752B (en) * | 2018-01-11 | 2021-05-25 | 瑞昱半导体股份有限公司 | Self-test circuit and self-test method applied to comparator |
| CN111025132B (en) * | 2018-10-09 | 2022-02-15 | 瑞昱半导体股份有限公司 | System chip, built-in self-test circuit and self-test method thereof |
| CN112731121A (en) * | 2019-10-14 | 2021-04-30 | 瑞昱半导体股份有限公司 | Chip and testing method thereof |
| WO2023283774A1 (en) * | 2021-07-12 | 2023-01-19 | 华为技术有限公司 | Scan chain design method and apparatus, and chip |
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