CN107483868B - VBO signal processing method, FPGA and laser television - Google Patents
VBO signal processing method, FPGA and laser television Download PDFInfo
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Abstract
The embodiment of the invention provides a VBO signal processing method, an FPGA and a laser television, wherein the method comprises the following steps: converting each VBO signal into a parallel signal respectively, and recovering a clock signal from each parallel signal; respectively caching a plurality of paths of parallel signals; performing a read operation on all the parallel signals buffered based on a target clock signal; the target clock signal is one of the multiple clock signals recovered from the multiple parallel signals. The method and the FPGA provided by the embodiment of the invention can improve the accuracy of VBO signal transmission between the SOC and the FPGA and improve the stability of a hardware system in the laser television.
Description
Technical Field
The embodiment of the invention relates to the technical field of laser televisions, in particular to a VBO signal processing method, an FPGA and a laser television.
Background
With the development of display technology, 4K televisions, i.e., ultra high definition televisions, have become very popular. There are many kinds of 4K televisions, and among them, a 4K laser television is a more popular type of 4K television.
The existing 4K laser television is mainly implemented by a hardware System of "System on Chip (SOC, abbreviated as SOC) + Field Programmable Gate Array (Field Programmable Gate Array, abbreviated as FPGA) + laser source". The SOC and the FPGA are connected by adopting a digital interface standard (V-by-One, VBO for short) signal developed specially for image transmission, One path of VBO signal in the FPGA is converted into multiple paths of parallel signals, each path of parallel signal is transmitted independently, and due to the fact that transmission delay exists among the parallel signals, the VBO signal finally obtained by the FPGA side is inaccurate, so that the stability of a system is poor, and the display problems such as screen splash, screen blackout and the like are prone to occurring.
Disclosure of Invention
The embodiment of the invention provides a VBO signal processing method, an FPGA and a laser television, which are used for improving the accuracy of VBO signal transmission and improving the stability of a hardware system in the laser television.
A first aspect of an embodiment of the present invention provides a method for processing a VBO signal, where the method includes:
converting each VBO signal into a parallel signal respectively, and recovering a clock signal from each parallel signal;
respectively caching a plurality of paths of parallel signals;
performing a read operation on all the parallel signals buffered based on a target clock signal; the target clock signal is one of the multiple clock signals recovered from the multiple parallel signals.
Optionally, the deviation between the target clock signal and the other clock signals recovered from the multiple parallel signals is minimum.
Optionally, the performing, based on the target clock signal, a read operation on all the cached parallel signals specifically includes:
performing bit width conversion processing on all the cached parallel signals;
and reading all parallel signals subjected to bit width conversion processing based on the target clock signal.
A second aspect of the embodiments of the present invention provides an FPGA, including:
a memory for storing a computer program;
and a processor for executing the computer program to perform the method of the first aspect.
A third aspect of the embodiments of the present invention provides an FPGA for processing a VBO signal, where the FPGA includes a GTP module, a cache module, and a control parsing module;
the GTP module is used for converting each path of VBO signal into a parallel signal respectively and recovering a path of clock signal from each path of parallel signal;
the buffer module is used for buffering parallel signals;
the control analysis module is used for reading all the cached parallel signals based on a target clock signal;
the target clock signal is one of the multiple clock signals recovered from the multiple parallel signals.
Optionally, the control parsing module is further configured to parse all the read parallel signals into video signals.
Optionally, the FPGA further includes a bit width conversion module, configured to perform bit width conversion processing on the parallel signals in the cache module;
the function of the control analysis module is replaced by: and the method is used for reading all parallel signals subjected to bit width conversion processing based on the target clock signal.
In a fourth aspect, the embodiment of the present invention provides a laser television, which includes the FPGA described in the above aspects.
Based on the above aspects, the embodiments of the present invention have the following beneficial effects:
according to the embodiment of the invention, each path of VBO signal is respectively converted into the parallel signal, one path of clock signal is recovered from each path of parallel signal, and the multiple paths of parallel signals are respectively cached, so that reading operation is performed on all cached parallel signals based on one path of clock signal in the multiple paths of clock signals recovered from the multiple paths of parallel signals. In the embodiment of the invention, all the cached parallel signals are read based on one path of clock signal in the recovered multiple paths of clock signals in the multiple paths of parallel signals, so that the difference of transmission time among the multiple paths of parallel signals can be solved, the accuracy of VBO signal transmission is improved, and the stability of the whole television hardware system is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flowchart illustrating a method for processing a VBO signal according to an embodiment of the present invention;
fig. 2 is a diagram illustrating a hardware system structure of a laser television according to an embodiment of the present invention;
fig. 3 is a diagram illustrating a hardware system structure of a laser television according to another embodiment of the present invention;
fig. 4 is a diagram illustrating a hardware system structure of a laser television according to another embodiment of the present invention;
fig. 5 is a schematic structural diagram of an FPGA according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "comprises" and "comprising," and any variations thereof, in the description and claims of this invention, are intended to cover non-exclusive inclusions, e.g., a process or an apparatus that comprises a list of steps is not necessarily limited to those structures or steps expressly listed but may include other steps or structures not expressly listed or inherent to such process or apparatus.
The embodiment of the invention provides a VBO signal processing method which can be executed by an FPGA (field programmable gate array), wherein the FPGA is arranged in a laser television and is connected with a system-level chip SOC (system on chip) in a laser television hardware system through a VBO signal.
Fig. 1 is a flowchart illustrating a VBO signal processing method according to an embodiment of the present invention. As shown in fig. 1, the method provided by this embodiment includes the following steps:
In this embodiment, the FPGA located in the laser television hardware system may include one or more GTP s. Each GTP can convert one VBO signal input by the SOC into multiple parallel signals, for example, 4 parallel signals. After converting the VBO signal into multiple parallel signals, GTP can also recover the corresponding clock signal from each parallel signal.
Taking a 4K laser television (i.e., an ultra high definition laser television) as an example, the FPGA includes two GTPs in a hardware system of the 4K laser television, and each GTP converts one VBO signal into 4 parallel signals of 20 bits. After the VBO signals are converted into the multiple paths of parallel signals, one path of clock signals are recovered from each path of parallel signals, and 8 paths of clock signals are recovered by two GTP signals. Of course, this is only an example and not a unique limitation to the present invention, and actually, the case where the FPGA includes one GTP or more than three GTP is similar to the case where the FPGA includes two GTP, and is not described again here.
And step 102, respectively caching the multipath parallel signals.
In this embodiment, each path of parallel signal output by each GTP needs to be buffered. In a possible scheme, one path of parallel signals corresponds to one cache module, and after the GTP converts the VBO into multiple paths of parallel signals, each path of parallel signals is written into the corresponding cache module for caching, that is, the number of the cache modules is the same as the number of the parallel signals. In another possible scheme, one path of parallel signals corresponds to a plurality of buffer modules, and the number of the buffer modules is greater than the number of the parallel signals.
Taking a GTP as an example, suppose that one GTP converts one VBO signal into 4 parallel signals, each parallel signal corresponds to one cache module, that is, one GTP corresponds to four cache modules, and so on, two GTP correspond to eight cache modules, and n GTP corresponds to 4n cache modules. It is understood that this is by way of illustration and not by way of limitation.
103, reading all the cached parallel signals based on the target clock signal; the target clock signal is one of the multiple clock signals recovered from the multiple parallel signals.
Optionally, the target clock signal in this embodiment may be one path of clock signal randomly selected from multiple paths of clock signals recovered from multiple paths of parallel signals, or one path of clock signal with the smallest deviation from other paths of clock signals in the clock signals recovered from multiple paths of parallel signals. The latter method is preferably adopted in this embodiment to obtain the target clock signal.
For example, if the FPGA includes one GTP, and the GTP outputs 4 parallel signals, one of the clock signals recovered from the 4 parallel signals with the smallest deviation from the other three clock signals is selected as the target clock information number. If the FPGA includes a plurality of GTPs, two possible ways are included:
in a possible manner, a target clock signal is selected for each GTP, and the method for recovering the target clock signal from the multiple parallel signals output by each GTP is the same as the case where the FPGA includes one GTP and is not described here again.
In another possible mode, one path of clock signals with the smallest deviation with other paths is selected from the clock signals recovered from all parallel signals output by all GTP conversions to be used as target clock signals of all GTP. For example, in a scenario where two GTP transforms and outputs 8 parallel signals, if the deviation between the clock signal recovered from the first parallel signal and the clock signal recovered from the other 7 parallel signals is minimum, the clock signal with the minimum deviation is determined to be the target clock signal.
Further, for the case that one GTP is included in the FPGA, after the target clock signal is determined, a read operation is performed on all the parallel signals buffered in the buffer module based on the target clock signal, that is, a read operation is performed on each path of parallel signals output by GTP conversion based on the same clock signal. Assuming that one GTP conversion outputs 4 parallel signals, the buffered parallel signals will be read from the corresponding 4 buffer modules based on the target clock signal.
In this embodiment, the read operation is performed on all the parallel signals cached based on the recovered target clock signal, so that the deviation of each path of parallel signals output by a single GTP in transmission time can be effectively corrected, and the accuracy of signal transmission is enhanced.
And if a target clock signal is recovered for each GTP in the process, respectively executing reading operation on the parallel signals output by each GTP conversion according to the target clock signal corresponding to each GTP. It should be noted here that the target clock signals may be different for different GTP. Optionally, if only one target clock signal is recovered for all GTPs in the foregoing process, a read operation is performed on parallel signals output by all GTP conversions according to the target clock signal, and signal synchronization between different GTPs can be ensured after the read operation is performed.
Optionally, in this embodiment, in order to make the bit width of the parallel signal conform to the processing requirement of the FPGA, the method may further include the following steps:
performing bit width conversion processing on all the cached parallel signals;
and reading all parallel signals subjected to bit width conversion processing based on the target clock signal.
In this embodiment, the VBO signal is converted into a 20-bit parallel signal, after the parallel signal is buffered, the bit width of the parallel signal is converted from 20 bits to 10 bits, and finally, the 10-bit parallel signal is read based on the target clock signal.
In this embodiment, each VBO signal is converted into a parallel signal, and a clock signal is recovered from each parallel signal, so that multiple parallel signals are buffered, and thus, a read operation is performed on all buffered parallel signals based on one clock signal of the multiple clock signals recovered from the multiple parallel signals. In the embodiment, all the cached parallel signals are read based on one of the recovered multiple clock signals in the multiple parallel signals, so that the problem of inaccurate VBO signal transmission between the SOC and the FPGA due to difference in transmission time between the multiple parallel signals can be solved, and the stability of the whole television hardware system is improved.
Fig. 2 is a structural diagram of a hardware system of a laser television according to an embodiment of the present invention, as shown in fig. 2, the hardware system includes an SOC and an FPGA, where the FPGA includes a GTP1, a cache module, and a control parsing module Ctl 1. When the hardware system works, the SOC outputs the VBO signals to the GTP1, after the GTP1 receives the VBO signals, the VBO signals received by the GTP1 are subjected to serial-parallel conversion processing, 4 paths of parallel signals are output to corresponding cache modules to be cached, one path of clock signal is recovered from the 4 paths of parallel signals output by the GTP1 respectively, and then one path of clock signal is determined from the recovered 4 paths of clock signals to serve as a target clock signal. Preferably, the clock signal with the smallest deviation from the other clock signals is used as the target clock signal. Further, the control parsing module Ctl1 reads all buffered parallel signals from all buffer modules corresponding to the GTP1 according to the target clock signal. Still further, the control parsing module Ctl1 is also used to parse all the read parallel signals into video signals.
The specific implementation manner and beneficial effects of this embodiment are similar to those of the embodiment in fig. 1, and are not described herein again.
Fig. 3 is a structural diagram of a hardware system of a laser television according to another embodiment of the present invention, as shown in fig. 3, based on the embodiment of fig. 2, in the hardware system, the FPGA further includes a GTP2, a cache module corresponding to the GTP2, and a control parsing module Ctl 2.
When the hardware system works, the SOC outputs 2 channels of VBO signals to GTP1 and GTP2, respectively, after receiving the VBO signals, GTP1 and GTP2 perform serial-to-parallel conversion on the received VBO signals, and output 4 channels of parallel signals to corresponding buffer modules for buffering, respectively recover one clock signal from each channel of parallel signals output from GTP1 and GTP2, and then determine one channel of clock signal as a target clock signal from the recovered multiple channels of clock signals, where the method for determining the target clock signal is similar to that in the embodiment of fig. 2 and is not repeated here.
Further, the control parsing module Ctl1 reads the cached parallel signals from all the cache modules corresponding to the GTP1 according to the target clock signal; and the control parsing module Ctl2 reads the buffered parallel signals from all the buffer modules corresponding to the GTP2 according to the same target clock signal. Still further, the control parsing module Ctl1 and the control parsing module Ctl2 parse the parallel signals read by the modules into video signals, respectively.
It should be understood by those skilled in the art that the present embodiment is only illustrated by the case that the FPGA includes two GTP s, and when the FPGA includes more than two GTP s, the execution method is similar to the case that the FPGA includes two GTP s, and details are not described here.
The specific implementation manner and beneficial effects of this embodiment are similar to those of the embodiment in fig. 1, and are not described herein again.
Fig. 4 is a hardware system structure diagram of a laser television according to still another embodiment of the present invention, and as shown in fig. 4, on the basis of the embodiment of fig. 3, the FPGA further includes a bit width conversion module, configured to perform bit width conversion processing on the parallel signal in the buffer module.
Specifically, when the hardware system works, the SOC outputs 2 channels of VBO signals to GTP1 and GTP2, respectively, after receiving the VBO signals, GTP1 and GTP2 perform serial-to-parallel conversion on the received VBO signals, and output 4 channels of parallel signals to corresponding buffer modules for buffering, and recover one clock signal from each channel of parallel signals output by GTP1, determine one channel of clock signal from the recovered multiple channels of clock signals as a first target clock signal, recover one clock signal from each channel of parallel signals output by GTP2, and determine one channel of clock signal from the recovered 4 channels of clock signals as a second target clock signal, where the determination method of the first target clock signal and the second target clock signal is similar to that in the embodiment of fig. 2 and is not described here again.
Further, the control parsing module Ctl1 reads the cached parallel signals from all the cache modules corresponding to the GTP1 according to the first target clock signal; and the control parsing module Ctl2 reads the buffered parallel signals from all the buffer modules corresponding to the GTP2 according to the second target clock signal. Further, the buffered parallel signals are respectively input to the bit width conversion module, so that the bit width conversion module performs bit width conversion processing on the buffered parallel signals, so that the bit width of the parallel signals conforms to the processing requirements of the control analysis module Ctl1 and the control analysis module Ctl 2.
Optionally, in this embodiment, the FPGA may further include a monitoring module, a matching module, and a resetting module (not shown in fig. 4).
The monitoring module is respectively electrically connected with the SOC and the control analysis module and is used for acquiring a first data parameter of an output signal of the SOC and monitoring a second data parameter analyzed by the control analysis module after receiving the output signal.
The matching module is used for matching the first data parameter with the second data parameter.
And the resetting module is used for resetting the GTP when the first data parameter is not matched with the second data parameter.
In this embodiment, each VBO signal is converted into a parallel signal, and a clock signal is recovered from each parallel signal, so that multiple parallel signals are buffered, and thus, a read operation is performed on all buffered parallel signals based on one clock signal of the multiple clock signals recovered from the multiple parallel signals. In the embodiment, all the cached parallel signals are read based on one of the recovered multiple clock signals in the multiple parallel signals, so that the problem of inaccurate VBO signal transmission between the SOC and the FPGA due to difference in transmission time between the multiple parallel signals can be solved, and the stability of the whole television hardware system is improved.
Fig. 5 is a schematic structural diagram of an FPGA according to an embodiment of the present invention, and as shown in fig. 3, the FPGA includes:
a memory for storing a computer program;
and a processor for executing the computer program to perform the methods of the above embodiments.
The FPGA provided in this embodiment can be used to implement the technical solutions of the above embodiments, and the implementation manner and the beneficial effects thereof are similar and will not be described herein again.
The embodiment of the invention also provides a laser television. The laser television comprises the FPGA provided by any embodiment.
Embodiments of the present invention further provide a non-transitory computer-readable storage medium, where instructions in the storage medium are executed by a processor of an FPGA, so that the processor of the FPGA can execute the following method:
converting each VBO signal into a parallel signal respectively, and recovering a clock signal from each parallel signal;
respectively caching a plurality of paths of parallel signals;
performing a read operation on all the parallel signals buffered based on a target clock signal; the target clock signal is one of the multiple clock signals recovered from the multiple parallel signals.
In this embodiment, each VBO signal is converted into a parallel signal, and a clock signal is recovered from each parallel signal, so that multiple parallel signals are buffered, and thus, a read operation is performed on all buffered parallel signals based on one clock signal of the multiple clock signals recovered from the multiple parallel signals. In the embodiment, all the cached parallel signals are read based on one of the recovered multiple clock signals in the multiple parallel signals, so that the problem of inaccurate VBO signal transmission between the SOC and the FPGA due to difference in transmission time between the multiple parallel signals can be solved, and the stability of the whole television hardware system is improved.
Finally, it should be noted that, as one of ordinary skill in the art will appreciate, all or part of the processes of the methods of the embodiments described above may be implemented by hardware related to instructions of a computer program, where the computer program may be stored in a computer-readable storage medium, and when executed, the computer program may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like.
Each functional unit in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer readable storage medium. The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (7)
1. A method for processing VBO signals, comprising:
converting each VBO signal into a parallel signal respectively, and recovering a clock signal from each parallel signal;
respectively caching a plurality of paths of parallel signals;
performing a read operation on all the parallel signals buffered based on a target clock signal; the target clock signal is one of multiple clock signals recovered from multiple parallel signals;
and the deviation of the target clock signal and other clock signals recovered from the multiple parallel signals is minimum.
2. The method of claim 1, wherein performing a read operation on all parallel signals buffered based on the target clock signal comprises:
performing bit width conversion processing on all the cached parallel signals;
and reading all parallel signals subjected to bit width conversion processing based on the target clock signal.
3. An FPGA, comprising:
a memory for storing a computer program;
and a processor for executing the computer program to perform the method of claim 1 or 2.
4. An FPGA for processing a VBO signal is characterized by comprising a GTP module, a cache module and a control analysis module;
the GTP module is used for converting each path of VBO signal into a parallel signal respectively and recovering a path of clock signal from each path of parallel signal;
the buffer module is used for buffering parallel signals;
the control analysis module is used for reading all the cached parallel signals based on a target clock signal;
the target clock signal is one of multiple clock signals recovered from multiple parallel signals;
and the deviation of the target clock signal and other clock signals recovered from the multiple parallel signals is minimum.
5. The FPGA of claim 4, wherein the control parsing module is further configured to parse all the read parallel signals into video signals.
6. The FPGA of claim 4, further comprising a bit width conversion module for performing bit width conversion processing on the parallel signals in the buffer module;
the function of the control analysis module is replaced by: and the method is used for reading all parallel signals subjected to bit width conversion processing based on the target clock signal.
7. A laser television comprising an FPGA according to any one of claims 4 to 6.
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| CN109639380B (en) * | 2018-11-29 | 2020-11-06 | 海信视像科技股份有限公司 | MIPI signal processing method, device, equipment and storage medium |
| CN111107410B (en) * | 2019-12-30 | 2021-05-07 | Tcl华星光电技术有限公司 | VBO signal processing method and device for saving hardware resources and terminal |
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