CN107482015B - A kind of preparation method and its structure of three-dimensional storage - Google Patents
A kind of preparation method and its structure of three-dimensional storage Download PDFInfo
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- CN107482015B CN107482015B CN201710724649.1A CN201710724649A CN107482015B CN 107482015 B CN107482015 B CN 107482015B CN 201710724649 A CN201710724649 A CN 201710724649A CN 107482015 B CN107482015 B CN 107482015B
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- peripheral circuit
- memory block
- preparation
- array memory
- dimensional storage
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The preparation method and its structure of a kind of three-dimensional storage provided by the invention, by before the contact hole technique of peripheral circuit region is advanceed to array memory storage location channel technique, realize release of the etching of contact hole to peripheral circuit region silica membrane stress, improve the distribution of wafer macro-stress, and effectively reduce bending, before being placed in array memory storage location channel technique additionally, due to peripheral circuit region contact hole, array memory block metal gate process not will cause the contact failure of peripheral circuit with the local stress inhomogeneities of array memory block channel technique.
Description
Technical field
The present invention relates to the preparation method of semiconductor devices and its manufacturing field more particularly to a kind of three-dimensional storage and its
Structure.
Background technique
Continuous improvement with the market demand to memory capacity, traditional memory based on plane or two-dimensional structure exist
Available number of memory cells is already close to the limit in unit area, can not further satisfaction market to larger capacity memory
Demand.Just as the several one-storey houses established in one piece of limited plane, these one-storey house proper alignments, but with demand
Be continuously increased, the continuous blowout of the quantity of one-storey house, can the plane of this final block limited area can only accommodate a certain number of one-storey houses
And it can not continue growing.The memory of planar structure has been approached its practical extended limit, brings sternly to semiconductor memory industry
High challenge.
In order to solve the above difficulties, industry proposes the concept of three-dimensional storage (3D NAND), is a kind of emerging sudden strain of a muscle
Type is deposited, 2D or the limitation of plane nand flash memory bring are solved by the way that memory grain is stacked.Different from that will deposit
Storage chip is placed on single side, new 3D NAND technology, and vertical stacking multi-layer data storage unit has brilliant precision.Base
In the technology, the storage equipment that memory capacity is up to several times than similar NAND technology can be created.The technology can be supported smaller
Space content receive more high storage capacity, and then very big cost savings, energy consumption is brought to reduce, and significantly performance boost with
Meet numerous consumer mobile devices comprehensively and requires the demand of most harsh enterprise's deployment.Enable particle using new technology
Enough carry out three-dimensional stacking, thus solve due to wafer physics limit and can not further expansion single-chip active volume
Limitation, in the case where same volume size, is greatly improved the content volume of memory particle single-chip, further pushes
Storage particle population size rises violently.
Three-dimensional memory structure generally includes: (1) array memory block, i.e. memory cell array, and array memory block is used as and deposits
Region where storage lotus forms the structure of vertical stack, and the direction of the metal-oxide-semiconductor conducting channel of array memory block is generally along vertical
To distribution, therefore it is different from the structure that storage unit in conventional two-dimensional memory is horizontal distribution；(2) peripheral circuit region, in order to
So that functionalization is realized in array memory block, the booster action of peripheral circuit is needed, peripheral circuit region can not only store for array
Area's power supply, is also equipped with the effect of logical operation and electrostatic protection.In three-dimensional memory structure, peripheral circuit region is usually to adopt
It is prepared with traditional two-dimentional preparation process, in addition, peripheral circuit region is entirely storing in order to enable memory to work normally
Shared area is even up to more than half in device structure.Different, the 3D NAND according to the particle number of plies stacked in vertical direction
Grain can be divided into 32 layers, 48 layers even different product of 64 layers of particle again.Although 3D NAND technology can under equal volume,
More memory spaces are provided, but this Stack Technology has comparable operation difficulty, is also faced with many technical problems at present
Have to be solved.
As shown in Figure 1, the preparation process flow of existing three-dimensional storage be first do two-dimensional peripheral circuit region 11 and
The silicon nitride layer 13 of array memory block 12 and the stacking of silicon oxide layer 14；Then cubical array memory block 12 is prepared again, specifically,
As shown in Figures 2 and 3, the channel region 15 and metal gate 16 of array memory block 12 are respectively formed；As shown in figure 4, followed by
Graphically, etching and tungsten plug (W plug) form contact hole (CT) 17, then realize multilayer gold by duplicate dual damascene technology
Belong to interconnection.It is required outer when the stacked memory cell number of plies increases based on the preparation process flow of existing three-dimensional storage
The thickness of dielectric layers for enclosing circuit will thicken, and in subsequent manufacturing process, heat treatment is brilliant so that the stress of wafer becomes uncontrollable
Circle become bended under the stress of thicker silica, when wafer bow to a certain extent when, not only bring light shield set
The problem of carving precision, or even influence whether the ability of manipulator crawl wafer；Three-dimensional memory chip is divided into array memory block
12 with peripheral circuit region 11, due to the inhomogeneities of local stress in the preparation process of array memory block 12, so that peripheral circuit
Area 11 squeezes, and in this way when forming contact hole 17, contact hole 17 can not be grown in device fully according to design idea and connect
It touches within the scope of window, contact is caused to fail.
Summary of the invention
The object of the invention is in order to solve problem above, by the way that the contact hole technique of peripheral circuit region is advanceed to battle array
Before column memory storage location channel technique, realize that the etching of contact hole releases peripheral circuit region silica membrane stress
It puts, improves the distribution of wafer macro-stress, and effectively reduce bending, be placed in array memory block additionally, due to peripheral circuit region contact hole
Before memory cell channels technique, the local stress of array memory block metal gate process and array memory block channel technique is uneven
Property not will cause peripheral circuit contact failure.The purpose of the present invention is what is be achieved through the following technical solutions.
A kind of preparation method of three-dimensional storage, which comprises the steps of:
One substrate is provided, forms the peripheral circuit region and array memory block of three-dimensional storage on the substrate；
Form the flat insulating layer in surface on the substrate to cover above-mentioned peripheral circuit region and array memory block；
Insulating layer on the peripheral circuit region is patterned, etching and metal filling are to form and the periphery
Multiple first contact holes of circuit region electrical connection；
The channel region of storage unit is formed in the array memory block；
The metal gate of storage unit is formed in the array memory block；
Insulating layer on the array memory block is patterned, etching and metal filling are to form and the array
Multiple second contact holes of each metal gate electrical connection of memory block.
Preferably, forming the array memory block includes being alternatively formed silicon nitride layer and silicon oxide layer on the substrate
Multilayer lamination structure；Stepped region is formed so that each silicon nitride in at least side of the multilayer lamination structure using photoetching process
A part of upper surface of layer is exposed to stepped region.
Preferably, the insulating layer on the peripheral circuit region is patterned, and etching and metal filling are with shape
It further include that chemical machinery is carried out to the substrate surface after multiple first contact holes being electrically connected with the peripheral circuit region
The step of exposure mask.
It preferably, further include in the substrate after described the step of carrying out chemical machinery exposure mask to the substrate surface
The step of upper deposition silica cap layers, is not destroyed with protecting the metal in first contact hole to fill by subsequent technique.
Preferably, the thickness of the silica cap layers is greater than 3000 angstroms.
Preferably, described after the metal gate that the array memory block forms storage unit, it further include in the dioxy
The step of depositing silica-filled layer in SiClx cap layers.
Preferably, it is tungsten that the metal, which fills used metal material,.
Preferably, the material of the metal gate is tungsten.
Preferably, first contact hole at the top and peripheral circuit region of the second contact hole of the array memory block
Top is not in a horizontal plane.
Preferably, the top of the second contact hole of the array memory block is higher than the first contact hole of the peripheral circuit region
Top.
The present invention also provides a kind of three-dimensional memory structures, which is characterized in that the three-dimensional memory structure is by as above
State what method described in any one was prepared.
The present invention has the advantages that the etching that contact hole may be implemented releases peripheral circuit region silica membrane stress
It puts, improves the distribution of wafer macro-stress, and effectively reduce wafer bow；Since peripheral circuit region contact hole is placed in array memory block
Before memory cell channels technique, the local stress of array memory block metal gate process and array memory block memory block channel technique
Inhomogeneities not will cause the contact failure of peripheral circuit.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1-4 shows the process structure schematic diagram of three-dimensional storage in background technique according to the present invention.
Fig. 5-10 shows the process structure schematic diagram of three-dimensional storage according to an embodiment of the present invention.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened is fully disclosed to those skilled in the art.
Embodiment one
With reference to shown in Fig. 5-10, the embodiment of the present invention one proposes that a kind of preparation method of three-dimensional storage, feature exist
In, comprising the following steps:
As shown in figure 5, providing a substrate 20, peripheral circuit region 21 and the battle array of three-dimensional storage are formed on the substrate 20
Arrange memory block 22；Preferably, forming the array memory block 22 includes that 23 He of silicon nitride layer is alternatively formed on the substrate 20
The multilayer lamination structure of silicon oxide layer 24；Stepped region 25 is formed in at least side of the multilayer lamination structure using photoetching process
So that a part of upper surface of each silicon nitride layer 23 is exposed to stepped region 25.
The flat insulating layer 26 in surface is formed on the substrate 20 to cover above-mentioned peripheral circuit region 21 and array storage
Area 22；
As shown in fig. 6, be patterned to the insulating layer 26 on the peripheral circuit region 21, etching and metal filling with
Multiple first contact holes 27 being electrically connected with the peripheral circuit region 21 are formed, the metal fills used metal material and is
Tungsten；
As shown in figure 8, forming the channel region 28 of storage unit in the array memory block 22；
As shown in figure 9, forming the metal gate 29 of storage unit, the material of the metal gate 29 in the array memory block 22
For tungsten；
As shown in Figure 10, the insulating layer 26 on the array memory block 22 is patterned, etching and metal filling
To form multiple second contact holes 30 being electrically connected with each metal gate 29 of the array memory block 22, the metal filling
Used metal material is tungsten.
Embodiment two
The embodiment of the present invention two proposes a kind of preparation method of three-dimensional storage, which comprises the following steps:
As shown in Figure 6, it is preferable that the insulating layer 26 on the peripheral circuit region 21 is patterned, etching with
It and further include to the base after metal filling is to form multiple first contact holes 27 being electrically connected with the peripheral circuit region 21
20 surface of plate carries out the step of chemical machinery exposure mask.
As shown in Figure 7, it is preferable that after described the step of carrying out chemical machinery exposure mask to 20 surface of substrate, also wrap
It includes the step of depositing silica cap layers 31 on the substrate 20, to protect the metal in first contact hole 27 to fill not
It is destroyed by subsequent technique.
Preferably, the thickness of the silica cap layers is greater than 3000 angstroms.
Embodiment three
The embodiment of the present invention three proposes a kind of preparation method of three-dimensional storage, in this embodiment, will description with
The different part of upper embodiment, same section will not be described in great detail.
As shown in Figure 9, it is preferable that it is described after the metal gate 29 that the array memory block 22 forms storage unit, also
Include the steps that depositing silica-filled layer 32 in the silica cap layers 31.
Example IV
The embodiment of the present invention four proposes a kind of preparation method of three-dimensional storage, in this embodiment, will description with
The different part of upper embodiment, same section will not be described in great detail.
As shown in Figure 10, it is preferable that the top of the second contact hole 30 of the array memory block 22 and the peripheral circuit
The top of first contact hole 27 in area 21 is not in a horizontal plane.
Preferably, the top of the second contact hole 30 of the array memory block 22 is higher than the first of the peripheral circuit region 21
The top of contact hole 27.
Embodiment five
The embodiment of the present invention five proposes that a kind of three-dimensional memory structure, the three-dimensional memory structure are by such as above-mentioned reality
Apply what method described in one to four any one of example was prepared.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (11)
1. a kind of preparation method of three-dimensional storage, which comprises the steps of:
One substrate is provided, forms the peripheral circuit region and array memory block of three-dimensional storage on the substrate；
Form the flat insulating layer in surface on the substrate to cover above-mentioned peripheral circuit region and array memory block；
First the insulating layer on the peripheral circuit region is patterned, etching and metal filling are to form and the periphery electricity
Multiple first contact holes of road area electrical connection；
Thereafter the channel region of storage unit is formed in the array memory block；
The metal gate of storage unit is formed in the array memory block；
Insulating layer on the array memory block is patterned, etching and metal filling are stored with being formed with the array
Multiple second contact holes of each metal gate electrical connection in area.
2. a kind of preparation method of three-dimensional storage as described in claim 1, it is characterised in that: form the array memory block
Multilayer lamination structure including being alternatively formed silicon nitride layer and silicon oxide layer on the substrate；Using photoetching process described more
At least side of layer heap stack structure forms stepped region so that a part of upper surface of each silicon nitride layer is exposed to stepped region.
3. a kind of preparation method of three-dimensional storage as described in claim 1, it is characterised in that: described to the peripheral circuit
Insulating layer in area is patterned, and etching and metal filling are to form be electrically connected with the peripheral circuit region multiple first
After contact hole, further include the steps that carrying out chemical machinery exposure mask to the substrate surface.
4. a kind of preparation method of three-dimensional storage as claimed in claim 3, it is characterised in that: described to the substrate surface
After the step of carrying out chemical machinery exposure mask, further include the steps that depositing silica cap layers on the substrate, to protect
The metal filling stated in the first contact hole is not destroyed by subsequent technique.
5. a kind of preparation method of three-dimensional storage as claimed in claim 4, it is characterised in that: the silica cap layers
Thickness is greater than 3000 angstroms.
6. a kind of preparation method of three-dimensional storage as claimed in claim 4, it is characterised in that: described to be stored in the array
Area is formed after the metal gate of storage unit, further includes the step that silica-filled layer is deposited in the silica cap layers
Suddenly.
7. a kind of preparation method of three-dimensional storage as described in claim 1, it is characterised in that: the metal filling is used
Metal material be tungsten.
8. a kind of preparation method of three-dimensional storage as described in claim 1, it is characterised in that: the material of the metal gate is
Tungsten.
9. a kind of preparation method of three-dimensional storage as described in claim 1, it is characterised in that: the of the array memory block
The top of first contact hole at the top of two contact holes and the peripheral circuit region is not in a horizontal plane.
10. a kind of preparation method of three-dimensional storage as claimed in claim 9, it is characterised in that: the array memory block
The top of second contact hole is higher than the top of the first contact hole of the peripheral circuit region.
11. a kind of three-dimensional memory structure, which is characterized in that the three-dimensional memory structure is any by such as claim 1-10
What method described in one was prepared.
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| CN201710724649.1A CN107482015B (en) | 2017-08-22 | 2017-08-22 | A kind of preparation method and its structure of three-dimensional storage |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107706182A (en) * | 2017-08-22 | 2018-02-16 | 长江存储科技有限责任公司 | The preparation method and its structure of a kind of three-dimensional storage |
| CN108649034B (en) * | 2018-05-11 | 2019-08-06 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN112635489A (en) * | 2019-08-02 | 2021-04-09 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of manufacturing the same |
| CN113035870B (en) * | 2021-03-01 | 2022-06-24 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811554A (en) * | 2012-11-13 | 2014-05-21 | 三星电子株式会社 | Semiconductor devices and methods of manufacturing the same |
| CN107706182A (en) * | 2017-08-22 | 2018-02-16 | 长江存储科技有限责任公司 | The preparation method and its structure of a kind of three-dimensional storage |
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| KR102523139B1 (en) * | 2015-11-25 | 2023-04-20 | 삼성전자주식회사 | A semiconductor memory device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811554A (en) * | 2012-11-13 | 2014-05-21 | 三星电子株式会社 | Semiconductor devices and methods of manufacturing the same |
| CN107706182A (en) * | 2017-08-22 | 2018-02-16 | 长江存储科技有限责任公司 | The preparation method and its structure of a kind of three-dimensional storage |
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