CN107481948B - Layout structure of process window for simultaneously detecting multiple bottom contact plugs - Google Patents

Layout structure of process window for simultaneously detecting multiple bottom contact plugs Download PDF

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CN107481948B
CN107481948B CN201610403191.5A CN201610403191A CN107481948B CN 107481948 B CN107481948 B CN 107481948B CN 201610403191 A CN201610403191 A CN 201610403191A CN 107481948 B CN107481948 B CN 107481948B
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bottom contact
layout structure
phase change
metal layers
material layer
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CN107481948A (en
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李莹
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention provides a layout structure of a process window for simultaneously detecting a plurality of bottom contact plugs, which comprises the following steps: the phase change material layer is electrically connected with a plurality of first metal layers of the test pad, the first metal layers are transversely arranged at the same interval, and the trend and the characteristic dimension of the first metal layers are consistent with those of the phase change material layer; the layout structure comprises a plurality of layout structures, a plurality of second metal layers electrically connected with the active region, wherein the second metal layers positioned outside the central position of the layout structure are isolated from each other, and the trend of the second metal layers is vertical to the trend of the first metal layers. According to the invention, the process window of the bottom contact plug can be comprehensively and effectively detected, and the reliability of the process is improved.

Description

Layout structure of process window for simultaneously detecting multiple bottom contact plugs
Technical Field
The invention relates to a semiconductor manufacturing process, in particular to a layout structure of a process window for simultaneously detecting a plurality of bottom contact plugs.
Background
A Phase Change Random Access Memory (PCRAM) is a memory having a high read/write speed, which is widely used in integrated circuits. The key step of integrating the phase change random access memory is to form a Bottom Contact Plug (Bottom Contact Plug) for communicating the metal electrode and the phase change material layer, wherein the Bottom Contact Plug contacts the phase change material layer from the Bottom of the phase change material (GST) layer. When a current with a certain intensity passes through the bottom contact plug, the bottom contact plug generates joule heat to change the phase change state of the phase change material layer, so that the working state of the phase change memory is controlled, namely the function of writing data in the phase change memory is realized when the phase change material layer is changed from an amorphous state to a crystalline state, and the function of reading data in the phase change memory is realized when the phase change material layer is changed from the crystalline state to the amorphous state.
In order to reduce the driving power consumption of the phase change random access memory, the contact area of the bottom contact plug and the phase change material layer should be reduced. With the continuous reduction of the feature size of the semiconductor device, the window critical value of the existing photolithography process has reached a limit, and cannot meet the requirement of defining the pattern of the bottom contact plug having a smaller contact area with the bottom of the phase change material layer, and the pattern of the bottom contact plug is easily deviated when formed at a predetermined position. After the material layer constituting the bottom contact plug is formed, chemical mechanical polishing needs to be performed to remove the portion of the material layer beyond the interlayer dielectric layer where the bottom contact plug is located. After the phase change material layer is formed, it is necessary to remove unnecessary portions by a chemical mechanical polishing or etching process. The polishing and etching processes may damage the bottom contact plug formed, resulting in reduced memory performance.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a layout structure of a process window for simultaneously detecting a plurality of bottom contact plugs, which comprises the following steps: the phase change material layer is electrically connected with a plurality of first metal layers of the test pad, the first metal layers are transversely arranged at the same interval, and the trend and the characteristic dimension of the first metal layers are consistent with those of the phase change material layer; the layout structure comprises a plurality of layout structures, a plurality of second metal layers electrically connected with the active region, wherein the second metal layers positioned outside the central position of the layout structure are isolated from each other, and the trend of the second metal layers is vertical to the trend of the first metal layers.
In one example, upper ends of the plurality of bottom contact plugs are in contact with the phase change material layer.
In one example, the second metal layer located at the right center of the layout structure penetrates through the layout structure and two ends of the second metal layer are electrically connected to the test pads through the third metal layer.
In one example, the third metal layer is electrically connected to a component monitoring the test pad through the active region.
In one example, the plurality of bottom contact plugs are cylindrical.
In one example, the plurality of bottom contact plugs are in a regular L shape, and a narrow side of an upper end of the regular L-shaped bottom contact plug is parallel to the direction of the phase change material layer.
In one example, the plurality of bottom contact plugs are in a regular L shape, and a narrow side of an upper end of the regular L-shaped bottom contact plug is perpendicular to the direction of the phase change material layer.
In one example, a first plurality of reticles for defining dimensions of the plurality of right L-shaped bottom contact plugs is also included.
In one example, a second plurality of photomasks for isolating the plurality of bottom contact plugs in the shape of a regular L from each other is also included.
In one example, the layout further comprises pattern layers which are positioned on two sides of the second metal layer at the positive center of the layout and used for adding a process window for a process of forming the bottom contact plug.
According to the invention, the process window of the bottom contact plug can be comprehensively and effectively detected, and the reliability of the process is improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 is a schematic diagram of a top view of a memory cell array of a conventional random access memory;
fig. 2 is a schematic diagram of a layout structure of a process window for simultaneously detecting a plurality of bottom contact plugs according to a first exemplary embodiment of the present invention;
fig. 3 is a schematic diagram of a layout structure of a process window for simultaneously detecting a plurality of bottom contact plugs according to a second exemplary embodiment of the present invention;
fig. 4 is a schematic diagram of a layout structure of a process window for simultaneously detecting a plurality of bottom contact plugs according to a third exemplary embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a bottom contact plug of the layout shown in FIG. 2;
fig. 6 is a schematic cross-sectional view of a bottom contact plug of the layout shown in fig. 3 and 4.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Referring to fig. 1, there is shown a schematic diagram of a top view of a memory cell array of a conventional random access memory.
In the memory cell array shown in fig. 1, a phase change material layer 100 is formed at a node position where a word line 101 and a bit line 102 intersect. In the process of manufacturing the memory cell array, the bottom contact plug contacts the phase change material layer from the bottom of the phase change material layer, after the material layer constituting the bottom contact plug is formed, chemical mechanical polishing needs to be performed to remove a portion of the material layer beyond the interlayer dielectric layer where the bottom contact plug is located, after the phase change material layer is formed, an unnecessary portion needs to be removed through chemical mechanical polishing or an etching process, and the polishing and the etching process may damage the formed bottom contact plug. The bottom contact plugs of the memory cells at the edge of the wafer are more susceptible to damage from the above process than the bottom contact plugs of the memory cells at the center of the wafer, such as the portion indicated by the dashed circle 103, and thus an abnormal current flow as shown by the arrows in fig. 1 may occur, resulting in a failure of the memory cell array.
In order to find the condition of the formed bottom contact plug in time, a layout structure of a process window for detecting the bottom contact plug needs to be provided so as to find the position of the damaged bottom contact plug in time, and accordingly, the setting parameters of the process window for forming the bottom contact plug are adjusted in a targeted manner.
Next, a layout structure of a process window for simultaneously detecting a plurality of bottom contact plugs according to the present invention will be explained with reference to the following exemplary embodiments.
[ exemplary embodiment one ]
Referring to fig. 2, a schematic diagram of a layout structure of a process window for simultaneously detecting a plurality of bottom contact plugs according to a first exemplary embodiment of the present invention is shown.
The plurality of first metal layers 201 which are transversely arranged at the same interval are electrically connected with the test pad 202, a phase change material layer is arranged below the first metal layers 201, and the direction and the characteristic dimension of the phase change material layer are consistent with those of the first metal layers 201.
The upper end of the bottom contact plug is in contact with the phase change material layer, when a current with a certain intensity passes through the bottom contact plug, the bottom contact plug generates Joule heat to change the phase change state of the phase change material layer, so that the working state of the phase change memory is controlled, namely the phase change material layer is changed from an amorphous state to a crystalline state to realize the function of writing data in the phase change memory, and the phase change material layer is changed from the crystalline state to the amorphous state to realize the function of reading data in the phase change memory. As shown in fig. 5, the bottom contact plug is cylindrical.
The bottom contact plug is electrically connected with an active region in the substrate through a second metal layer 203, the direction of the second metal layer 203 is perpendicular to the direction of the first metal layer 201, wherein the second metal layer 203 located at the positive center of the layout structure penetrates through the layout structure from left to right and two ends of the second metal layer are electrically connected to a test pad through a third metal layer 204, and the third metal layer 204 is electrically connected with an element monitoring the test pad through the active region in the substrate. The monitoring element may be one commonly used in the art, and is not particularly limited herein.
The area 205 marked with a dashed box on both sides of the second metal layer 203 located at the very center of the layout structure represents a pattern layer for adding a process window for a process of forming a bottom contact plug.
[ second exemplary embodiment ]
Referring to fig. 3, a diagram of a layout structure of a process window for simultaneously detecting a plurality of bottom contact plugs according to a second exemplary embodiment of the present invention is shown.
The plurality of first metal layers 301 which are transversely arranged at the same interval are electrically connected with the test pad 302, a phase change material layer is arranged below the first metal layers 301, and the direction and the characteristic dimension of the phase change material layer are consistent with those of the first metal layers 301.
The upper end of the bottom contact plug is in contact with the phase change material layer, when a current with a certain intensity passes through the bottom contact plug, the bottom contact plug generates Joule heat to change the phase change state of the phase change material layer, so that the working state of the phase change memory is controlled, namely the phase change material layer is changed from an amorphous state to a crystalline state to realize the function of writing data in the phase change memory, and the phase change material layer is changed from the crystalline state to the amorphous state to realize the function of reading data in the phase change memory. As shown in fig. 6, the bottom contact plug is in a regular L shape, and the narrow side of the upper end of the bottom contact plug is parallel to the direction of the phase change material layer.
The bottom contact plug is electrically connected with an active region in the substrate through a second metal layer 303, the direction of the second metal layer 303 is perpendicular to the direction of the first metal layer 301, wherein the second metal layer 303 located at the positive center of the layout structure penetrates through the layout structure from left to right and two ends of the second metal layer are electrically connected to a test pad through a third metal layer 304, and the third metal layer 304 is electrically connected with an element monitoring the test pad through the active region in the substrate. The monitoring element may be one commonly used in the art, and is not particularly limited herein.
The area 305 indicated by a dashed box on both sides of the second metal layer 303 located at the very center of the layout represents a pattern layer that adds a process window for the process of forming the bottom contact plug.
To ensure the accuracy of the bottom contact plug dimensions, a first mask 306 is provided to define the bottom contact plug dimensions (height, thickness). To ensure the non-communication between the bottom contact plugs, a second mask 307 is provided to isolate the bottom contact plugs.
[ exemplary embodiment III ]
Referring to fig. 4, there is shown a schematic diagram of a layout structure of a process window for simultaneously detecting a plurality of bottom contact plugs according to a third exemplary embodiment of the present invention.
The plurality of first metal layers 401 which are transversely arranged at the same interval are electrically connected with the test pad 402, a phase change material layer is arranged below the first metal layers 401, and the direction and the characteristic dimension of the phase change material layer are consistent with those of the first metal layers 401.
The upper end of the bottom contact plug is in contact with the phase change material layer, when a current with a certain intensity passes through the bottom contact plug, the bottom contact plug generates Joule heat to change the phase change state of the phase change material layer, so that the working state of the phase change memory is controlled, namely the phase change material layer is changed from an amorphous state to a crystalline state to realize the function of writing data in the phase change memory, and the phase change material layer is changed from the crystalline state to the amorphous state to realize the function of reading data in the phase change memory. As shown in fig. 6, the bottom contact plug is in a regular L shape, and the wide side of the upper end of the bottom contact plug is parallel to the direction of the phase change material layer.
The bottom contact plug is electrically connected with an active region in the substrate through a second metal layer 403, the direction of the second metal layer 403 is perpendicular to the direction of the first metal layer 401, wherein the second metal layer 403 located at the positive center of the layout structure penetrates through the layout structure from left to right and two ends of the second metal layer are electrically connected to a test pad through a third metal layer 404, and the third metal layer 404 is electrically connected with an element monitoring the test pad through the active region in the substrate. The monitoring element may be one commonly used in the art, and is not particularly limited herein.
The area 405 marked with a dashed box on both sides of the second metal layer 403 located at the very center of the layout represents a pattern layer that adds a process window for the process of forming the bottom contact plug.
To ensure the accuracy of the dimensions of the bottom contact plug, a first mask 406 is provided to define the dimensions (height, thickness) of the bottom contact plug. To ensure the non-communication between the bottom contact plugs, a second mask 407 is disposed to isolate the bottom contact plugs.
According to the layout structure of the process window for simultaneously detecting a plurality of bottom contact plugs in the exemplary embodiment, the process window of the bottom contact plugs positioned in different regions (particularly at the edge of a wafer) of the wafer can be effectively monitored, the bottom contact plugs with different shapes (such as a cylindrical shape and a positive L shape) can be considered, the narrow side of the upper end of the positive L-shaped bottom contact plug can be considered to be parallel to or perpendicular to the direction of the phase change material layer, the device where each bottom contact plug is positioned has an independent metal layer lead electrically connected with the active region in the substrate, the performance of each phase change memory device can be independently verified, a selector (selector) serving as a switch (switch) is not required, and the complexity of layout of the layout structure is reduced.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (9)

1. A layout structure for simultaneously detecting process windows for a plurality of bottom contact plugs, comprising:
a plurality of first metal layers (201,301,401) electrically connected with the test pads (202,302,402), wherein the first metal layers are transversely arranged at the same interval, and the orientation and the characteristic dimension of the first metal layers are consistent with the orientation and the characteristic dimension of the phase change material layer;
a plurality of second metal layers (203,303,403) electrically connected with the active region, wherein the second metal layers outside the central position of the layout structure are isolated from each other, and the trend of the second metal layers is vertical to the trend of the first metal layers; upper ends of the plurality of bottom contact plugs are in contact with the phase change material layer.
2. The layout structure according to claim 1, wherein the second metal layer located at the very center of the layout structure penetrates the layout structure and both ends are electrically connected to a test pad through a third metal layer (204,304,404).
3. The layout structure according to claim 2, wherein the third metal layer is electrically connected to an element monitoring the test pad through the active region.
4. The layout structure according to claim 1, wherein the plurality of bottom contact plugs are cylindrical.
5. The layout structure according to claim 1, wherein the bottom contact plugs are in a regular L shape, and a narrow edge of an upper end of the regular L-shaped bottom contact plug is parallel to the direction of the phase change material layer.
6. The layout structure according to claim 1, wherein the bottom contact plugs are in a regular L shape, and a narrow edge of an upper end of the bottom contact plug in the regular L shape is perpendicular to the direction of the phase change material layer.
7. The layout structure according to claim 5 or 6, further comprising a plurality of first reticles (306,406) for defining the dimensions of the plurality of bottom contact plugs in a positive L-shape.
8. The layout structure according to claim 5 or 6, further comprising a plurality of second photomasks (307,407) for isolating the plurality of bottom contact plugs in the regular L shape from each other.
9. The layout structure according to claim 1, further comprising pattern layers (205,305,405) on both sides of the second metal layer at the right central position of the layout for adding a process window for a process of forming the bottom contact plug.
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Citations (5)

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Publication number Priority date Publication date Assignee Title
CN101777571A (en) * 2009-12-30 2010-07-14 复旦大学 Array structure of phase-change memory and preparation method thereof
CN101794862A (en) * 2010-02-24 2010-08-04 中国科学院半导体研究所 Manufacturing method of vertical phase-change memory
CN101800237A (en) * 2010-02-09 2010-08-11 中国科学院上海微***与信息技术研究所 Phase change memory chip layout structure
CN101826596A (en) * 2010-03-31 2010-09-08 中国科学院半导体研究所 Production method of phase-change memory
CN103456881A (en) * 2012-06-05 2013-12-18 中芯国际集成电路制造(上海)有限公司 Phase change random access memory manufacturing method

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US6855975B2 (en) * 2002-04-10 2005-02-15 Micron Technology, Inc. Thin film diode integrated with chalcogenide memory cell
US20090301894A1 (en) * 2008-06-09 2009-12-10 Carsten Ehlers Method of fabricating an integrated circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101777571A (en) * 2009-12-30 2010-07-14 复旦大学 Array structure of phase-change memory and preparation method thereof
CN101800237A (en) * 2010-02-09 2010-08-11 中国科学院上海微***与信息技术研究所 Phase change memory chip layout structure
CN101794862A (en) * 2010-02-24 2010-08-04 中国科学院半导体研究所 Manufacturing method of vertical phase-change memory
CN101826596A (en) * 2010-03-31 2010-09-08 中国科学院半导体研究所 Production method of phase-change memory
CN103456881A (en) * 2012-06-05 2013-12-18 中芯国际集成电路制造(上海)有限公司 Phase change random access memory manufacturing method

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