CN107480359B - FPGA area modeling method under advanced nano process - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an FPGA area modeling method under an advanced nano process. The invention mainly combines the design rule DRC parameter of the nanometer process and the self characteristic of the FPGA chip layout, and carries out area modeling based on the layout characteristic of the basic component sub-circuit of the lower layer of the circuit. For example, for programmable interconnect circuits, the most important low-level basic component sub-circuits are the NMOS pass-transistors and CMOS inverters: for an NMOS transmission tube, layout realization technologies such as a transistor with two ends not shared, a transistor with one end shared, a transistor with two ends shared and the like are researched by combining with a design rule DRC parameter of a nanometer process, and an area evaluation model is provided; for the CMOS inverter, a layout implementation technology of a gate folding structure and the influence of different sizes and different folding numbers on the area are researched, and an area evaluation model is provided; other basic component sub-circuit area models use a similar approach. The method can accurately predict the area of the layout in the early stage of circuit design.

Description

FPGA area modeling method under advanced nano process

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to an area modeling method for an FPGA circuit.

Background

For the design of an FPGA chip, the area of design implementation is an important evaluation parameter. The area of a layout in an actual chip can be used for measurement, but the circuit needs to be comprehensively realized, and the work cannot be completed in a short time, so that the evaluation cannot be used as a means for early evaluation.

At present, the academia has research on an area modeling method for FPGA, the academia usually adopts a minimum equivalent transistor number method, a polynomial fitting method and the like [1-6], the method does not consider the FPGA layout design characteristics under the nanometer small process, such as advanced process layout design strategies like source and drain sharing, grid folding multi-finger structures and the like, and is not applicable.

Reference documents:

[1]BETZ V,ROSE J,MARQUARDT A.Architecture and CAD for Deep-Submicron FPGAS[J].Springer International,1999,497

[2]KUON I,ROSE J.Measuring the Gap Between FPGAs and ASICs[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2007,26(2):203-15.

[3]KUON I,ROSE J.Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design[J].Very Large Scale Integration Systems IEEE Transactions on,2011,19(1):71-84.

[4]KUON I,ROSE J.Measuring the Navigating the Gap Between FPGAs and ASICs[D].CANADA:University of Toronto,2008.

[5]KHAN F F,YE A.An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures[A].In:proceedings of the International Conference on Field Programmable Logic and Applications[C],F,2016.

[6]CHIASSON C,BETZ V.COFFE:Fully-automated transistor sizing for FPGAs[A].In:proceedings of the International Conference on Field-Programmable Technology[C],F,2013.。

disclosure of Invention

The invention aims to provide an FPGA area modeling method under an advanced nano process, which is used for predicting the area of a circuit layout at the early stage of circuit design of an FPGA chip.

The FPGA area modeling method under the advanced nano process provided by the invention carries out area modeling based on the layout characteristics of the basic component sub-circuit of the circuit lower layer according to the design Rule DRC (design Rule checking) parameter of the nano process and the self characteristics of the FPGA chip layout. For example, in the case of a programmable interconnect circuit, the most important low-level basic component circuits are the NMOS pass transistor and the CMOS inverter: for an NMOS transmission tube, layout realization technologies such as a transistor with two ends not shared, a transistor with one end shared, a transistor with two ends shared and the like are researched by combining with a design rule DRC parameter of a nanometer process, and an area evaluation model is provided; for a CMOS inverter, a layout implementation technology of a gate folding structure and the influence of different sizes and different folding numbers on the area are researched by combining with a design rule DRC parameter of a nanometer process, and an area evaluation model is provided. The area model obtained by the design rule DRC parameter and the layout implementation characteristic of the basic component circuit of the low layer of the FPGA circuit can accurately predict the area of the layout in the early stage of circuit design, and the difference between the predicted layout area and the actual layout area is within 10%.

The method of the present invention is further described below using area modeling of programmable interconnect circuits as an example, and other circuit methods are similar.

The FPGA interconnect circuitry consists of various MUXs, which in turn typically consist of NMOS and CMOS, see fig. 1. According to the self characteristics of the topological structure of the FPGA interconnection circuit, a large number of interconnection lines are shared by a plurality of MUXs. That is, there may be many shared ports between different MUXs. Therefore, in an actual layout, there are more cases that can be shared. As shown in fig. 1(a) (b), if there are more common inputs between two MUXs, then these NMOS transistors can be connected end to end when the layout is implemented, resulting in a layout similar to that shown in fig. 1 (c). Moreover, this situation is quite common in FPGA chips. As shown in fig. 1(b), six transistors, MUX0_ MN0, MUX0_ MN1, MUX1_ MN1, MUX1_ MN2, MUX0_ MN2 and MUX0_ MN3, have two terminals shared by another transistor, and the area overhead is smaller. More ports are shared for the NMOS transistor, meaning a smaller area. Of course, such a long layout may not meet the principle that the layout shape is drawn as square as possible. However, because the number of MUXs in the interconnection circuit is large, two or more MUXs can be combined to realize layout completely through reasonable layout, so that the layout of the group of MUXs tends to be square, and later layout and wiring are facilitated. Based on the above analysis, for the NMOS pass tubes, the present invention divides the NMOS pass tubes into three categories: respectively establishing an area model by using a transistor with two ends not shared, a transistor with one end shared and a transistor with two ends shared; the area of all transistors is added to obtain the area of all NMOS pass transistors in the interconnection.

The area models of the three NMOS pass transistors are derived as follows: for NMOS pass transistors, the end-to-end connection shown in fig. 1(c) can be realized because both the input and output of the pass transistors can be shared with other transistors, such as MUX0_ MN0 in fig. 2, and the output is shared because the first layer of pass transistors uses decode mode and is transmitted to the next level of MUX, and is typically connected by the same layer of metal. And the input terminal is shared, namely a shared port exists on the topological structure, and the driving source of the shared port comes from the outside of the circuit. This aspect requires as large a metal area as possible for the contacts. On the other hand, the second layer metal and the first layer often have different routing directions. In the metal connection between the first layer and the second layer shown in fig. 2, there will be a minimum distance m _1 between the metals in the same layer. This determines that the common active region can be divided into two cases. The first is an internal signal common active region, and the second is an input signal common active region. The first one is used for in-circuit connections and can be implemented with as much as possible of a first layer of metal. While the second case tends to go to the upper level of metal to complete the connections between the sub-circuits. Therefore, in the second case, the distance between two adjacent gates is larger, as shown by s _3 in fig. 2.

Thus, the area model of the three NMOS pass transistors is as follows:

transistors are not shared across:

Area_{nmos 0}＝(x_2+2s_1+L)(x_1+h_1+h_2+w_eff) (1)

one-terminal common transistor:

two-terminal sharing transistor:

for CMOS inverters, the layout is suitably implemented in a folded structure when the size is relatively large. By doing so, the shape of the layout can be more reasonable to a certain extent, and meanwhile, the area can be reduced appropriately. Since folding is equivalent to using some active area sharing. However, each step of folding is added, the grid needs to extend out of the active region for a certain length, and extra area consumption is generated, so that the area of the newly added layout needs to be added when an area model is calculated.

The CMOS inverters would be connected directly with the gate poly of the PMOS and NMOS. The area of the polysilicon layer connected to the first layer metal by vias is of course also considered. And determining the boundary distance h _3 from the active region to the ion implantation according to the spacing rule between the through hole and the active region, the spacing rule between the active region and the ion implantation region and the like. The drivers of the interconnect circuits tend to be larger and, in order to maintain better performance, the Pickup (ohmic area) needs to be added more frequently to prevent latch-up and improve performance. According to layout design experience, a Pickup is added to one end, which is not connected with metal, of the driver, or a certain area is reserved to facilitate interconnection and routing. As shown in fig. 3. And the spacing of the two cases is not very different. The minimum height h _4 of a Pickup is taken as a measure for the pitch of the links or the size of the pickups.

Thus, the area model of the CMOS inverter is specifically as follows:

f represents the number of folds (finger) and for different transistor sizes w _ eff there will be an optimum at different values of F, as shown in fig. 4. Through optimization, the following can be obtained:

when in use

Area_cmosHas a minimum value of]Here, rounding is indicated.

Area_cmosHas the minimum area as follows:

the process parameters referred to in the above formula are shown in table 1.

TABLE 1 description of the parameters

The area model is obtained by adding the area of all NMOS transmission tubes to the sum of the area of all CMOS tubes as follows:

Area_{general assembly}＝∑Area_{nmos 0}+∑Area_{nmos 1}+∑Area_{nmos 2}+∑Area_CMOS (6)

Here Σ denotes the sum of the areas of the same type of tubes.

It should be noted that if there are other types of sub-circuit transistors besides NMOS and CMOS in the interconnection circuit, the Area model Area of the transistor is obtained in the same manner as described above_OthersThen all such tubes are added to equation (6), the total area model is as follows:

Area_{general assembly}＝∑Area_{nmos 0}+∑Area_{nmos 1}+∑Area_{nmos 2}+∑Area_CMOS+ ∑ Area Others (7)

Similar methods can be used for modeling other circuits, such as programmable logic circuits.

Technical effects

By using the area model disclosed by the invention, the layout area of the circuit can be predicted at the early stage of FPGA design. Compared with the existing area, the area model established by the invention has better consistency with the layout. Taking a programmable interconnection circuit of a certain FPGA as an example, analysis shows that the programmable interconnection circuit comprises 9 types of different MUX circuits, namely, various MUX circuits such as DOUBLE, HEX, LONG, IMUX, OMUX, CLK, SRCE, BOUNCE and BYP, and the MUX circuits are taken as experimental objects, so that the difference between the predicted area of the established area model and the actual layout area is within 10%, and the basis for evaluation prediction can be provided for a designer at the initial stage of chip design.

Drawings

The layout of the MOS tubes connected end to end in the MUX in FIG. 1 is schematically realized.

Fig. 2 illustrates the area modeling of three NMOS transistors.

FIG. 3 is a schematic representation of area modeling under different folded configurations.

FIG. 4 is an area for different fold indices for different sizes.

Detailed Description

The area model of the FPGA programmable interconnection circuit realized by the SMIC 65nm process is taken as an example for explanation, and other processes of other circuits are similar.

Taking 9 different types of MUXs of a certain FPGA programmable interconnection circuit as an example, calculating the MUX circuits of DOUBLE, HEX, LONG, IMUX, OMUX, CLK, SRCE, BOUNCE and BYP 9 by using the model in the text, and evaluating by using the methods proposed in the documents [1] and [6] for comparison, wherein the experimental results are shown in Table 2.

Table 2 shows the area of the actual circuit layout, the area obtained by the method of the present invention, and the areas obtained by the documents [1] and [6 ]. Table 3 shows the tolerance between various area models and the actual circuit layout area. As can be seen from Table 3, most of the errors between the predicted layout area and the actual layout area are about 5%, and all the errors are less than 10%. The area model of the document [1] has a large error with the actual layout. In document [6], although the prediction error in an individual circuit is small, most errors are 10% or more. Therefore, the results were analyzed to show that the present invention is more effective.

TABLE 2 comparison of the predicted area of the model with different areas with the actual layout area

Sub-circuit	Layout/um 2	Invention/um 2	Document [1]]/um2	Document [6]/um2
					DOUBLE	14.67	15.52	30.92	16.86
HEX	13.54	14.45	27.82	14.45
					LONG	37.53	34.26	58.52	29.19
IMUX	17.72	19.45	36.76	23.46
					OMUX	18.89	18.90	39.06	21.55
CLK	14.58	14.89	21.52	14.95
					SRCE	15.99	17.39	28.43	18.08
BOUNCE	14.31	13.38	24.01	14.53
					BYP	25.42	25.61	45.93	28.96

TABLE 3 error between area predicted by different area model and actual layout area

Claims (2)

1. An FPGA area modeling method under an advanced nano process is characterized in that area modeling is carried out according to the DRC parameters of the design rules of the nano process and the characteristics of the FPGA chip layout, and from the layout characteristics of the basic circuit formed by the lower layers of the circuit;

for the programmable interconnection circuit, the programmable interconnection circuit is composed of various MUXs, and the MUXs are composed of NMOS transmission tubes and CMOS inverters;

for NMOS pass transistors, the NMOS pass transistors are classified into three categories: respectively establishing an area model by using a transistor with two ends not shared, a transistor with one end shared and a transistor with two ends shared; adding the areas of all transistors to obtain the areas of all NMOS transmission tubes in interconnection; here, the area models of the three NMOS pass transistors are specifically as follows:

transistors are not shared across:

Area_nmos0＝(x_2+2s_1+L)(x_1+h_1+h_2+w_eff) (1)

one-terminal common transistor:

two-terminal sharing transistor:

the area model of the CMOS inverter is specifically as follows:

f represents the number of folds, with optimum values at different values of F for different transistor sizes w _ eff:

when in use

Area_cmosHas a minimum value of]Here, rounding is indicated;

Area_cmosthe minimum area is:

the process parameters involved in the above formula are shown in table 1:

TABLE 1

The area model is obtained by adding the area of all NMOS pass transistors and the area of all CMOS transistors as follows:

Area_{general assembly}＝∑Area_nmos0+∑Area_nmos1+∑Area_nmos2+∑Area_CMOS (6)

Here Σ denotes the sum of the areas of the same type of tubes.

2. The method as claimed in claim 1, wherein if there are other sub-circuit tubes in the interconnect circuit, the Area model Area of the tube is obtained by the same method_OthersAdding all such tubes to equation (6), the total area model is as follows:

Area_{general assembly}＝∑Area_nmos0+∑Area_nmos1+∑Area_nmos2+∑Area_CMOS+∑Area_Others (7)。

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