CN107465217B

CN107465217B - Switch type lithium battery charging circuit and chip without current sampling resistor

Info

Publication number: CN107465217B
Application number: CN201610395747.0A
Authority: CN
Inventors: 杨敏; 苏丹; 秦鹏举
Original assignee: Fuman Microelectronics Group Co ltd
Current assignee: Fuman Microelectronics Group Co ltd
Priority date: 2016-06-03
Filing date: 2016-06-03
Publication date: 2023-03-21
Anticipated expiration: 2036-06-03
Also published as: CN107465217A

Abstract

The invention is suitable for the field of lithium battery charging circuits, and provides a switch type lithium battery charging circuit and a chip without a current sampling resistor. The invention additionally arranges a prejudging circuit and a sampling holding circuit in the traditional switch type lithium battery charging circuit, so that the logic control circuit triggers the prejudging circuit to send a rising edge signal to the sampling holding circuit at the time of 0.5 times of the conduction period of the switch circuit, triggers the sampling holding circuit to sample and hold a sampling voltage signal output by the current sampling circuit and output a current signal, converts the current signal into a voltage signal through the reference current sampling signal amplifying circuit and then compares the voltage signal with the reference voltage to generate an error voltage, so that the logic control circuit can adjust the duty ratio of the conduction time of the switch circuit according to the error voltage, and the lithium battery can be controlled to be charged with constant current without a sampling resistor.

Description

Switch type lithium battery charging circuit and chip without current sampling resistor

Technical Field

The invention belongs to the field of lithium battery charging circuits, and particularly relates to a switch type lithium battery charging circuit and a chip without a current sampling resistor.

Background

With the continuous popularization of mobile communication devices such as smart phones and tablet computers, the cruising ability of the public for the mobile communication devices is higher and higher. Lithium batteries are the first choice for mobile communication devices due to their small size, high energy density, and no memory.

At present, the lithium battery is generally charged by adopting a constant current switch charging circuit, however, the charging current of the lithium battery needs to be monitored by a sampling resistor with very high resistance precision in the conventional constant current switch charging circuit, the sampling resistor has higher cost, the hardware cost of the whole electronic equipment powered by the lithium battery is increased, and the charging efficiency is reduced.

Disclosure of Invention

The invention aims to provide a switch type lithium battery charging circuit without a current sampling resistor, and aims to solve the problems that the conventional constant current switch charging circuit needs to monitor the charging current of a lithium battery through a sampling resistor with very high resistance precision, the sampling resistor is high in cost, the hardware cost of the whole electronic equipment powered by the lithium battery is increased, and the charging efficiency is reduced.

The invention is realized in such a way that a switch type lithium battery charging circuit without a current sampling resistor comprises a switch circuit, a current sampling circuit, an inductor L, a current conversion voltage circuit, a prejudging circuit, a sample holding circuit, a reference current sampling signal amplifying circuit, a constant current and constant voltage switching circuit, a PWM (pulse width modulation) comparator, a logic control circuit, a reference voltage sampling signal amplifying circuit and a compensating circuit;

the input end of the switch circuit and the first input end of the current sampling circuit are connected to an external power supply in a sharing mode, the output end of the switch circuit and the second input end of the current sampling circuit are connected to one end of an inductor L in a sharing mode, and the other end of the inductor L is connected to the anode of the lithium battery;

the output end of the current sampling circuit is connected with the input end of the current-to-voltage circuit;

the output end of the current-to-voltage circuit is connected with the input end of the sampling hold circuit;

the output end of the sample-hold circuit is connected with the first input end of the reference current sampling signal amplifying circuit, the first logic signal input end of the sample-hold circuit is connected with the logic signal output end of the prejudging circuit, the second logic signal input end of the sample-hold circuit and the logic signal input end of the prejudging circuit are connected with the logic signal output end of the logic control circuit in a shared mode, and the enable input end of the sample-hold circuit and the enable input end of the prejudging circuit are connected with the enable output end of the logic control circuit in a shared mode;

the input end of the prejudging circuit is connected with an external power supply, the output end of the prejudging circuit is connected with the anode of the lithium battery, and the reference voltage input end of the prejudging circuit inputs reference voltage;

the second input end of the reference current sampling signal amplifying circuit is connected with an external power supply to generate reference voltage, and the output end of the reference current sampling signal amplifying circuit is connected with the first input end of the constant current and constant voltage switching circuit;

a first input end of the reference voltage sampling signal amplifying circuit is connected with an external power supply to generate reference voltage, a second input end of the reference voltage sampling signal amplifying circuit is connected with the anode of the lithium battery, and an output end of the reference voltage sampling signal amplifying circuit is connected with a second input end of the constant-current and constant-voltage switching circuit;

the output end of the constant-current constant-voltage switching circuit is connected with the positive input end of the PWM comparator, and the negative input end of the PWM comparator is connected with the compensating circuit;

the output end of the PWM comparator is connected with the input end of the logic control circuit, and the output end of the logic control circuit is connected with the controlled end of the switch circuit;

when the switch circuit is switched on, the current sampling circuit samples a sampling current signal flowing into the inductor L, and the current-to-voltage circuit converts the sampling current signal into a sampling voltage signal and sends the sampling voltage signal to the sample-and-hold circuit;

at the time 0.5 times of the conduction time period of the switch circuit, the logic control circuit triggers the prejudging circuit to send a rising edge signal to the sampling and holding circuit, so that the sampling and holding circuit samples and holds the sampling voltage signal and outputs a current signal to the reference current sampling signal amplifying circuit;

the reference current sampling signal amplifying circuit converts the current signal into a voltage signal and compares the voltage signal with the reference voltage to generate an error voltage, the error voltage is transmitted to the logic control circuit through the constant current and constant voltage switching circuit and the PWM comparator, and the logic control circuit adjusts the duty ratio of the conduction time of the switching circuit according to the error voltage so as to control the switching circuit to output a constant charging current to charge the lithium battery.

Preferably, the prejudgment circuit comprises a first logic device, a NOT1, a NOT2, a NOR gate NOR1, a first amplifier, a second amplifier, a third amplifier, PMOS tubes Q1-Q5, NMOS tubes Q6-Q11, resistors R1-R6 and a capacitor C1;

the signal input end of the first logic device is connected with an external power supply, the clock signal end of the first logic device is the logic signal input end of the prejudging circuit, the signal output end of the first logic device is connected with the input end of an NOT1, and the enable end of the first logic device is connected with the output end of the NOR gate NOR 1;

the output end of the NOT1, the grid of the PMOS tube Q1 and the grid of the NMOS tube Q6 are connected in common;

the source electrode of the PMOS tube Q1, the drain electrode of the PMOS tube Q2 and the drain electrode of the NMOS tube Q7 are connected in common, the drain electrode of the PMOS tube Q1 and the drain electrode of the NMOS tube Q6 are connected in common and then respectively connected with the positive electrode of the capacitor C1 and the positive input end of the first amplifier, and the negative electrode of the capacitor C1 is connected with the analog ground;

the source electrode of the NMOS tube Q6 is connected with the drain electrode of the NMOS tube Q8;

the grid electrode of the PMOS tube Q2, the grid electrode of the PMOS tube Q3, the drain electrode of the PMOS tube Q3 and the drain electrode of the NMOS tube Q9 are connected in common, and the source electrode of the PMOS tube Q2 and the source electrode of the PMOS tube Q3 are connected in common with an external power supply;

the grid electrode of the NMOS tube Q7, the grid electrode of the NMOS tube Q8, the grid electrode of the NMOS tube Q10 and the drain electrode of the PMOS tube Q4 are connected in common, and the source electrode of the NMOS tube Q7, the source electrode of the NMOS tube Q8 and the source electrode of the NMOS tube Q10 are connected with analog ground;

the grid electrode of the NMOS tube Q9 is connected with the output end of the second amplifier, the source electrode of the NMOS tube Q9 is connected with the reverse input end of the second amplifier and one end of the resistor R1 in common, and the other end of the resistor R1 is connected with the analog ground;

the grid electrode of the PMOS tube Q4, the grid electrode of the PMOS tube Q5, the drain electrode of the PMOS tube Q5 and the drain electrode of the NMOS tube Q11 are connected in common, and the source electrode of the PMOS tube Q4 and the source electrode of the PMOS tube Q5 are connected in common with an external power supply;

the grid electrode of the NMOS tube Q11 is connected with the output end of the third amplifier, the source electrode of the NMOS tube Q11, the inverting input end of the third amplifier and one end of the resistor R2 are connected in common, and the other end of the resistor R2 is connected with the analog ground;

the first input end of the NOR gate NOR1 is connected with the output end of the NOR gate NOT2, the second input end of the NOR gate NOR1 and the output end of the first amplifier are connected with the logic signal output end of the pre-judging circuit, and the input end of the NOR gate NOT2 is the enabling input end of the pre-judging circuit;

the inverting input end of the first amplifier is the reference voltage input end of the prejudging circuit;

the positive input end of the second amplifier is connected with one end of a resistor R3 and one end of a resistor R4 in common, the other end of the resistor R3 is the input end of the prejudging circuit, the other end of the resistor R4 is grounded, and the resistance values of the resistor R3 and the resistor R4 are equal;

the positive input end of the third amplifier is connected with one end of a resistor R5 and one end of a resistor R6 in common, the other end of the resistor R5 is the output end of the prejudging circuit, the other end of the resistor R6 is grounded, and the resistance value of the resistor R6 is three times that of the resistor R5;

after the time 0.5 times of the conduction period of the switch circuit and before the switch circuit is conducted, the output end of the prejudging circuit outputs current to discharge a capacitor C1, and the initial voltage of the capacitor C1 is equal to the reference voltage;

before the conduction starting moment of the switch circuit to 0.5 time of the conduction time period of the switch circuit, the input end of the prejudging circuit inputs current to charge a capacitor C1;

when the capacitor voltage of the capacitor C1 is equal to the reference voltage again after charging, the prejudging circuit judges that the time is 0.5 times of the conduction time period of the switch circuit, and the logic signal output end of the prejudging circuit sends a rising edge signal to the sample-and-hold circuit.

Preferably, the sample-hold circuit comprises a second logic device, NOT gates NOT 3-NOT 8, an AND gate AND1, an inverse Schmitt trigger ST2, an NOR gate NOR2, an NAND gate NAND1, a resistor R7, a resistor R8, capacitors C2-C5, a PMOS tube Q12, a PMOS tube Q13, NMOS tubes Q14-Q16, a switch S1 AND a switch S2;

the signal input end of the second logic device is connected with an external power supply, the signal output end of the second logic device, the input end of the NOT3, the grid of the PMOS tube Q12, the grid of the NMOS tube Q14 AND the first input end of the AND gate AND1 are connected in common, the clock signal end of the second logic device is the first logic signal input end of the sample-hold circuit, the enabling end of the second logic device is connected with the output end of the NOR gate NOR2, AND the output end of the NOT3 forms the sampling control end of the sample-hold circuit;

the source electrode of the PMOS tube Q12 is connected with an external power supply, and the drain electrode of the PMOS tube Q12, the input end of the reverse Schmitt trigger ST1, one end of the resistor R7 and the anode of the capacitor C2 are connected in common;

the drain electrode of the NMOS tube 14 is connected with the other end of the resistor R7, and the source electrode of the NMOS tube 14 and the negative electrode of the capacitor C2 are connected with the analog ground in common;

the second input end of the AND gate AND1 is connected with the output end of a NOT4, the output end of the AND gate AND1 is connected with the input end of a NOT5, the output end of the NOT5 forms a holding control end of the sampling holding circuit, AND the input end of the NOT4 is connected with the output end of an inverse Schmitt trigger ST 1;

the first input end of the NOR gate NOR2 is connected with the output end of the NOT gate NOT6, the second input end of the NOR gate NOR2 is connected with the output end of the NOT gate NOT7, and the input end of the NOT gate NOT7 is the enabling input end of the sample hold circuit;

the input end of the NOT6 is connected with the output end of the NAND gate NAND1, the first input end of the NAND gate NAND1 is connected with the output end of the NOT8, and the second input end of the NAND gate NAND', the gate of the PMOS tube Q13 and the gate of the NMOS tube Q15 are connected together to form a second logic signal input end of the sample-and-hold circuit;

the input end of the NOT8 is connected with the output end of the Schmitt trigger ST2, the input end of the Schmitt trigger ST2, the anode of the capacitor C3, one end of the resistor R8 and the drain electrode of the PMOS tube Q13 are connected in common, and the source electrode of the PMOS tube Q13 is connected with an external power supply;

the drain electrode of the NMOS tube Q15 is connected with the other end of the resistor R8, and the source electrode of the NMOS tube Q15 and the negative electrode of the capacitor C3 are connected to the analog ground in common;

one end of the switch S1 is an input end of the sample hold circuit, and the other end of the switch S1, the anode of the capacitor C4 and one end of the switch S2 are connected in common;

the other end of the switch S2, the positive electrode of the capacitor C5 and the grid electrode of the NMOS tube Q16 are connected in common, the drain electrode of the NMOS tube Q16 is the output end of the sample-hold circuit, and the negative electrode of the capacitor C4, the negative electrode of the capacitor C5 and the source electrode of the NMOS tube Q16 are connected in common to an analog ground;

at the starting moment of the switch circuit being turned on, the sampling and holding circuit receives the rising edge signal of the prejudging circuit, the sampling control end triggers the switch S1 to be closed, the switch S2 is opened at the moment, and the input end of the sampling and holding circuit inputs the sampling voltage signal output by the current-to-voltage circuit to charge the capacitor C4;

at the time 0.5 times the conduction period of the switch circuit, the sampling control end triggers the switch S1 to be switched off, and at the time, the capacitor C4 stores a sampling current signal corresponding to the time 0.5 times;

after the time 0.5 times the conduction period of the switch circuit and before the switch circuit is conducted, the holding control end triggers the switch S2 to be closed, so that the capacitor C4 charges the capacitor C5, when the voltage of the capacitor C4 is equal to the voltage of the capacitor C5, the holding control end triggers the switch S2 to be opened, so that the capacitor C5 stores the sampling current signal corresponding to the time 0.5 times, and the sampling current signal is output to the reference current sampling signal amplifying circuit through the NMOS tube Q16.

Preferably, the reference current sampling signal amplifying circuit includes a reference current generating unit composed of a first equivalent current source, an NMOS transistor Q17, an NMOS transistor Q18, a PMOS transistor Q19, and a PMOS transistor Q20;

the input end of the first equivalent current source, the source electrode of a PMOS tube Q19 and the source electrode of a PMOS tube Q20 are connected in common to form the input end of the reference current sampling signal amplifying circuit, the output end of the first equivalent current source, the drain electrode of an NMOS tube Q17, the grid electrode of the NMOS tube Q17 and the grid electrode of an NMOS tube Q18 are connected in common, and the source electrode of the NMOS tube Q17 and the source electrode of the NMOS tube Q18 are connected in common to an analog ground;

the grid electrode of the PMOS tube Q19 and the grid electrode of the PMOS tube Q20 are connected, the drain electrode of the PMOS tube Q19 and the drain electrode of the NMOS tube Q18 are connected in common, and the drain electrode of the PMOS tube Q20 is a first input end and an output end of the reference current sampling signal amplifying circuit;

the first equivalent current source generates a reference current to flow through the PMOS tube Q20, and the reference current and a sampling current signal output by the sampling holding circuit form an error voltage through an equivalent resistor between the PMOS tube Q20 and the NMOS tube Q16 and are output to the constant-current constant-voltage switching circuit.

Preferably, the reference current sampling signal amplifying circuit includes an error amplifier and a reference voltage generating unit; the reference voltage generating unit comprises a second equivalent current source, an NMOS tube Q21, an NMOS tube Q22, a resistor R9 and a resistor R10;

the positive input end of the error amplifier and one end of the resistor R9 are connected in common to form a first input end of the reference current sampling signal amplifying circuit, the reverse input end of the error amplifier and one end of the resistor R10 are connected in common to the drain electrode of the NMOS tube Q21, and the output end of the error amplifier is the output end of the reference current sampling signal amplifying circuit;

the input end of the second equivalent current source, the other end of the resistor R9 and the other end of the resistor R10 are connected in common to form a second input end of the reference current sampling signal amplifying circuit, the output end of the second equivalent current source is connected in common to the drain electrode of the NMOS transistor Q21, the grid electrode of the NMOS transistor Q21 and the grid electrode of the NMOS transistor Q22, and the source electrode of the NMOS transistor Q21 and the source electrode of the NMOS transistor Q22 are connected in common to the analog ground;

the second equivalent current source generates a reference current which flows through a resistor R10, so that a reference voltage generated on the resistor R10 is output to the reverse input end of the error amplifier, a sampling current signal output by the sampling and holding circuit is converted into a voltage signal through a resistor R9, and the error amplifier amplifies the difference between the voltage signal and the reference voltage, so that an error voltage is generated and output to the constant-current constant-voltage switching circuit.

Preferably, the current-to-voltage circuit comprises an NMOS transistor Q23, a drain of the NMOS transistor Q23 is connected to a gate to form an input terminal and an output terminal of the current-to-voltage circuit, and a source of the NMOS transistor Q23 is connected to an analog ground;

the drain electrode of the NMOS tube Q23 inputs the sampling current signal, converts the sampling current signal into a sampling voltage signal and outputs the sampling voltage signal to the sampling hold circuit through the grid electrode of the NMOS tube.

Preferably, the switching circuit comprises a PMOS transistor Q24 and a diode D1;

the grid electrode of the PMOS tube Q24 is the controlled end of the switch circuit, the drain electrode of the PMOS tube Q24 is the input end of the switch circuit, the source electrode of the PMOS tube Q24 and the negative electrode of the diode D1 are connected together to form the output end of the switch circuit, and the positive electrode of the diode D1 is grounded.

Preferably, the switching circuit further comprises an NMOS transistor Q25;

the grid electrode of the NMOS tube Q25 is the other controlled end of the switch circuit, the drain electrode of the NMOS tube Q25 is connected with the source electrode of the PMOS tube Q24, and the source electrode of the NMOS tube Q25 is grounded.

Preferably, the switch type lithium battery charging circuit further comprises a resistor R11, a resistor R12 and a capacitor C6;

one end of the resistor R11, the anode of the capacitor C6 and the other end of the inductor L are connected to the anode of the lithium battery in common, the other end of the resistor R11 and one end of the resistor R12 are connected to the second input end of the reference voltage sampling signal amplifying circuit in common, and the other end of the resistor R12, the cathode of the capacitor C6 and the cathode of the lithium battery are connected to the ground in common.

The invention also provides a switch type lithium battery charging chip without a current sampling resistor, which comprises the switch type lithium battery charging circuit.

Compared with the prior art, the invention has the beneficial effects that:

by arranging the prejudging circuit and the sampling holding circuit, the logic control circuit triggers the prejudging circuit to send a rising edge signal to the sampling holding circuit at the time of 0.5 times of the conduction time period of the switching circuit, triggers the sampling holding circuit to sample and hold a sampling voltage signal output by the current sampling circuit and output a current signal, converts the current signal into a voltage signal through the reference current sampling signal amplifying circuit and then compares the voltage signal with the reference voltage to generate an error voltage, so that the logic control circuit can adjust the duty ratio of the conduction time of the switching circuit according to the error voltage to control the switching circuit to perform constant-current charging on the lithium battery under the condition of not needing a sampling resistor.

Drawings

Fig. 1 is a block diagram of a basic structure of a switch-type lithium battery charging circuit without a current sampling resistor according to an embodiment of the present invention;

fig. 2 is a block diagram of a specific structure of a switch-type lithium battery charging circuit without a current sampling resistor according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of a look-ahead circuit provided by an embodiment of the present invention;

fig. 4 is a schematic circuit diagram of a current-to-voltage conversion unit, a sample-and-hold circuit, and a reference current sampling signal amplifying circuit according to an embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a reference current sampling signal amplifying circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.

As shown in fig. 1, the switching type lithium battery charging circuit without a current sampling resistor according to this embodiment includes a switching circuit 10, a current sampling circuit 20, an inductor L, a current-to-voltage circuit 30, a pre-judging circuit 40, a sample-and-hold circuit 50, a reference current sampling signal amplifying circuit 60, a constant current and constant voltage switching circuit 70, a PWM comparator 80, a logic control circuit 90, a reference voltage sampling signal amplifying circuit 00, and a compensation circuit 01.

The input end of the switch circuit 10 and the first input end of the current sampling circuit 20 are connected to an external power supply VIN, the output end of the switch circuit 10 and the second input end of the current sampling circuit 20 are connected to one end of an inductor L, and the other end of the inductor L is connected to the anode of the lithium battery BAT;

the output end of the current sampling circuit 20 is connected with the input end of the current-to-voltage conversion circuit 30;

the output end of the current-to-voltage circuit 30 is connected with the input end of the sampling hold circuit 50;

the output end of the sample-and-hold circuit 50 is connected to the first input end of the reference current sample signal amplifying circuit 60, the first logic signal input end of the sample-and-hold circuit 50 is connected to the logic signal output end of the prejudging circuit 40, the second logic signal input end of the sample-and-hold circuit 50 and the logic signal input end 40 of the prejudging circuit are connected to the logic signal output end of the logic control circuit 90 in common, and the enable input end of the sample-and-hold circuit 50 and the enable input end of the prejudging circuit 40 are connected to the enable output end of the logic control circuit 90 in common;

the input end of the prejudging circuit 40 is connected with an external power supply VIN, the output end of the prejudging circuit 40 is connected with the positive electrode of the lithium battery, and the reference voltage input end of the prejudging circuit 40 inputs reference voltage;

a second input end of the reference current sampling signal amplifying circuit 60 is connected with an external power supply to generate a reference voltage, and an output end of the reference current sampling signal amplifying circuit 60 is connected with a first input end of the constant-current constant-voltage switching circuit 70;

a first input end of the reference voltage sampling signal amplifying circuit 00 is connected with an external power supply to generate a reference voltage, a second input end of the reference voltage sampling signal amplifying circuit 00 is connected with the anode of the lithium battery BAT, and an output end of the reference voltage sampling signal amplifying circuit 00 is connected with a second input end of the constant-current and constant-voltage switching circuit 70;

the output end of the constant-current constant-voltage switching circuit 70 is connected with the positive input end of the PWM comparator 80, and the negative input end of the PWM comparator 80 is connected with the compensation circuit 01;

the output end of the PWM comparator 80 is connected to the input end of the logic control circuit 90, and the output end of the logic control circuit 90 is connected to the controlled end of the switch circuit 10;

in the present embodiment, the switch circuit 10 includes a PMOS transistor Q24 and a diode D1; the gate of the PMOS transistor Q24 is the controlled end of the switch circuit 10, the drain of the PMOS transistor Q24 is the input end of the switch circuit 10, the source of the PMOS transistor Q24 and the cathode of the diode D1 are connected together to form the output end of the switch circuit 10, and the anode of the diode D1 is grounded.

When the switch circuit 10 is turned on, the current sampling circuit 20 samples a sampling current signal flowing into the inductor L, and the current-to-voltage circuit 30 converts the sampling current signal into a sampling voltage signal and sends the sampling voltage signal to the sample-and-hold circuit 50;

at the time 0.5 times the conduction period of the switch circuit, the logic control circuit 90 triggers the prejudging circuit 40 to send a rising edge signal to the sample-and-hold circuit 50, so that the sample-and-hold circuit 50 samples and holds the sampled voltage signal and outputs a current signal to the reference current sampling signal amplifying circuit 60;

the reference current sampling signal amplifying circuit 60 converts the current signal into a voltage signal, compares the voltage signal with a reference voltage, and generates an error voltage, the error voltage is transmitted to the logic control circuit 90 through the constant current and constant voltage switching circuit 70 and the PWM comparator 80, and the logic control circuit 90 adjusts the duty ratio of the on-time of the switching circuit 10 according to the error voltage, so as to control the switching circuit 10 to output a constant charging current for charging the lithium battery BAT.

As shown in fig. 2, the switch-type lithium battery charging circuit without a current sampling resistor provided in this embodiment further includes a resistor R11, a resistor R12, and a capacitor C6; one end of the resistor R11, the anode of the capacitor C6 and the other end of the inductor L are connected to the anode of the lithium battery in a common mode, the other end of the resistor R11 and one end of the resistor R12 are connected to the second input end of the reference voltage sampling signal amplifying circuit 00 in a common mode, and the other end of the resistor R12, the cathode of the capacitor C6 and the cathode of the lithium battery BAT are connected to the ground in a common mode.

The switch circuit 10 further includes an NMOS transistor Q25, a gate of the NMOS transistor Q25 is another controlled end of the switch circuit 10, a drain of the NMOS transistor Q25 is connected to the source of the PMOS transistor Q24, and a source of the NMOS transistor Q25 is grounded.

The reference current sampling signal amplifying circuit 60 includes an error amplifier 61 and a reference voltage generating unit 62, wherein a positive input terminal of the error amplifier 61 is connected to an output terminal of the sample-and-hold circuit 50 as an input terminal of the reference current sampling signal amplifying circuit 60, and an output terminal of the error amplifier 61 is connected to an input terminal of the cross current constant voltage switching unit as an output terminal of the reference current sampling signal amplifying circuit 60; an output terminal of the reference voltage generating unit 62 is connected to an inverting input terminal of the error amplifier 61 for inputting an external power supply to generate a reference voltage.

The logic control circuit 90 includes a logic unit 91, a power tube driving unit 92 connected to an output terminal of the logic unit 91, and an oscillator 93 connected to the logic unit 91, wherein a first input terminal of the logic unit 91 is an input terminal of the logic control circuit 90, an enable terminal of the logic unit 91 is an enable output terminal of the logic control circuit 90, a logic signal terminal of the power tube driving unit 92 is a logic signal output terminal of the logic control circuit 90, and an output terminal of the oscillator 93 is connected to a second input terminal of the logic unit 91 to provide a clock signal for the logic unit 91.

The reference voltage sampling signal amplifying circuit 00 includes an error amplifier 001 and a reference voltage generating unit 002, wherein an inverting input terminal of the error amplifier 001 serves as a second input terminal of the reference voltage sampling signal amplifying circuit 00, and an output terminal of the error amplifier 001 serves as an output terminal of the reference voltage sampling signal amplifying circuit 00 and is connected to an input terminal of the cross current constant voltage switching unit; an output terminal of the reference voltage generating unit 002 is connected to a positive input terminal of the error amplifier 001 for inputting an external power source to generate a reference voltage.

The compensation circuit 01 integrates current sampling, slope compensation and bias current superposition functions.

As shown in fig. 3, in the present embodiment, the prejudging circuit 40 includes a first logic device 41, a NOT gate NOT1, a NOT gate NOT2, a NOR gate NOR1, a first amplifier 42, a second amplifier 43, a third amplifier 44, PMOS transistors Q1 to Q5, NMOS transistors Q6 to Q11, resistors R1 to R6, and a capacitor C1.

A signal input terminal D of the first Logic device 41 is connected to an external Power supply VDD, a clock signal terminal CLK of the first Logic device 41 is a Logic signal input terminal Power _ PMOS _ Turn _ ON _ Logic of the pre-judging circuit 40, a signal output terminal Q of the first Logic device 41 is connected to an input terminal of the NOT gate NOT1, and an enable terminal of the first Logic device 41

The output end of the NOR gate NOR1 is connected;

the source electrode of the PMOS tube Q1, the drain electrode of the PMOS tube Q2 and the drain electrode of the NMOS tube Q7 are connected in common, the drain electrode of the PMOS tube Q1 and the drain electrode of the NMOS tube Q6 are connected in common and then respectively connected with the positive electrode of the capacitor C1 and the positive input end of the first amplifier 42, and the negative electrode of the capacitor C1 is connected with the analog ground;

the grid electrode of the PMOS tube Q2, the grid electrode of the PMOS tube Q3, the drain electrode of the PMOS tube Q3 and the drain electrode of the NMOS tube Q9 are connected in common, and the source electrode of the PMOS tube Q2 and the source electrode of the PMOS tube Q3 are connected in common with an external power supply VDD;

the grid electrode of the NMOS tube Q9 is connected with the output end of the second amplifier 43, the source electrode of the NMOS tube Q9, the inverting input end of the second amplifier 43 and one end of the resistor R1 are connected together, and the other end of the resistor R1 is connected with the analog ground;

the grid electrode of the PMOS tube Q4, the grid electrode of the PMOS tube Q5, the drain electrode of the PMOS tube Q5 and the drain electrode of the NMOS tube Q11 are connected in common, and the source electrode of the PMOS tube Q4 and the source electrode of the PMOS tube Q5 are connected in common with an external power supply VDD;

the grid electrode of the NMOS tube Q11 is connected with the output end of the third amplifier 44, the source electrode of the NMOS tube Q11, the inverted input end of the third amplifier 44 and one end of the resistor R2 are connected together, and the other end of the resistor R2 is connected with the analog ground;

the first input end of the NOR gate NOR1 is connected with the output end of the NOT gate NOT2, the second input end of the NOR gate NOR1 and the output end of the first amplifier 42 are connected together to form a logic signal output end OUT of the prejudging circuit 40, and the input end of the NOT gate NOT2 is an Enable input end Enable of the prejudging circuit 40;

the inverting input terminal of the first amplifier 42 is the reference voltage input terminal VInitial of the pre-judging circuit 40;

the positive input end of the second amplifier 43 is connected to one end of the resistor R3 and one end of the resistor R4, the other end of the resistor R3 is the input end VIN of the prejudging circuit 40, the other end of the resistor R4 is grounded, and the resistances of the resistor R3 and the resistor R4 are equal;

the positive input end of the third amplifier 44 is connected to one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 is the output terminal VOUT of the prejudging circuit 40, and the other end of the resistor R6 is grounded, where the resistance of the resistor R6 is three times that of the resistor R5;

after the time 0.5 times of the conduction period of the switching circuit 10 and before the switching circuit 10 is conducted, the output end of the prejudging circuit 40 outputs current to discharge the capacitor C1, and the initial voltage of the capacitor C1 is equal to the reference voltage;

before the time from the conduction starting moment of the switch circuit 10 to the time 0.5 times of the conduction time period of the switch circuit 10, the input current of the input end of the prejudging circuit 40 charges the capacitor C1;

when the capacitor C1 is charged and the capacitor voltage is equal to the reference voltage again, the pre-decision circuit 40 determines that the time is 0.5 times the conduction period of the switch circuit 10, and the logic signal output end of the pre-decision circuit sends a rising edge signal to the sample-and-hold circuit 50.

As shown in fig. 4 or fig. 5, the current sampling circuit 20 is represented by an equivalent current source, an input end and an output end of the equivalent current source are respectively an input end and an output end of the current sampling circuit 20, the current sampling circuit 20 samples a current signal of an external power supply, and outputs a sampled current signal Isense to an input end of the current-to-voltage circuit 30.

As shown in fig. 4 or fig. 5, the current-to-voltage circuit 30 includes an NMOS transistor Q23, a drain of the NMOS transistor Q23 is connected to a gate to form an input terminal and an output terminal of the current-to-voltage circuit 30, and a source of the NMOS transistor Q23 is connected to a analog ground;

the drain of the NMOS transistor Q23 inputs the sampled current signal Isense and converts it into a sampled voltage signal, and the sampled voltage signal is output to the sample-and-hold circuit 50 through the gate thereof.

As shown in fig. 4, the sample-AND-hold circuit 50 includes a second logic device 51, NOT gates NOT3 to NOT8, an AND gate AND1, an inverted schmitt trigger ST2, a NOR gate NOR2, an NAND gate NAND1, a resistor R7, a resistor R8, capacitors C2 to C5, a PMOS transistor Q12, a PMOS transistor Q13, NMOS transistors Q14 to Q16, a switch S1, AND a switch S2;

a signal input end D of the second logic device 51 is connected to an external power supply VDD, a signal output end Q of the second logic device 51, an input end of the NOT gate NOT3, a gate of the PMOS transistor Q12, a gate of the NMOS transistor Q14, AND a first input end of the AND gate AND1 are commonly connected, a clock signal end CLK of the second logic device 51 is a first logic signal input end of the sample-AND-hold circuit 50, AND an enable end of the second logic device 51

The output end of the NOR gate NOR2 is connected, and the output end of the NOT gate NOT3 forms a sampling control end Sample of the sampling hold circuit 50;

the source electrode of the PMOS tube Q12 is connected with an external power supply VDD, and the drain electrode of the PMOS tube Q12, the input end of the reverse Schmitt trigger ST1, one end of the resistor R7 and the anode of the capacitor C2 are connected in common;

the drain electrode of the NMOS tube Q14 is connected with the other end of the resistor R7, and the source electrode of the NMOS tube 14 and the negative electrode of the capacitor C2 are connected to the analog ground in common;

the second input end of the AND gate AND1 is connected with the output end of the NOT gate NOT4, the output end of the AND gate AND1 is connected with the input end of the NOT gate NOT5, the output end of the NOT gate NOT5 forms the holding control end Charge of the sample holding circuit 50, AND the input end of the NOT gate NOT4 is connected with the output end of the inverse schmitt trigger ST 1;

a first input end of the NOR gate NOR2 is connected with an output end of the NOT gate NOT6, a second input end of the NOR gate NOR2 is connected with an output end of the NOT gate NOT7, and an input end of the NOT gate NOT7 is an Enable input end Enable of the sample hold circuit 50;

the input end of the NOT gate NOT6 is connected with the output end of the NAND gate NAND1, the first input end of the NAND gate NAND1 is connected with the output end of the NOT gate NOT8, and the second input end of the NAND gate NAND', the gate of the PMOS transistor Q13 and the gate of the NMOS transistor Q15 are connected in common to form a second Logic signal input end Power _ PMOS _ Turn _ ON _ Logic of the sample-and-hold circuit 50;

the input end of the NOT8 is connected with the output end of the Schmitt trigger ST2, the input end of the Schmitt trigger ST2, the anode of the capacitor C3, one end of the resistor R8 and the drain of the PMOS tube Q13 are connected together, and the source of the PMOS tube Q13 is connected with an external power supply;

one end of the switch S1 is an input end of the sample-and-hold circuit 50, and the other end of the switch S1, the anode of the capacitor C4 and one end of the switch S2 are connected in common;

the other end of the switch S2, the positive electrode of the capacitor C5 and the grid electrode of the NMOS tube Q16 are connected in common, the drain electrode of the NMOS tube Q16 is the output end of the sample-hold circuit 50, and the negative electrode of the capacitor C4, the negative electrode of the capacitor C5 and the source electrode of the NMOS tube Q16 are connected in common to an analog ground;

at the time of starting the switch circuit 10 to be turned on, the Sample-and-hold circuit 50 receives the rising edge signal of the pre-judging circuit 40, the Sample control terminal Sample triggers the switch S1 to be closed, the switch S2 is turned off, and the input terminal of the Sample-and-hold circuit 50 inputs the sampling voltage signal output by the current-to-voltage circuit 30 to charge the capacitor C4;

at the time 0.5 times the conduction period of the switch circuit 10, the sampling control terminal Sample triggers the switch S1 to turn off, and at this time, the capacitor C4 stores the sampling current signal corresponding to the time 0.5 times;

after the time 0.5 times the conduction period of the switch circuit 10 and before the switch circuit 10 is turned on, the Charge-holding control end trigger switch S2 is closed to Charge the capacitor C4 to the capacitor C5, and when the voltage of the capacitor C4 is equal to the voltage of the capacitor C5, the Charge-holding control end trigger switch S2 is opened to store the sampling current signal corresponding to the time 0.5 times in the capacitor C5, and the sampling current signal is output to the reference current sampling signal amplifying circuit 60 through the NMOS transistor Q16.

As shown in fig. 4, the reference current sampling signal amplification circuit 60 includes an error amplifier 61 and a reference voltage generation unit 62; the reference voltage generating unit 62 includes a second equivalent current source 621, an NMOS transistor Q21, an NMOS transistor Q22, a resistor R9, and a resistor R10;

the positive input end of the error amplifier 61 and one end of the resistor R9 are connected in common to form a first input end of the reference current sampling signal amplifying circuit 60, the negative input end of the error amplifier 61 and one end of the resistor R10 and the drain electrode of the NMOS tube Q21 are connected in common, and the output end of the error amplifier 61 is the output end of the reference current sampling signal amplifying circuit 60;

the input end of the second equivalent current source 621, the other end of the resistor R9 and the other end of the resistor R10 are connected in common to form a second input end of the reference current sampling signal amplifying circuit 60, the output end of the second equivalent current source 621, the drain electrode of the NMOS transistor Q21, the gate electrode of the NMOS transistor Q21 and the gate electrode of the NMOS transistor Q22 are connected in common, and the source electrode of the NMOS transistor Q21 and the source electrode of the NMOS transistor Q22 are connected in common to the analog ground;

the second equivalent current source 621 generates a reference current flowing through the resistor R10, so that a reference voltage generated on the resistor R10 is output to the inverting input terminal of the error amplifier, the sampled current signal output by the sample-and-hold circuit is converted into a voltage signal through the resistor R9, and the error amplifier amplifies the difference between the voltage signal and the reference voltage, thereby generating an error voltage and outputting the error voltage to the constant-current constant-voltage switching circuit.

As shown in fig. 5, in the present embodiment, the reference current sampling signal amplifying circuit 60 includes a reference current generating unit composed of a first equivalent current source 63, an NMOS transistor Q17, an NMOS transistor Q18, a PMOS transistor Q19, and a PMOS transistor Q20;

the input end of the first equivalent current source 63, the source electrode of the PMOS tube Q19 and the source electrode of the PMOS tube Q20 are connected in common to form the input end of the reference current sampling signal amplifying circuit 60, the output end of the first equivalent current source 63, the drain electrode of the NMOS tube Q17, the grid electrode of the NMOS tube Q17 and the grid electrode of the NMOS tube Q18 are connected in common, and the source electrode of the NMOS tube Q17 and the source electrode of the NMOS tube Q18 are connected in common to the analog ground;

the grid electrode of the PMOS tube Q19 and the grid electrode of the PMOS tube Q20, the drain electrode of the PMOS tube Q19 and the drain electrode of the NMOS tube Q18 are connected in common, and the drain electrode of the PMOS tube Q20 is a first input end and an output end of the reference current sampling signal amplifying circuit 60;

the first equivalent current source 63 generates a reference current flowing through the PMOS transistor Q20, and the reference current and the sampled current signal output from the sample-and-hold circuit 50 form an error voltage through an equivalent resistance between the PMOS transistor Q20 and the NMOS transistor Q16 and output to the constant current and constant voltage switching circuit 70.

The embodiment of the invention also provides a switch type lithium battery charging chip without a current sampling resistor, which comprises the switch type lithium battery charging circuit. In a specific application, the switch circuit may be disposed outside the switch type lithium battery charging chip, or may be integrated inside the switch type lithium battery charging chip.

The above description is intended to be illustrative of the preferred embodiment of the present invention and should not be taken as limiting the invention, but rather, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Claims

1. A switch type lithium battery charging circuit without a current sampling resistor is characterized by comprising a switch circuit, a current sampling circuit, an inductor L, a current conversion voltage circuit, a pre-judging circuit, a sampling holding circuit, a reference current sampling signal amplifying circuit, a constant current and constant voltage switching circuit, a PWM (pulse width modulation) comparator, a logic control circuit, a reference voltage sampling signal amplifying circuit and a compensating circuit;

the input end of the switch circuit and the first input end of the current sampling circuit are connected to an external power supply in a common way, the output end of the switch circuit and the second input end of the current sampling circuit are connected to one end of an inductor L in a common way, and the other end of the inductor L is connected to the anode of the lithium battery;

the output end of the constant-current and constant-voltage switching circuit is connected with the positive input end of the PWM comparator, and the negative input end of the PWM comparator is connected with the compensation circuit;

at the time 0.5 times of the conduction time of the switch circuit, the logic control circuit triggers the pre-judging circuit to send a rising edge signal to the sampling and holding circuit, so that the sampling and holding circuit samples and holds the sampling voltage signal and outputs a current signal to the reference current sampling signal amplifying circuit;

the reference current sampling signal amplifying circuit converts the current signal into a voltage signal and compares the voltage signal with the reference voltage to generate an error voltage, the error voltage is transmitted to the logic control circuit through the constant-current constant-voltage switching circuit and the PWM comparator, and the logic control circuit adjusts the duty ratio of the on-time of the switching circuit according to the error voltage so as to control the switching circuit to output a constant charging current to charge the lithium battery;

the current-to-voltage circuit comprises an NMOS (N-channel metal oxide semiconductor) tube Q23, the drain electrode of the NMOS tube Q23 is connected with the grid electrode to form the input end and the output end of the current-to-voltage circuit, and the source electrode of the NMOS tube Q23 is connected with an analog ground;

the drain electrode of the NMOS tube Q23 inputs the sampling current signal, converts the sampling current signal into a sampling voltage signal and outputs the sampling voltage signal to the sampling hold circuit through the grid electrode of the NMOS tube Q23;

the switch type lithium battery charging circuit further comprises a resistor R11, a resistor R12 and a capacitor C6;

2. The switching type lithium battery charging circuit without the current sampling resistor as claimed in claim 1, wherein the prejudgment circuit comprises a first logic device, a NOT gate NOT1, a NOT gate NOT2, a NOR gate NOR1, a first amplifier, a second amplifier, a third amplifier, PMOS transistors Q1-Q5, NMOS transistors Q6-Q11, resistors R1-R6 and a capacitor C1;

the grid electrode of the NMOS tube Q7, the grid electrode of the NMOS tube Q8, the grid electrode of the NMOS tube Q10 and the drain electrode of the PMOS tube Q4 are connected in common, and the source electrode of the NMOS tube Q7, the source electrode of the NMOS tube Q8 and the source electrode of the NMOS tube Q10 are all connected with analog ground;

the first input end of the NOR gate NOR1 is connected with the output end of the NOT2, the second input end of the NOR gate NOR1 and the output end of the first amplifier are connected together to form a logic signal output end of the pre-judging circuit, and the input end of the NOT2 is the enabling input end of the pre-judging circuit;

3. The switching type lithium battery charging circuit without the current sampling resistor as claimed in claim 1, wherein the sample hold circuit comprises a second logic device, NOT gates NOT3 to NOT8, an AND gate AND1, an inverse Schmitt trigger ST2, an NOR gate NOR2, an NAND gate NAND1, a resistor R7, a resistor R8, capacitors C2 to C5, a PMOS transistor Q12, a PMOS transistor Q13, NMOS transistors Q14 to Q16, a switch S1 AND a switch S2;

the drain electrode of the NMOS tube 14 is connected with the other end of the resistor R7, and the source electrode of the NMOS tube 14 and the negative electrode of the capacitor C2 are connected to the analog ground in common;

the input end of the NOT6 is connected with the output end of the NAND gate NAND1, the first input end of the NAND gate NAND1 is connected with the output end of the NOT8, and the second input end of the NAND gate NAND', the grid of the PMOS tube Q13 and the grid of the NMOS tube Q15 are connected with the second logic signal input end of the sample-and-hold circuit;

at the starting moment of the switch circuit being turned on, the sample-and-hold circuit receives the rising edge signal of the prejudging circuit, the sampling control end triggers the switch S1 to be closed, the switch S2 is opened at the moment, and the input end of the sample-and-hold circuit inputs the sampling voltage signal output by the current-to-voltage conversion circuit to charge the capacitor C4;

4. The switched-mode lithium battery charging circuit without a current sampling resistor as claimed in claim 3, wherein the reference current sampling signal amplifying circuit comprises a reference current generating unit consisting of a first equivalent current source, an NMOS transistor Q17, an NMOS transistor Q18, a PMOS transistor Q19 and a PMOS transistor Q20;

5. The switched-mode lithium battery charging circuit without a current sampling resistor as claimed in claim 1, wherein the reference current sampling signal amplifying circuit comprises an error amplifier and a reference voltage generating unit; the reference voltage generating unit comprises a second equivalent current source, an NMOS tube Q21, an NMOS tube Q22, a resistor R9 and a resistor R10;

the positive input end of the error amplifier and one end of the resistor R9 are connected together to form a first input end of the reference current sampling signal amplifying circuit, the negative input end of the error amplifier and one end of the resistor R10 are connected together with the drain electrode of the NMOS tube Q21, and the output end of the error amplifier is the output end of the reference current sampling signal amplifying circuit;

the second equivalent current source generates a reference current which flows through a resistor R10, so that a reference voltage generated on the resistor R10 is output to the reverse input end of the error amplifier, a sampling current signal output by the sampling holding circuit is converted into a voltage signal through a resistor R9, and the error amplifier amplifies the difference between the voltage signal and the reference voltage, so that an error voltage is generated and output to the constant-current and constant-voltage switching circuit.

6. The switched-mode lithium-ion battery charging circuit without a current-sampling resistor of claim 1, wherein the switching circuit comprises a PMOS transistor Q24 and a diode D1;

7. The switched-mode lithium-ion battery charging circuit without a current-sampling resistor of claim 6, wherein the switching circuit further comprises an NMOS transistor Q25;

8. A switch type lithium battery charging chip without a current sampling resistor, which is characterized by comprising the switch type lithium battery charging circuit as claimed in any one of claims 1 to 7.