CN107463759A - The simulating, verifying device and emulation verification method of a kind of timer - Google Patents
The simulating, verifying device and emulation verification method of a kind of timer Download PDFInfo
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Abstract
The embodiment of the invention discloses the simulating, verifying device and emulation verification method of a kind of timer.Wherein, the simulating, verifying device of the timer includes：Register configuration component and assertion verification component；Register configuration component is used to generate the first register of configuration Timer module and/or the configuration data of the second register；Assertion verification component includes register and checks module, register checks that module includes and the first register and/or the one-to-one register authentication unit of the second register, any register authentication unit is used to contrast data of the register data with corresponding first register or the second register, by comparing result, the correctness of the first register of inspection or the second register configuration.The technical scheme of the embodiment of the present invention, which can be realized, to be checked the correctness of data caused by Timer module bosom link.
Description
Technical field
The present invention relates to the simulating, verifying device and simulating, verifying of technical field of integrated circuits, more particularly to a kind of timer
Method.
Background technology
Timer is the module of a kind of Dose times in MCU (Microcontroller Unit, micro-control unit).
MCU can realize the generation and control of many complex time sequences, and timer is actually into the generation and control of this complex time sequence
The key modules of function.Timer can configure internal control registers on the basis of common timing according to user's request,
Numerous controllable waveforms are produced, or realize the control to numerous peripheral hardwares.Timer from simple clocking capability, is developed into multiple
Miscellaneous waveform generating module, and as the critical function in MCU practical applications.
When developing a kind of timer with specific function, typically retouched by hardware description language (verilog or VHDL)
The Timer module of the specific function is stated, to simulate real timer.By building verification environment, to verify Timer module
Correctness.In common verification environment, typically have excitation produce component, expected data formation component, receiver assembly,
Data comparison component and coverage rate collection assembly.Wherein, excitation produces component by randomised way, produces swashing used in test
Signal data is encouraged, drives Timer module and expected data formation component.Expected data formation component according to pumping signal data,
The desired value of output data is produced based on parameter configuration.Receiver assembly receives the final output data of Timer module, passes through
After packing processing, comparing component is sent to.Comparing component is sent out according to expected data formation component and receiver assembly
The data sent, generate comparison result.Coverage rate collection assembly collects test coverage, produces test coverage data.Generally
Expected data formation component realizes that poor real can only be to timing by high-level language such as Systemverilog or C language
The correctness of the final output data of device module checked, can not be to data caused by Timer module bosom link
Correctness is checked.
The content of the invention
The embodiment of the present invention provides a kind of the simulating, verifying device and emulation verification method of timer, to realize to timer
The correctness of data is checked caused by inside modules intermediate link, and then fast positioning errors present, is greatly shortened
The purpose of debug time.
In a first aspect, the embodiments of the invention provide a kind of simulating, verifying device of timer, wherein,
Timer module, including multiple input capture passages, multiple outputs produce passage and register submodule；
Wherein, register submodule includes：Multiple first registers for being correspondingly arranged with each input capture passage and with it is each
Output produces multiple second registers that passage is correspondingly arranged；
Any input capture passage includes multiple first working devices, and multiple first working devices are according to the first default connected mode
Carry out data transmission, according to the data of the first register corresponding with the first working device, determine the mode of operation of the first working device,
To realize default input capture function；
Any output, which produces passage, includes multiple second working devices, and multiple second working devices are according to the second default connected mode
Carry out data transmission, according to the data of the second register corresponding with the second working device, determine the mode of operation of the second working device,
To realize that default output produces function；
Simulating, verifying device includes：Register configuration component and assertion verification component；
Register configuration component, for generating the configuration data of the first register of configuration and/or the second register；
Timer module, for according to configuration data, configuring the data of the first register and/or the second register；
Assertion verification component, including register check module, wherein, register checks that module includes and the first register
And/or the second one-to-one register authentication unit of register, any register authentication unit are used for according to register configuration
The configuration data of component generation, generates register data, and contrast register data is deposited with corresponding first register or second
The data of device, if comparing result is identical, verify that the first register or the second register configuration are correct, if comparing result is not
It is identical, then verify the first register or the second register configuration mistake.
Second aspect, the embodiment of the present invention additionally provide a kind of emulation verification method of timer, based on of the invention any
The simulating, verifying device for the timer that embodiment provides realizes that this method includes：
The configuration data that Timer module generates according to register configuration component, configure the first register and/or second post
The data of storage；
The data output of first register and/or the second register to register is checked module by Timer module.
The third aspect, the embodiment of the present invention additionally provide a kind of emulation verification method of timer, based on of the invention any
The simulating, verifying device for the timer that embodiment provides realizes that this method includes：
Any register authentication unit generates register data according to the configuration data of register configuration component；
Assertion verification component introduces the data of each first register and/or the second register of Timer module；
Any register authentication unit contrasts data of the register data with corresponding first register or the second register；
If comparing result is identical, verify that the first register or the second register configuration are correct；
If comparing result verifies the first register or the second register configuration mistake to differ.
The technical scheme of the embodiment of the present invention generates the first register of configuration and the second deposit by register configuration component
The configuration data of device, the configuration number that any register authentication unit in assertion verification component generates according to register configuration component
According to, generation register data, the first register or the second register of contrast register data and corresponding Timer module
Data, if comparing result is identical, verify that the first register or the second register configuration are correct, if comparing result is not phase
Together, then the first register or the second register configuration mistake are verified, to realize to the register of Timer module inside first and the
The correctness of the data of two register configurations is checked, with fast positioning errors present, can greatly shorten the mesh of debug time
's.
Brief description of the drawings
Fig. 1 is a kind of structural representation of the simulating, verifying device of timer provided in an embodiment of the present invention；
Fig. 2 is a kind of structural representation of the input capture passage of Timer module provided in an embodiment of the present invention；
Fig. 3 is that a kind of output of Timer module provided in an embodiment of the present invention produces the structural representation of passage；
Fig. 4 is the structural representation of the simulating, verifying device of another timer provided in an embodiment of the present invention；
Fig. 5 is the structural representation of the simulating, verifying device of another timer provided in an embodiment of the present invention；
Fig. 6 is a kind of flow chart of the emulation verification method of timer provided in an embodiment of the present invention；
Fig. 7 is the flow chart of the emulation verification method of another timer provided in an embodiment of the present invention；
Fig. 8 is the flow chart of the emulation verification method of another timer provided in an embodiment of the present invention；
Fig. 9 is a kind of emulation verification method of the timer performed by assertion verification component provided in an embodiment of the present invention
Flow chart；
Figure 10 is the simulating, verifying side of another timer performed by assertion verification component provided in an embodiment of the present invention
The flow chart of method；
Figure 11 is the simulating, verifying side of another timer performed by assertion verification component provided in an embodiment of the present invention
The flow chart of method.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that in order to just
Part related to the present invention rather than entire infrastructure are illustrate only in description, accompanying drawing.
The embodiment of the present invention provides a kind of simulating, verifying device of timer.Fig. 1 is one kind provided in an embodiment of the present invention
The structural representation of the simulating, verifying device of timer, the simulating, verifying device of the timer can be realized by software mode.Its
In, Timer module can be realized by hardware description language, such as VHDL language and verilog language.As shown in figure 1, timer
Module 10 is used to simulate real timer, has and true timer identical behavior；Simulating, verifying device 20 is used to check
The correctness of the Timer module 10.If verifying, the Timer module is correct, can be used for the code for realizing the Timer module
Produce real timer.
As shown in figure 1, Timer module 10, including multiple input capture passages 110, multiple outputs produce the He of passage 120
Register submodule 130.
Wherein, register submodule 130 includes：Multiple first registers being correspondingly arranged with each input capture passage 110
111, multiple second registers 121 being correspondingly arranged with each output generation passage 120.
Any input capture passage 110 includes multiple first working devices 112, and multiple first working devices 112 are pre- according to first
If connected mode carries out data transmission, according to the data with 112 corresponding first register 111 of the first working device, first is determined
The mode of operation of working device 112, to realize default input capture function, the input signal even captured is default input
Pumping signal, then final output first encourages or first interrupts.Default input signal can be the pulse letter of default pulsewidth
Number, the duration for presetting pulsewidth can be the integral multiple in the cycle of clock signal.
Any output, which produces passage 120, includes multiple second working devices 122, and multiple second working devices 122 are pre- according to second
If connected mode carries out data transmission, according to the data with 122 corresponding second register 121 of the second working device, second is determined
The mode of operation of working device 122, to realize that default output produces function, i.e., according to the data of the second register, final output the
Two excitations or the second interruption.
It should be noted that the major function of timer is divided into input capture and output produces.Input capture is i.e. according to the
The configuration of one register, external data signal (i.e. external drive) is obtained, external data signal is measured, and then produced and swash
Encourage or interrupt.Output is produced i.e. according to the configuration of the second register, produces various controllable output signals, as excitation or in
It is disconnected.Wherein, the embodiment of the present invention is not limited the number of input capture passage and the number of output generation passage, can be one
It is individual or multiple.Wherein, between the first working device of adjacent connection, the signal output part of previous first working device and latter first work
Make the signal input part connection of device；Between the second adjacent working device, the signal output part of previous second working device and latter the
The signal input part connection of two working devices.Wherein, the working device of part first also includes input end of clock, believes for input clock
Number.The working device of part second also includes input end of clock, for input clock signal.
Optionally, the first working device includes following at least one：Synchronizer, marginal detector, edge selector, path choosing
Select device, Clock dividers, the first master timer, capture register and input frequency divider.
Exemplary, lead to as shown in Fig. 2 Fig. 2 is a kind of input capture of Timer module provided in an embodiment of the present invention
The structural representation in road, for convenience of illustrate, Fig. 2 it is exemplary draw input capture passage all the way.The signal input of synchronizer 60
End introduces input signal and clock signal, and input signal is synchronized into intra clock domain；The letter of synchronizer 60
Number output end is connected with the signal input part of wave filter 61, and wave filter 61 is used to filter out unwanted noise jamming；Wave filter 61
Signal output part be connected with the signal input part of marginal detector 62, the signal output part of marginal detector 62 selects with edge
The signal input part connection of device 63, marginal detector 62 are used for the rising edge and trailing edge for selecting input signal, for
Edge selector 63 selects；The signal output part of edge selector 63 is connected with the signal input part of way selectors 64, edge
Selector 63 is used to export the first signal to way selectors 64；The signal output part of way selectors 64 and input frequency divider 65
Signal input part connection, other input capture passages and/or output produce passage also can caused by corresponding signal (such as the
Binary signal and other signals), select wherein all the way, into input frequency divider 65, to carry out scaling down processing by way selectors 64.
Caused signal can generate capture interrupt identification after inputting the signal output part and frequency dividing of frequency divider 65, and cause capture register
66 obtain the value of master timer 67.The signal input part of Clock dividers 68 introduces clock signal, and carries out scaling down processing；When
The signal output part of clock frequency divider 68 is connected with the signal input part of the first master timer 67.Interrupt identification is captured to interrupt with capture
It is enabled to pass through one and door 69, capture interrupt signal output is produced, this signal can pass through an OR gate 70 with other signals, produce
The interrupt output of whole Timer module.Clock signal is the work clock of Timer module.
Wherein, synchronizer 60 includes the first trigger 71 and the second trigger 72, the first input end of the first trigger 71
D1 is connected with the signal input part of synchronizer 60, and the second input of the first trigger 71 connects with the input end of clock of synchronizer 60
Connecing, the output end Q1 of the first trigger 71 is connected with the first input end D2 of the second trigger 72, and the second of the second trigger 72
Input is connected with the input end of clock of synchronizer 60, the output end Q2 of the second trigger 72 and the signal output part of synchronizer 60
Connection.Marginal detector 62 includes the 3rd trigger 73, the first gate circuit 74 and the second gate circuit 75, and the of the 3rd trigger 73
One input D3, the first input end of the first gate circuit 74 and the second gate circuit 75 the second input, and Edge check
The signal input part connection of device 62, the second input of the 3rd trigger 73 are connected with the input end of clock of marginal detector 62,
Second input of the first gate circuit 74, and the first input end of the second gate circuit 75, the output with the 3rd trigger 73
Q3 connections are held, the output end of the first gate circuit 74 is connected with the first signal output part of marginal detector 62, the second gate circuit 75
Output end be connected with the secondary signal output end of marginal detector 62, wherein, the second input of the first gate circuit 74 is anti-
Phase input, signal can be inputted and carry out the first gate circuit 74 of anti-phase rear input, the first gate circuit 74 is used for the second input
The signal of end input carry out it is anti-phase after, by signal and the second input of first input end input it is anti-phase after signal carry out and
Exported after effect；Second input of the second gate circuit 75 is inverting input, can be inputted signal and carry out anti-phase rear input,
Second gate circuit 75 be used for by the second input input signal carry out it is anti-phase after, by first input end input signal and second
Input it is anti-phase after signal carry out with act on after export.
Optionally, the second working device includes following at least one：Export comparand register, the second master timer, output ratio
Compared with device, output mode controller, output delay controller and output polarity selector.
Exemplary, as shown in figure 3, the output that Fig. 3 is a kind of Timer module provided in an embodiment of the present invention is produced and led to
The structural representation in road, for convenience of illustrating, the output all the way that draws exemplary Fig. 3 produces passage.Wherein, comparand register is exported
76, for receiving central processing unit (Central Processing Unit, CPU) configuration data.
Second master timer 77, the first signal input part receive enabling signal, and secondary signal input receives reset signal,
For under conditions of preset configuration pattern is met, starting timing or clearing.
Output comparator 78, the first signal input part with and output comparand register 76 signal output part be connected, second
Signal input part is connected with the signal output part of the second master timer 77, for according to output comparand register 76 value CRR and
The value CNT of second master timer 77, determines output mode, exemplary, works as CNT>During CCR, the first letter of output comparator 78
Number output end output high level, secondary signal output end and the 3rd signal output part export low level；As CNT==CCR,
The secondary signal output end output high level of output comparator 78, the first signal output part and the 3rd signal output part export low
Level；Work as CNT<During CCR, the 3rd signal output part output high level of output comparator 78, the first signal output part and second
Signal output part exports low level.
Output mode controller 79, the first signal input part, secondary signal input and the 3rd signal input part respectively with
First signal output part of output comparator 78, secondary signal output end connect with the 3rd signal output part, for according to first
The input signal of signal input part, secondary signal input and the 3rd signal input part and the Working mould of output mode controller 79
Formula, corresponding output is produced, it is exemplary, if the mode of operation of output mode controller 79 is the first mode of operation, work as output
When first signal input part of mode controller 79 is high level or secondary signal input is high level, the first signal output
End output high level, secondary signal output end output low level；When the 3rd signal input part of output mode controller 79 is height
During level, secondary signal output end output high level, the first signal output part output low level.If output mode controller 79
Mode of operation is the second mode of operation, when the first signal input part of output mode controller 79 is high level or secondary signal
When input is high level, the first signal output part output low level, secondary signal output end output high level；Work as output mode
When 3rd signal input part of controller 79 is high level, secondary signal output end exports high level, and the first signal output part is defeated
Go out low level.It is stop mode if the mode of operation of output mode controller 79 is the 3rd mode of operation, the first signal output part
Export low level, secondary signal output end output low level.
Delay controller 80 is exported, the first signal output part of the first signal input part and output mode controller 79 connects
Connect, secondary signal input is connected with the secondary signal output end of output mode controller 79, for the first signal input part
Input signal carry out time-lag action, and export to the first signal output part, and the input signal to secondary signal input
Time-lag action is carried out, and is exported to secondary signal output end.The mode of operation of output delay controller 80 includes：Rising edge is delayed
And/or trailing edge delay.
Output polarity selector 81, the first signal output part of the first signal input part and output delay controller 80 connect
Connect, secondary signal input is connected with exporting the secondary signal output end of delay controller 80, for the first signal input part
Input signal carry out polarity effect, and export corresponding to second excitation or second interrupt to the first signal output part, to second
The input signal of signal input part carries out polarity effect, and the second excitation corresponding to output or the second interruption to secondary signal export
End.The mode of operation of output polarity selector 81 includes：Reversing or polarity are constant.
It should be noted that the first working device can have corresponding first register, also can be without corresponding first deposit
Device, and if the first working device have corresponding to the first register, the number of corresponding first register can be one or more.
For example, synchronizer does not have corresponding first register；Marginal detector does not have corresponding first register；Select at edge
Selecting device has corresponding first register, for the data of the first register corresponding to, determines the work of edge selector
Operation mode, it is to select rising edge as trigger signal, or selection trailing edge is as trigger signal；Channel to channel adapter has therewith
Corresponding first register.Second working device can have corresponding second register, can also not have corresponding second register, and
If the second working device has corresponding second register, the number of corresponding second register can be one or more.First
Working device connects with corresponding first register, and the second working device connects with corresponding second register.
Simulating, verifying device 20 includes：Register configuration component 30 and assertion verification component 40.Wherein, assertion verification component
It can be realized by assertion language.
Wherein, register configuration component 30, for generating the configuration of the first register 111 of configuration and the second register 121
Data.Timer module 10, it is connected with register configuration component 30, for introducing the configuration number of the generation of register configuration component 30
According to according to configuration data, the data of the first register 111 of configuration and the second register 121, can be stored in configuration data
In the corresponding register 121 of first register 111 or second.Assertion verification component 40, including register check module 410, its
In, it is single with the first register 111 and the 121 one-to-one register checking of the second register that register checks that module 410 includes
Member 411, any register authentication unit 411, is connected with register configuration component 30, with corresponding first register 111 or the
Two registers 121 connect, for according to configuration data, generating register data, can be configuration data is stored in corresponding to
In register authentication unit 411, data of the register data with the corresponding register 121 of first register 111 or second are contrasted,
If comparing result is identical, verify that the first register 111 or the second register 121 configure correctly, if comparing result is not phase
Together, then the first register 111 or the configuration error of the second register 121 are verified, and to the first register 111 or the of current check
Two registers 121 carry out the processing that reports an error.
It should be noted that the configuration of register configuration component generation the first register 111 of configuration and the second register 121
Data, it is the register data that true timer truly uses.Assertion verification component can be checked in Timer module in real time
The correctness of portion's signal.Assertion verification component can't go really to realize the trifling function of Timer module, but can pass through
Check that the internal signal of Timer module checks whether the method that timer is realized in itself is correct.Assertion verification component owns
Signal is all input signal, does not influence the normal work of Timer module.Can be with ease in use based on the checking language asserted
Language construction establishes accurate temporal expression.By checking whether these expression formulas occur, work(can be easily carried out
The inspection that can be covered, and this coverage rate analysis is to be directed to a sequence of events or the whole transmission across multiple timing cycles
Process, so higher than the abstraction hierarchy of traditional covering driving checking.Asserting can be carried out accurately to the expected behavior of design
Description.Assertion verification belongs to one kind of formal verification, and the work asserted does not need special flow, in the normal work of tested module
Among the process of work, assert and start working.After suitable condition, which is asserted checking assembly, to be captured, that is, start to check work
Make, and inspection result can be produced immediately, inspection result includes comparing correctness, sequential relationship correctness, and breaks
Say the information such as frequency.
The technical scheme of the present embodiment generates the first register of configuration and second register by register configuration component
Configuration data, the configuration data that any register authentication unit in assertion verification component generates according to register configuration component,
Register data is generated, contrasts register data and the first register of corresponding Timer module or the number of the second register
According to, if comparing result is identical, verify that the first register or the second register configuration are correct, if comparing result is to differ,
The first register or the second register configuration mistake are then verified, the register of Timer module inside first and second are posted with realizing
The correctness of the data configuration of storage is checked, with fast positioning errors present, can greatly shorten the purpose of debug time.
The embodiment of the present invention provides the simulating, verifying device of another timer.Fig. 4 for it is provided in an embodiment of the present invention again
A kind of structural representation of the simulating, verifying device of timer, as shown in figure 4, on the basis of above-described embodiment, simulating, verifying
Device 20 also includes：Excitation produces component 50, and for generating default excited data, the input as input capture passage 110 swashs
Encourage signal；Assertion verification component 40 also includes：Input capture authentication module 420.
Input capture authentication module 420 includes：It is any with 112 one-to-one first authentication unit 421 of the first working device
First authentication unit 421, connect with the signal input part and signal output part of corresponding first working device 112, posted with corresponding
Storage authentication unit 411 connects, for the first input data (signal of signal input part input) according to the first working device 112
And/or corresponding register data, determine the first checking output data, the checking output data of contrast first and the first working device
112 the first output data (signal of signal output part output), if comparing result is identical, verifies the first working device 112
Function it is correct, and count and first assert number；If comparing result verifies that the function of the first working device 112 is wrong to differ
By mistake, and the processing that reports an error is carried out to the first working device 112 of current check.
Wherein, first assert number according to what corresponding first authentication unit counted, determine the first authentication unit whether by
Performed, and then determine whether the first working device was performed.If the first of corresponding first authentication unit statistics asserts number
It is zero, it is determined that the first authentication unit was not performed, and then determined that the first working device was not performed, i.e. first working device
Function do not cover.If the first of corresponding first authentication unit statistics asserts that number is more than zero, it is determined that the first checking is single
Member was performed, and then determined that the first working device was performed, i.e. the function of first working device is capped.
Exemplary, with continued reference to Fig. 2, synchronizer is used to input signal be synchronized to clock zone, in order to avoid Asia
Stable state is, it is necessary to use the data after the bat of clock signal two.So the output signal of synchronizer must clap with input signal two
Data before are consistent.If synchronizer goes wrong, before its first output data is not clapped with input signal two
Data are consistent, then the capability error for verifying synchronizer is quoted mistake by the first authentication unit corresponding with synchronizer.If in addition,
Input signal does not drive change, such as input signal to be consistently equal to 0, then the first checking corresponding with synchronizer
Unit will not perform, then the first of corresponding first authentication unit statistics asserts that number will be zero, so coverage rate detector
The warning asserted code and be not performed of the first authentication unit corresponding with synchronizer will be quoted (i.e. function does not cover)；
If the first of corresponding first authentication unit statistics asserts that number is more than zero, function is capped.Thus, collecting function coverage rate
Function very easily realized.Marginal detector is used for the rising edge and trailing edge for detecting the input signal of signal input part
When, signal output part produces corresponding single pulse signal (equivalent to the first checking output data).If the input of marginal detector
After the rising edge of signal arrives, the signal output part of marginal detector does not produce corresponding single pulse signal, its first output
Data are not in the subsequent time for detecting rising edge and arriving, and export single pulse signal, then and corresponding with marginal detector first
Authentication unit will verify the capability error of marginal detector；After if the rising edge of the input signal of marginal detector arrives, side
Along detector signal output part produce corresponding to single pulse signal, then the first authentication unit corresponding with marginal detector will test
The function of card marginal detector is correct, i.e., sequential relationship is correct.Wherein, each inspection module in assertion verification component is to timing
What the various output datas of device module were checked in real time, and start to from Timer module during the whole service of stopping all
Carry out.
The technical scheme of the present embodiment provides the simulating, verifying device of another timer, and the embodiment is in above-mentioned implementation
On the basis of example, by any first authentication unit, connect with the signal input part and signal output part of corresponding first working device
Connect, connected with corresponding register authentication unit, for the first input data according to the first working device and/or corresponding deposit
Device data, the first output data of the first checking output data, the checking output data of contrast first and the first working device is determined, if
Comparing result is identical, then verifies that the function of the first working device is correct, and counts first and assert number；If comparing result is not phase
Together, then the capability error of the first working device is verified, and the processing that reports an error is carried out to the first working device of current check, to realize in terms of
When any input capture passage of device inside modules the input of the first working device and the correctness of output relation checked, can be with
Fast positioning errors present, facilitate collecting function coverage rate, greatly shorten the purpose of debug time.
The embodiment of the present invention provides the simulating, verifying device of another timer.Fig. 5 for it is provided in an embodiment of the present invention again
A kind of structural representation of the simulating, verifying device of timer, as shown in figure 5, on the basis of above-described embodiment, assertion verification
Component 40 also includes：Output produces authentication module 430.
Wherein, output produces authentication module 430 and included：With 122 one-to-one second authentication unit of the second working device
431, any second authentication unit 431, connected with the signal input part and signal output part of corresponding second working device 122, with
Corresponding register authentication unit 411 connects, for according to the second input data of the second working device 122, (signal input part to be defeated
The signal entered) and/or corresponding register data, determine the second checking output data, the checking output data of contrast second and the
The second output data (signal of signal output part output) of two working devices 122, if comparing result is identical, verifies the second work
It is correct to make the function of device 122, and counts second and asserts number；If comparing result verifies the second working device 122 to differ
Capability error, and the processing that reports an error is carried out to the second working device 122 of current check.It should be noted that for convenience of signal, Fig. 5
The exemplary output all the way that draws produces passage.
Wherein, second assert number according to what corresponding second authentication unit counted, determine the second authentication unit whether by
Performed, and then determine whether the second working device was performed.If the second of corresponding second authentication unit statistics asserts number
It is zero, it is determined that the second authentication unit was not performed, and then determined that the second working device was not performed, i.e. second working device
Function do not cover.If the second of corresponding second authentication unit statistics asserts that number is more than zero, it is determined that the second checking is single
Member was performed, and then determined that the second working device was performed, i.e. the function of second working device is capped.
The technical scheme of the present embodiment provides the simulating, verifying device of another timer, and the embodiment is in above-mentioned implementation
On the basis of example, by any second authentication unit, connect with the signal input part and signal output part of corresponding second working device
Connect, connected with corresponding register authentication unit, for the second input data according to the second working device and/or corresponding deposit
Device data, the second output data of the second checking output data, the checking output data of contrast second and the second working device is determined, if
Comparing result is identical, then verifies that the function of the second working device is correct, and counts second and assert number；If comparing result is not phase
Together, then the capability error of the second working device is verified, to realize that output any to Timer module inside produces the second work of passage
Make the input of device and the correctness of output relation checked, collecting function coverage rate can be facilitated with fast positioning errors present,
Greatly shorten the purpose of debug time.
Optionally, assertion verification component can be produced by script language code, convenient by input capture passage or output all the way
The assertion verification component of passage is produced, multichannel input capture passage is produced or output produces the assertion verification component of passage, it is convenient
Fast construction verification environment.
The embodiment of the present invention provides a kind of emulation verification method of timer.Fig. 6 is one kind provided in an embodiment of the present invention
The flow chart of the emulation verification method of timer.The timer that the emulation verification method can be provided based on any embodiment of the present invention
Simulating, verifying device realize.The emulation verification method can be applied to the simulation checking system of timer, the simulation checking system
The simulating, verifying device of the timer provided including Timer module and any embodiment of the present invention.The emulation verification method is by counting
When device module perform, specifically comprise the following steps：
The configuration data that step 510, Timer module generate according to register configuration component, configuration the first register and/
Or second register data.
The data output of first register and/or the second register to register is checked mould by step 520, Timer module
Block.
The emulation verification method of timer provided in an embodiment of the present invention, it is the meter provided based on any embodiment of the present invention
When device simulating, verifying device realize, therefore the emulation verification method of timer provided in an embodiment of the present invention also possess it is above-mentioned
Beneficial effect described in embodiment, here is omitted.
The embodiment of the present invention provides the emulation verification method of another timer.Fig. 7 for it is provided in an embodiment of the present invention again
A kind of flow chart of the emulation verification method of timer.The emulation verification method is performed by Timer module, in above-described embodiment
On the basis of, component is produced when simulating, verifying device also includes excitation, assertion verification component also includes input capture authentication module
When, the emulation verification method of the timer comprises the following steps：
The configuration data that step 510, Timer module generate according to register configuration component, configuration the first register and/
Or second register data.
The data output of first register and/or the second register to register is checked mould by step 520, Timer module
Block.
Step 530, any first working device are raw according to the first input data, and/or the data of corresponding first register
Into corresponding first output data.
Step 540, Timer module by the first input data of any first working device and the first output data export to
Corresponding first authentication unit.
The embodiment of the present invention provides the emulation verification method of another timer.Fig. 8 for it is provided in an embodiment of the present invention again
A kind of flow chart of the emulation verification method of timer.The emulation verification method is performed by Timer module, in above-described embodiment
On the basis of, when assertion verification component, which also includes output, produces authentication module, the emulation verification method of the timer is included such as
Lower step：
The configuration data that step 510, Timer module generate according to register configuration component, configuration the first register and/
Or second register data.
The data output of first register and/or the second register to register is checked mould by step 520, Timer module
Block.
The data of step 550, any second working device, second register corresponding to, and/or the second input data, it is raw
Into corresponding second output data.
Step 560, Timer module by the second input data of any second working device and the second output data export to
Corresponding second authentication unit.
The embodiment of the present invention provides a kind of emulation verification method of the timer performed by assertion verification component.Fig. 9 is this
A kind of flow chart of the emulation verification method for timer performed by assertion verification component that inventive embodiments provide.The emulation is tested
The simulating, verifying device for the timer that card method can be provided based on any embodiment of the present invention is realized.The simulating, verifying of the timer
Method can be applied to the simulation checking system of timer, and the simulation checking system includes Timer module and any implementation of the present invention
The simulating, verifying device for the timer that example provides.The emulation verification method is performed by assertion verification component, specifically includes following step
Suddenly：
Step 610, any register authentication unit generate register count according to the configuration data of register configuration component
According to.
Step 620, assertion verification component introduce the number of each first register and/or the second register of Timer module
According to.
Step 630, any register authentication unit contrast register data are deposited with corresponding first register or second
The data of device.
Wherein, if comparing result is identical, the first register or the second register configuration are correct corresponding to checking, that is, hold
Row step 640, if comparing result to differ, the first register or the second register configuration mistake corresponding to checking, that is, is held
Row step 650.
The first register or the second register configuration are correct corresponding to step 640, checking.
First register or the second register configuration mistake corresponding to step 650, checking.
The emulation verification method of the timer provided in an embodiment of the present invention performed by assertion verification component, it is to be based on this hair
What the simulating, verifying device for the timer that bright any embodiment provides was realized, thus it is provided in an embodiment of the present invention by assertion verification
The emulation verification method that component performs also possesses the beneficial effect described in above-described embodiment, and here is omitted.
The embodiment of the present invention provides the emulation verification method of another timer performed by assertion verification component.Figure 10 is
The flow chart of the emulation verification method of another timer performed by assertion verification component provided in an embodiment of the present invention.This is imitative
True verification method is performed by assertion verification component, on the basis of above-described embodiment, when assertion verification component is also caught including input
When obtaining authentication module, meanwhile, when simulating, verifying device, which also includes excitation, produces component, the emulation verification method includes following step
Suddenly：
Step 610, any register authentication unit generate register count according to the configuration data of register configuration component
According to.
Step 620, assertion verification component introduce the number of each first register and/or the second register of Timer module
According to.
Step 630, any register authentication unit contrast register data are deposited with corresponding first register or second
The data of device.
The first register or the second register configuration are correct corresponding to step 640, checking.
First register or the second register configuration mistake corresponding to step 650, checking.
Step 660, assertion verification component introduce the first input data and first of each first working device of Timer module
Output data.
Wherein, verifying that the first register configuration is correct and then performing step 660 to step 700.
Step 670, any first authentication unit the first input data of the first working device and/or corresponding corresponding to
Register data, determine the first checking output data.
First output data of step 680, the checking output data of contrast first and the first working device.
Wherein, if comparing result is identical, the function of the first working device is correct corresponding to checking, and counts first and assert
Number, that is, perform step 690；If comparing result is differs, the capability error of the first working device, that is, perform corresponding to checking
Step 700.
The function of the first working device is correct corresponding to step 690, checking, and counts first and assert number.
The capability error of first working device corresponding to step 700, checking.
The embodiment of the present invention provides the emulation verification method of another timer performed by assertion verification component.Figure 11 is
The flow chart of the emulation verification method of another timer performed by assertion verification component provided in an embodiment of the present invention.This is imitative
True verification method is performed by assertion verification component, on the basis of above-described embodiment, is produced when assertion verification component includes output
During authentication module, the emulation verification method comprises the following steps：
Step 610, any register authentication unit generate register count according to the configuration data of register configuration component
According to.
Step 620, assertion verification component introduce the number of each first register and/or the second register of Timer module
According to.
Step 630, any register authentication unit contrast register data are deposited with corresponding first register or second
The data of device.
The first register or the second register configuration are correct corresponding to step 640, checking.
First register or the second register configuration mistake corresponding to step 650, checking.
Step 710, assertion verification component introduce the second input data and second of each second working device of Timer module
Output data.
Wherein, in checking, all the second register configuration is correct and then performs step 710 to step 750.
Step 720, any second authentication unit the second input data of the second working device and/or corresponding corresponding to
Register data, determine the second checking output data.
Second output data of step 730, the checking output data of contrast second and the second working device.
Wherein, if comparing result is identical, the function of the second working device is correct corresponding to checking, and counts second and assert
Number, that is, perform step 740；If comparing result is differs, the capability error of the second working device, that is, perform corresponding to checking
Step 750.
The function of the second working device is correct corresponding to step 740, checking, and counts second and assert number.
The capability error of second working device corresponding to step 750, checking.
Pay attention to, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust, be combined with each other and substitute without departing from protection scope of the present invention.Therefore, although by above example to this
Invention is described in further detail, but the present invention is not limited only to above example, is not departing from present inventive concept
In the case of, other more equivalent embodiments can also be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
- A kind of 1. simulating, verifying device of timer, it is characterised in thatTimer module, including multiple input capture passages, multiple outputs produce passage and register submodule；Wherein, the register submodule includes：Multiple first registers for being correspondingly arranged with each input capture passage and Multiple second registers being correspondingly arranged with each output generation passage；Any input capture passage includes multiple first working devices, and the multiple first working device is according to the first default connection Mode carries out data transmission, and according to the data of the first register corresponding with first working device, determines first work The mode of operation of device, to realize default input capture function；Any output, which produces passage, includes multiple second working devices, and the multiple second working device is according to the second default connection Mode carries out data transmission, and according to the data of the second register corresponding with second working device, determines second work The mode of operation of device, to realize that default output produces function；Simulating, verifying device includes：Register configuration component and assertion verification component；The register configuration component, the configuration number of first register and/or second register is configured for generating According to；The Timer module, for according to the configuration data, configuring the number of first register and/or the second register According to；The assertion verification component, including register check module, wherein, the register checks that module includes and described first Register and/or the one-to-one register authentication unit of the second register, any register authentication unit are used for basis The configuration data of register configuration component generation, generates register data, contrasts the register data and corresponding the The data of one register or the second register, if comparing result is identical, verify first register or the second register Configuration is correct, if comparing result verifies first register or the second register configuration mistake to differ.
- 2. the simulating, verifying device of timer according to claim 1, it is characterised in that the simulating, verifying device also wraps Include：Excitation produces component, for generating default excited data, the input signal as the input capture passage；The assertion verification component also includes：Input capture authentication module；The input capture authentication module includes：It is any described with one-to-one first authentication unit of first working device First authentication unit is used for the first input data of the first working device and/or the corresponding register data corresponding to, The first output data of the first checking output data, the contrast first checking output data and first working device is determined, If comparing result is identical, verify that the function of first working device is correct, and count first and assert number；If comparing result To differ, then the capability error of first working device is verified, wherein, first input data is first working device Signal input part input signal, first output data for first working device signal output part output letter Number.
- 3. the simulating, verifying device of timer according to claim 1 or 2, it is characterised in that the assertion verification component Also include：Output produces authentication module,The output, which produces authentication module, to be included：It is any described with one-to-one second authentication unit of second working device Second authentication unit is used for the second input data of the second working device and/or the corresponding register data corresponding to, The second output data of the second checking output data, the contrast second checking output data and second working device is determined, If comparing result is identical, verify that the function of second working device is correct, and count second and assert number；If comparing result To differ, then the capability error of second working device is verified, wherein, second input data is second working device Signal input part input signal, second output data for second working device signal output part output letter Number.
- 4. the simulating, verifying device of timer according to claim 1, it is characterised in that under first working device includes State at least one：Synchronizer, marginal detector, edge selector, way selectors, Clock dividers, the first master timer, catch Obtain register and input frequency divider；Second working device includes following at least one：Export comparand register, the second master timer, output comparator, defeated Exit pattern controller, output delay controller and output polarity selector.
- 5. a kind of emulation verification method of timer, the simulating, verifying device based on any described timers of claim 1-4 Realize, it is characterised in that including：The configuration data that Timer module generates according to register configuration component, configure the first register and/or the second register Data；The data output of first register and/or the second register to register is checked module by the Timer module.
- 6. the emulation verification method of timer according to claim 5, it is characterised in that when the simulating, verifying device also Component, when the assertion verification component also includes input capture authentication module, the simulating, verifying of the timer are produced including excitation Method also includes：Any first working device is according to the first input data, and/or the data of corresponding first register, first corresponding to generation Output data；The Timer module exports the first input data of any first working device and the first output data to corresponding The first authentication unit.
- 7. the emulation verification method of the timer according to claim 5 or 6, it is characterised in that when the assertion verification group When part also includes output generation authentication module, the emulation verification method of the timer also includes：The data of any second working device, second register corresponding to, and/or the second input data, second corresponding to generation Output data；The Timer module exports the second input data of any second working device and the second output data to corresponding The second authentication unit.
- 8. a kind of emulation verification method of timer, the simulating, verifying device based on any described timers of claim 1-4 Realize, it is characterised in that including：Any register authentication unit generates register data according to the configuration data of register configuration component；Assertion verification component introduces the data of each first register and/or the second register of Timer module；Any register authentication unit contrasts the register data and corresponding first register or the second register Data；If comparing result is identical, verify that first register or the second register configuration are correct；If comparing result verifies first register or the second register configuration mistake to differ.
- 9. the emulation verification method of timer according to claim 8, it is characterised in that when the simulating, verifying device also Component, when the assertion verification component also includes input capture authentication module, the simulating, verifying of the timer are produced including excitation Method also includes：The assertion verification component introduces the first input data and the first output of each first working device of the Timer module Data；Any first authentication unit the first input data of the first working device and/or corresponding register count corresponding to According to determining the first checking output data；Contrast the first checking output data and the first output data of first working device；If comparing result is identical, verify that the function of first working device is correct, and count first and assert number；If comparing result verifies the capability error of first working device to differ.
- 10. the emulation verification method of timer according to claim 8 or claim 9, it is characterised in that when the assertion verification group When part also includes output generation authentication module, the emulation verification method of the timer also includes：The assertion verification component introduces the second input data and the second output of each second working device of the Timer module Data；Any second authentication unit the second input data of the second working device and/or corresponding register count corresponding to According to determining the second checking output data；Contrast the second checking output data and the second output data of second working device；If comparing result is identical, verify that the function of second working device is correct, and count second and assert number；If comparing result verifies the capability error of second working device to differ.
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