CN107437566A - One kind has compound medium layer wide band gap semiconducter vertical double-diffused MOS FET and preparation method thereof - Google Patents
One kind has compound medium layer wide band gap semiconducter vertical double-diffused MOS FET and preparation method thereof Download PDFInfo
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- CN107437566A CN107437566A CN201710623838.XA CN201710623838A CN107437566A CN 107437566 A CN107437566 A CN 107437566A CN 201710623838 A CN201710623838 A CN 201710623838A CN 107437566 A CN107437566 A CN 107437566A
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- 150000001875 compounds Chemical class 0.000 title claims abstract description 24
- 238000002360 preparation method Methods 0.000 title abstract description 3
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 16
- 230000015556 catabolic process Effects 0.000 claims description 14
- 238000009413 insulation Methods 0.000 claims description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 4
- 238000002156 mixing Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 9
- 239000000203 mixture Substances 0.000 abstract description 5
- 239000002131 composite material Substances 0.000 abstract description 2
- 238000009825 accumulation Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention, which proposes one kind, has compound medium layer (Composite Dielectric Layer, CDL) broad-band gap vertical double-diffused MOS FET (VDMOS) and preparation method thereof, the device are mainly the compound medium layer that semi-insulating polysilicon layer (SIPOS) and high-k (High K) dielectric layer composition is formed in device gate base part drift region side wall.SIPOS posts are evenly distributed with having uniform electric field in High K dielectric layers by the drift region internal electric field of Electric Field Modulated device when device turns off.Meanwhile SIPOS posts and the common assisted depletion drift region of High K dielectric layers, the ability that exhausts that device drift region is greatly improved cause the drift doping concentration of device to increase, conducting resistance reduces.There is majority-carrier accumulation layer when device is opened so that the conducting resistance of device further reduces in the side wall of drift region.
Description
Technical field
The present invention relates to field of semiconductor devices, more particularly to a kind of longitudinal double diffused metal of groove (Trench) type
Oxide semiconductor field effect pipe.
Background technology
Wide bandgap semiconductor materials have big energy gap, high critical breakdown electric field, high heat conductance and high electronics saturation
The features such as drift velocity, therefore it has boundless application prospect in the field of power electronics of high-power, high temperature and high frequency.
At present using the typical SiC of wide band gap semiconducter as in the FET of substrate, vertical DMOS field
Effect pipe (VDMOS) is one of object being widely studied.Groove (Trench) MOS is proposed by D.Ueda et al. in 1985
Structure.The communication channel for causing device using U-shaped groove structure is changed into longitudinal from horizontal, effectively eliminates JFET resistance,
Primitive unit cell density is considerably increased, improves the current handling capability of device.But in power device high-voltage applications field, with
The rise of device electric breakdown strength, power VDMOSFET epitaxy layer thickness are continuously increased, and drift doping concentration gradually reduces, and causes device
The conducting resistance of part can increase as device electric breakdown strength increases so that the conduction loss increase of device.
The content of the invention
The present invention, which proposes one kind, has compound medium layer (Composite Dielectric Layer, CDL) broad-band gap
Semiconductor vertical double-diffused MOS FET (VDMOS), it is intended to further optimize wide band gap semiconducter
VDMOS device breakdown voltage and the contradictory relation than conducting resistance.
Technical scheme is as follows：
One kind has compound medium layer wide band gap semiconducter vertical double-diffused MOS FET, wraps
Include：
The substrate of semi-conducting material, as drain region；
In the drift region that substrate Epitaxial growth is formed；
Base to be formed left and right two is adulterated in the drift region upper surface；
The source region and channeled substrate contact that doping is formed respectively on the base top；
In the source electrode that the source region and channeled substrate contact upper surface are formed；
In the drain electrode that the drain region lower surface is formed；
Be different from existing VDMOS is：
The substrate and the material of drift region are wide bandgap semiconductor materials, are carved between base at described left and right two
The groove of erosion, groove is longitudinally through drift region to substrate drain region；The depth-to-width ratio of groove according to the length of the drift region of device and
Width determines that the length of drift region requires to determine according to breakdown voltage；
The gate insulation layer that is sequentially formed in the trenched side-wall, there is the semi-insulating polysilicon layer for mixing oxygen, make semi-insulating more
Crystal silicon layer longitudinal direction both ends are connected with the grid leak both ends of device；Semi-insulating polysilicon layer longitudinal surface is heavily doped region corresponding to base
Domain；Correspond to the grid of base formation in semi-insulating polysilicon layer longitudinal surface.
Turn on surface and High K media are filled in the groove of semi-insulating polysilicon layer, High K media and drift region longitudinal direction
It is contour.
On the basis of above scheme, the present invention has also made following optimization：
The relative dielectric constant of High K materials is 100~2000.
The width (namely surface turns into the width of the groove of semi-insulating polysilicon layer) of High K media is 0.2 in transverse direction
~5 μm.
The thickness of gate insulation layer determines that representative value is 0.02~0.1 μm according to threshold voltage.
The concentration that the doping concentration of the substrate of wide bandgap semiconductor materials is prepared or adulterated for general material, the model of representative value
Enclose for 1 × 1013cm-3~1 × 1015cm-3。
When breakdown voltage requires 1200V, then depth-to-width ratio is 10:1~20:1；When breakdown voltage requires 600V, then depth-to-width ratio
For 5:1-10:1.
The thickness of semi-insulating polysilicon layer is 0.2~1.5 μm.Semi-insulating polysilicon layer mix oxygen ratio for 15%~
35%, its corresponding resistor rate is 109~1011Ω·cm。
The doping concentration of heavily doped region described in semi-insulating polysilicon layer is 1018~1020cm-3。
Gallium nitride, carborundum, diamond etc. may be selected in wide bandgap semiconductor materials.
A kind of compound medium layer longitudinal double diffusion metal oxide of the above based on wide band gap semiconducter substrate that make partly is led
The method of body FET, comprises the following steps：
1) substrate of wide bandgap semiconductor materials is taken, while is used as drain region；
2) epitaxial layer is formed on substrate as drift region；
3) base is formed with ion implanting on drift region top；
4) in base etching groove, groove is made to be passed down through drift region to drain region；
5) gate insulation layer is formed on trenched side-wall；
6) deposit forms semi-insulating polysilicon layer and mixes oxygen outside gate insulation layer；
7) the area filling High K media of drift region are longitudinally corresponded in groove；
8) doping forms source region and channeled substrate contact on base；
9) region for longitudinally corresponding to base to semi-insulating polysilicon layer surface in groove carries out heavy doping, and deposits polycrystalline
Silicon forms grid；
10) source region and channeled substrate contact surface form source electrode；
11) drain region surface forms drain electrode.
Technical solution of the present invention has the beneficial effect that：
Semi-insulating polysilicon (SIPOS) layer is formed in the side wall of VDMOS device drift region using deep trench technology, is made
The gate electrode and drain electrode (be connected to drain region can be considered be connected with drain electrode) of its both ends difference interface unit.It is empty among SIPOS layers
Gap is partially filled with High K materials.There is uniform electricity when device turns off on the compound medium layer of SIPOS and High K compositions
, acting on the overall electric field on device drift region by Electric Field Modulated becomes uniform, while compound medium layer increase device
Ability is exhausted, the ability that exhausts than simple only SIPOS layers or the only situation device of High K layers strengthens, i.e., significantly carries
The doping concentration of high device drift region has relatively low conduction loss in break-over of device.The compound medium layer when device is opened
More majority carriers are accumulated on device drift region, the conducting resistance of device further reduces.
In a word, the CBL VDMOS devices based on wide bandgap semiconductor materials compared to traditional wide band gap semiconducter VDMOS and
Silicon substrate VDMOS device, in the case of identical drift region length, CBL VDMOS devices have higher pressure-resistant and lower lead
Logical loss, CBL VDMOS devices have better performance.
Brief description of the drawings
Fig. 1 be the embodiment of the present invention structural representation (front view), device architecture dotted line specular along figure.
Drawing reference numeral explanation：
1- source electrodes；2- gate insulation layers；3- semi-insulating polysilicon layers；4- grids；5-High K materials；6- drains；7- substrates
Drain region；8- drift regions；9- bases；10- channeled substrates contact；11- source regions.
Embodiment
As shown in figure 1, it should be imitated based on wide band gap semiconducter compound medium layer vertical double-diffused MOS field
Should manage including：
The substrate drain region 7 of wide bandgap semiconductor materials, growth conditions and doping of the doping concentration according to wide band gap semiconducter
Technique determines that Typical value range is 1 × 1012cm-3~1 × 1015cm-3；
The drift region 8 that epitaxial layer on substrate is formed；
The base 9 of formation is adulterated on the drift region；
The etching groove on base, groove are passed down through drift region to substrate drain region；
The gate insulation layer 2 formed on trenched side-wall, thickness are 0.02~0.1 μm；
What deposit was formed outside gate insulation layer has the semi-insulating polysilicon layer 3 for mixing oxygen；The thickness of semi-insulating polysilicon layer
For 0.2~1.5 μm；The oxygen ratio of mixing of semi-insulating polysilicon layer is 15%~35%, and its corresponding resistor rate is 109~1011Ω·
cm；
Longitudinally corresponding to filling High K dielectric materials, relative dielectric constant 100 in the region of drift region 8 in groove
~1000；The width of High K media is 0.2~5 μm in transverse direction；
Adulterated on base and form source region 11 and channeled substrate contact 10 respectively；
The region for corresponding to base to the surface longitudinal of semi-insulating polysilicon layer 3 carries out high-concentration dopant (such as 1018~
1020cm-3) and form grid 4；
Source electrode is formed in source region 11 and channeled substrate contact 10.
SIPOS layers are formed in the side wall of VDMOS device drift region using deep trench technology, its both ends is distinguished connector
The gate electrode and drain electrode (be connected to drain region can be considered be connected with drain electrode) of part.SIPOS layer intermediate gaps are partially filled with High K
Material.There is uniform electric field on the compound medium layer of SIPOS and High K compositions when device turns off, made by Electric Field Modulated
With causing the overall electric field on device drift region to become uniform, while compound medium layer increase device exhausts ability, than simple
The only ability that exhausts of SIPOS layers or the only situation device of High K layers strengthens, that is, device drift region is greatly improved
Doping concentration has relatively low conduction loss in break-over of device.Compound medium layer product on device drift region when device is opened
Tire out more majority carriers, the conducting resistance of device further reduces.
By taking N-channel wide band gap semiconducter VDMOS as an example, it can specifically be prepared by following steps：
1) substrate of wide bandgap semiconductor materials is as drain region；
2) N-type drift region is formed on the upper epitaxial layer of substrate drain region；
3) p-type base is formed by ion implanting in N-type drift region；
4) etching groove on p-type base, beneath trenches pass through drift region to substrate drain region；The depth-to-width ratio of groove is according to device
The length and width of the drift region of part determines that the length of drift region requires to determine according to breakdown voltage；Breakdown voltage requires 1200V
When, then depth-to-width ratio is 10:1~20:1；When breakdown voltage requires 600V, then depth-to-width ratio is 5:1-10:1；
5) gate insulation layer is formed on trenched side-wall；
6) one layer thin of SIPOS layers are deposited outside gate insulation layer and mix oxygen；
7) High K dielectric materials are filled in the longitudinal drift region in groove；
8) source region and channeled substrate contact are formed respectively by ion implanting in base；
9) it is that base exterior lateral area carries out high-concentration dopant by ion implanting to SIPOS layers in groove；
10) trench interiors base region depositing polysilicon forms gate electrode；
11) device surface deposit passivation layer, and etch contact hole；
12) deposit metal and etch and form source electrode and gate electrode；
13) drain electrode is formed on substrate drain region.
Being emulated through Sentaurus, the performance of new device proposed by the present invention is significantly lifted compared to traditional devices, and two
For kind device under equal breakdown voltage, the conducting resistance of new device reduces 60%.
Certainly, the wide band gap semiconducter VDMOS in the present invention can also be P-type channel, its structure and N raceway grooves VDMOS etc.
Together, these are regarded as belonging to the application scope of the claims, will not be repeated here.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvement and replacement can also be made, these improve and replaced
Scheme also fall into protection scope of the present invention.
Claims (10)
1. one kind has compound medium layer wide band gap semiconducter vertical double-diffused MOS FET, including：
The substrate of semi-conducting material, as drain region；
In the drift region that substrate Epitaxial growth is formed；
Base to be formed left and right two is adulterated in the drift region upper surface；
The source region and channeled substrate contact that doping is formed respectively on the base top；
In the source electrode that the source region and channeled substrate contact upper surface are formed；
In the drain electrode that the drain region lower surface is formed；
It is characterized in that：
The substrate and the material of drift region are wide bandgap semiconductor materials, and shape is etched between base at described left and right two
Into groove, groove is longitudinally through drift region to substrate drain region；The depth-to-width ratio of groove is according to the length and width of device drift region
It is determined that the length of drift region requires to determine according to the breakdown voltage of device；
The gate insulation layer that is sequentially formed in the trenched side-wall, there is the semi-insulating polysilicon layer for mixing oxygen, make semi-insulating polysilicon
The longitudinal both ends of layer are connected with the grid leak both ends of device；Semi-insulating polysilicon layer longitudinal surface is heavily doped region corresponding to base,
Grid is formed in the heavily doped region；
Turn on surface and High K media are filled in the groove of semi-insulating polysilicon layer, High K media and drift region longitudinal direction etc.
It is high.
2. according to claim 1 have compound medium layer wide band gap semiconducter vertical double-diffused MOS
FET, it is characterised in that：The relative dielectric constant of High K materials is 100~2000.
3. according to claim 2 have compound medium layer wide band gap semiconducter vertical double-diffused MOS
FET, it is characterised in that：The width of High K media is 0.2~5 μm in transverse direction.
4. according to claim 1 have compound medium layer wide band gap semiconducter vertical double-diffused MOS
FET, it is characterised in that：For the thickness of gate insulation layer according to threshold voltage settings, representative value is 0.02~0.1 μm.
5. according to claim 1 have compound medium layer wide band gap semiconducter vertical double-diffused MOS
FET, it is characterised in that：The doping concentration of substrate is 1 × 1013cm-3~1 × 1015cm-3。
6. according to claim 1 have compound medium layer wide band gap semiconducter vertical double-diffused MOS
FET, it is characterised in that：When breakdown voltage requires 1200V, then the depth-to-width ratio of groove is 10:1~20:1；Breakdown voltage will
When seeking 600V, then the depth-to-width ratio of groove is 5:1-10:1.
7. according to claim 1 have compound medium layer wide band gap semiconducter vertical double-diffused MOS
FET, it is characterised in that：The thickness of semi-insulating polysilicon layer is 0.2~1.5 μm；Semi-insulating polysilicon layer mixes oxygen ratio
For 15%~35%, its corresponding resistor rate is 109~1011Ω·cm。
8. according to claim 1 have compound medium layer wide band gap semiconducter vertical double-diffused MOS
FET, it is characterised in that：The doping concentration of heavily doped region described in semi-insulating polysilicon layer is 1018~1020cm-3。
9. according to claim 1 have compound medium layer wide band gap semiconducter vertical double-diffused MOS
FET, it is characterised in that：The wide bandgap semiconductor materials are gallium nitride, carborundum or diamond.
10. one kind, which is made described in claim 1, has compound medium layer wide band gap semiconducter longitudinal double diffusion metal oxide half
The method of conductor FET, comprises the following steps：
1) substrate of wide bandgap semiconductor materials is taken, while is used as drain region；
2) epitaxial layer is formed on substrate as drift region；
3) base is formed with ion implanting on drift region top；
4) in base etching groove, groove is made to be passed down through drift region to drain region；
5) gate insulation layer is formed on trenched side-wall；
6) deposit forms semi-insulating polysilicon layer outside gate insulation layer；
7) the area filling High K media of drift region are longitudinally corresponded in groove；
8) doping forms source region and channeled substrate contact on base；
9) region for longitudinally corresponding to base to semi-insulating polysilicon layer surface in groove carries out heavy doping, and depositing polysilicon shape
Into grid；
10) source region and channeled substrate contact surface form source electrode；
11) drain region surface forms drain electrode.
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| CN201710623838.XA CN107437566B (en) | 2017-07-27 | 2017-07-27 | Semiconductor longitudinal double-diffusion metal oxide semiconductor field effect transistor with composite dielectric layer wide band gap and manufacturing method thereof |
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| CN201710623838.XA CN107437566B (en) | 2017-07-27 | 2017-07-27 | Semiconductor longitudinal double-diffusion metal oxide semiconductor field effect transistor with composite dielectric layer wide band gap and manufacturing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511527A (en) * | 2018-04-08 | 2018-09-07 | 西安电子科技大学 | Vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block |
| CN110034175A (en) * | 2019-03-07 | 2019-07-19 | 电子科技大学 | Longitudinal direction can integrated power device |
| WO2022095834A1 (en) * | 2020-11-06 | 2022-05-12 | 中国电子科技集团公司第二十四研究所 | Shared-dielectric resistive field plate field effect mos device, and manufacturing method therefor |
| US11888038B2 (en) | 2020-10-08 | 2024-01-30 | Samsung Electronics Co., Ltd. | Integrated circuit devices and methods of manufacturing the same |
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| US20060065923A1 (en) * | 2004-09-24 | 2006-03-30 | Infineon Technologies Ag. | High-voltage-resistant semiconductor component having vertically conductive semiconductor body areas and a trench structure |
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| US20060065923A1 (en) * | 2004-09-24 | 2006-03-30 | Infineon Technologies Ag. | High-voltage-resistant semiconductor component having vertically conductive semiconductor body areas and a trench structure |
| CN102779836A (en) * | 2012-07-13 | 2012-11-14 | 电子科技大学 | Longitudinal power device with low specific on-resistance using high dielectric constant groove structure |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511527A (en) * | 2018-04-08 | 2018-09-07 | 西安电子科技大学 | Vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block |
| CN110034175A (en) * | 2019-03-07 | 2019-07-19 | 电子科技大学 | Longitudinal direction can integrated power device |
| US11888038B2 (en) | 2020-10-08 | 2024-01-30 | Samsung Electronics Co., Ltd. | Integrated circuit devices and methods of manufacturing the same |
| WO2022095834A1 (en) * | 2020-11-06 | 2022-05-12 | 中国电子科技集团公司第二十四研究所 | Shared-dielectric resistive field plate field effect mos device, and manufacturing method therefor |
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| CN107437566B (en) | 2020-06-16 |
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