CN107431070B

CN107431070B - Switching device and memory device

Info

Publication number: CN107431070B
Application number: CN201680017534.2A
Authority: CN
Inventors: 清宏彰; 大场和博
Original assignee: Sony Semiconductor Solutions Corp
Current assignee: Sony Semiconductor Solutions Corp
Priority date: 2015-03-31
Filing date: 2016-03-16
Publication date: 2022-03-01
Anticipated expiration: 2036-03-16
Also published as: JPWO2016158430A1; KR102514350B1; CN107431070A; JP6791845B2; US10529777B2; US20180204881A1; WO2016158430A1; KR20170134377A

Abstract

A switching device according to one embodiment of the present technology includes: the switching layer includes a first electrode, a second electrode facing the first electrode, and a switching layer disposed between the first electrode and the second electrode. The switching layer is configured to include a chalcogen element. The switching device also includes a diffusion inhibiting layer in contact with at least a portion of a surface of the switching layer and inhibiting diffusion of oxygen into the switching layer.

Description

Switching device and memory device

Technical Field

The present disclosure relates to a switching device including a chalcogenide layer between electrodes, and to a memory apparatus including the switching device.

Background

In recent years, an increase in capacity has been demanded for data storage nonvolatile memories typified by resistance change memories such as a resistance random access memory (ReRAM) and a phase change random access memory (PRAM) (registered trademark). However, in the conventional resistance change memory using the access transistor, the occupied area per unit cell is large. Therefore, even if miniaturization is performed under the same design rule, an increase in capacity is not easy as compared with, for example, a NAND flash memory. In contrast, in the case of using a so-called cross-point array structure in which memory devices are disposed at cross points (cross points) of cross wirings, the occupied area per unit cell is reduced, which makes it possible to achieve an increase in capacity.

In addition to the memory devices in the cross-point memory cells, selection devices (switching devices) for cell selection are also provided. Examples of the switching device include a switching device constructed using, for example, a PN diode, an avalanche diode, or a metal oxide (see, for example, NPTL 1 and 2), and a switching device that is switched at a predetermined threshold voltage by Mott transition so as to greatly increase a current (see, for example, NPTL 3 and 4).

Examples of the switching device include a switching device using a chalcogenide material (an Ovonic Threshold Switch (OTS) device). OTS devices are disclosed in, for example,

PTLs

1 and 2. The OTS device has a characteristic in which a current sharply increases at a switching threshold voltage or higher, which makes it possible to provide a relatively large current density in a selected (ON) state. Furthermore, the layer made of chalcogenide material (OTS layer) has an amorphous microstructure. This allows the formation of the OTS layer under room temperature conditions, such as a Physical Vapor Deposition (PVD) process or a Chemical Vapor Deposition (CVD) process. Thus, OTS devices have the advantage of high processing affinity with the manufacturing process of the memory device.

Reference list

Patent document

PTL 1: japanese unexamined patent application publication No.2006-86526

PTL 2: japanese unexamined patent application publication No.2010-157316

Non-patent document

NPTL 1: Jiun-Jia Huang et al, 2011IEEE IEDM 11-733-736

NPTL 2: wootea Lee et al, 2012IEEE VLSI Technology symposium, pages 37 to 38

NPTL 3: myungwoo Son et al, IEEE ELECTRON DEVICE LETTERS, Vol.32, No. 11, 11 months 2011

NPTL 4: seonghyun Kim et al 2012VLSI, pages 155 to 156

Disclosure of Invention

In the cross-point memory cell array, increasing the number of cross points makes it possible to achieve an increase in capacity. However, in the case where the threshold voltage variation is large in each OTS device, the voltage at which the resistance variation occurs in the memory cell having the combination of the memory device and the switching device greatly varies, and the settable range of the read voltage (read margin) between the high resistance state and the low resistance state of the memory cell becomes small. Therefore, there is a problem that the number of intersections does not easily increase.

Accordingly, it is desirable to provide a switching device that makes it possible to suppress variations in operating threshold voltage in each OTS device, and a memory apparatus including the switching device.

A switching device according to a first embodiment of the present disclosure includes: a first electrode; a second electrode facing the first electrode; and a switching layer disposed between the first electrode and the second electrode. The switching layer includes one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S). The switching device also includes a diffusion inhibiting layer in contact with at least a portion of a surface of the switching layer and inhibiting diffusion of oxygen into the switching layer.

A memory device according to a first embodiment of the present disclosure includes a plurality of memory cells. Each memory cell includes a memory device and a switching device directly coupled to the memory device. The switching device included in each memory cell has the same configuration as that of the above-described switching device according to the first embodiment.

In the switching device according to the first embodiment of the present disclosure and the storage apparatus according to the first embodiment of the present disclosure, at least the portion of the surface of the switching layer is covered with a diffusion suppressing layer that suppresses diffusion of oxygen into the switching layer. This makes it possible to reduce the amount of oxygen that enters the switching layer during the manufacturing process of the switching device or in the use of the switching device. Here, in the case where the amount of oxygen contained in the switching layer is larger than a predetermined amount, the variation in the operation threshold voltage of the switching device becomes large. In contrast, in the case where the amount of oxygen contained in the switching layer is equal to or less than the predetermined amount, the variation in the operating threshold voltage of the switching device becomes small. Thus, at least the portion of the surface of the switching layer is covered by the diffusion suppressing layer that suppresses diffusion of oxygen into the switching layer, which enables the amount of oxygen contained in the switching layer to be less than a predetermined amount. This can suppress variation in the operating threshold voltage of the switching device.

A switching device according to a second embodiment of the present disclosure includes: a first electrode; a second electrode facing the first electrode; and a switching layer disposed between the first electrode and the second electrode. The switching layer contains one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), and has an oxygen content of 5 at% or less.

A memory device according to a second embodiment of the present disclosure includes a plurality of memory cells. Each memory cell includes a memory device and a switching device directly coupled to the memory device. The switching device included in each memory cell has the same configuration as that of the above-described switching device according to the second embodiment.

In the switching device according to the second embodiment of the present disclosure and the storage apparatus according to the second embodiment of the present disclosure, the oxygen content of the switching layer is 5 at% or less. Here, in the case where the amount of oxygen contained in the switching layer is more than 5 at%, the variation in the operation threshold voltage of the switching device becomes large. In contrast, in the case where the amount of oxygen contained in the switching layer is 5 at% or less, the variation in the operating threshold voltage of the switching device becomes small. Therefore, in the switching device according to the second embodiment of the present disclosure, the variation in the operation threshold voltage of the switching device can be made small.

Each of the switching device according to the first embodiment of the present disclosure, the memory apparatus according to the first embodiment of the present disclosure, the switching device according to the second embodiment of the present disclosure, and the memory apparatus according to the second embodiment of the present disclosure makes it possible to make the variation in the operating threshold voltage of the switching device small.

Drawings

Fig. 1 is a diagram illustrating a schematic configuration of a memory cell array according to one embodiment of the present disclosure.

Fig. 2A is a diagram illustrating an example of the configuration of the memory cell of fig. 1.

Fig. 2B is a diagram illustrating an example of the configuration of the memory cell of fig. 1.

Fig. 3 is a diagram illustrating an example of a cross-sectional configuration of a portion of the switching device of fig. 1 and the periphery thereof.

Fig. 4A is a diagram illustrating an example of a cross-sectional configuration of a portion of the switching device of fig. 2A and the periphery thereof.

Fig. 4B is a diagram illustrating an example of a cross-sectional configuration along the line a-a in fig. 4A.

Fig. 5A is a diagram illustrating an example of a cross-sectional configuration of a portion of the switching device of fig. 2B and the periphery thereof.

Fig. 5B is a diagram illustrating an example of a cross-sectional configuration along line a-a in fig. 5A.

Fig. 6 is a diagram illustrating a modification of the cross-sectional configuration of the switching device of fig. 1.

Fig. 7A is a diagram illustrating a modification of the cross-sectional configuration of a portion of the memory cell array of fig. 1.

Fig. 7B is a diagram illustrating a modification of the cross-sectional configuration of the portion of the memory cell array of fig. 1.

Fig. 7C is a diagram illustrating a modification of the cross-sectional configuration of the portion of the memory cell array of fig. 1.

Fig. 8 is a diagram illustrating an example of IV characteristics of the switching device of fig. 1.

Fig. 9 is a diagram illustrating an example of IV characteristics of the memory device of fig. 1.

Fig. 10 is a diagram illustrating an example of IV characteristics of the memory cell of fig. 1.

Fig. 11 is a diagram illustrating an example of IV characteristics of the memory cell of fig. 1.

Fig. 12 is a diagram illustrating an example of IV characteristics of the respective memory cells of fig. 1 in an overlapping manner.

Fig. 13 is a diagram illustrating the manufacturing conditions of five samples 01 to 05.

Fig. 14 is a graph illustrating measured values of the respective oxygen contents of five samples 01 to 05.

Fig. 15 is a graph illustrating the IV characteristics of all 120 switching devices formed in each of samples 01 to 05 in an overlapping manner.

Fig. 16 is a graph illustrating the threshold voltage variation of the switching device in each of samples 01 to 05.

Fig. 17 is a TEM photograph of the switching device in sample 05.

Fig. 18 is a graph illustrating a change in threshold voltage of the switching device when the periphery of the switching device is covered with an SiO2 film or an SiN film.

Fig. 19 is a TEM photograph of the switching device without the oxide film around the switching device.

Fig. 20 is a TEM photograph of the switching device having the oxide film around the switching device.

Fig. 21 is a graph illustrating a change in threshold voltage of the switching device in a sample having an oxide film around the switching device and in a sample having no oxide film around the switching device.

Fig. 22 is a diagram illustrating a modification of the perspective configuration of the memory cell array of fig. 1.

Fig. 23 is a diagram illustrating a modification of the cross-sectional configuration of a portion of the memory cell array of fig. 1.

Detailed Description

Some embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Note that the description is given in the following order.

1. Examples of the embodiments

Examples in which a diffusion suppressing layer is provided around the switching device to reduce the oxygen content of the switching layer

2. Modifying

Modification A: examples of switching devices arranged along bit lines or word lines

And B, modification: examples omitting diffusion-suppressing layers

And C, modification: examples in which bit lines or word lines extend in the stacking direction

<1. example >

Fig. 1 is a diagram illustrating a perspective configuration of a memory cell array 1 according to one embodiment of the present disclosure. The memory cell array 1 corresponds to a specific example of "storage device" of the present disclosure. The memory cell array 1 has a so-called cross-point array structure, and includes a memory cell 10. For example, as shown in fig. 1, each memory cell 10 is disposed at a position (intersection) where each word line WL and each bit line BL face each other. In other words, the memory cell array 1 includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells 10 disposed one by one at respective intersections. As described above, the memory cell array 1 of the present embodiment has a three-dimensional structure in which a plurality of memory cells 10 are disposed in a plane (two-dimensionally, in the XY plane direction) and further stacked in the Z axis direction. This makes it possible to provide a storage device having higher density and large capacity. Further, the memory cell array 1 of the present embodiment can have a vertical cross-point structure in which one of the word lines WL and the bit lines BL is disposed parallel to the Z-axis direction, and the other remaining lines are disposed parallel to the XY plane.

The word lines WL extend in a common direction to each other. The bit lines BL extend in a direction different from and common to the extending direction of the word lines WL (for example, a direction orthogonal to the extending direction of the word lines WL). The plurality of word lines WL are disposed in one or more layers, and for example, as shown in fig. 1, the plurality of word lines WL are separately disposed in a plurality of levels (levels). The plurality of bit lines BL are disposed in one or more layers, and, for example, as shown in fig. 1, the plurality of bit lines BL are separately disposed in a plurality of levels.

In the case where a plurality of word lines WL are separately disposed in a plurality of levels, a plurality of bit lines BL are disposed in a layer between a first layer in which the plurality of word lines WL are disposed and a second layer in which the plurality of word lines WL are disposed. The second layer is adjacent to the first layer. In the case where the plurality of bit lines BL are separately disposed in a plurality of levels, the plurality of word lines WL are disposed in a layer between a third layer in which the plurality of bit lines BL are disposed and a fourth layer in which the plurality of bit lines BL are disposed. The fourth layer is adjacent to the third layer. In the case where a plurality of word lines WL are separately disposed in a plurality of levels and a plurality of bit lines BL are separately disposed in a plurality of levels, the plurality of word lines WL and the plurality of bit lines BL are alternately disposed in the stacking direction of the memory cell array 1.

The memory cell array 1 includes a plurality of memory cells 10 arranged two-dimensionally or three-dimensionally on a substrate. The substrate includes, for example, wiring groups electrically coupled to each word line WL and each bit line BL, circuits for coupling the wiring groups to an external circuit, and the like. Each memory cell 10 includes a memory device 30 and a switching device 20 directly coupled to the memory device 30. The switching device 20 corresponds to a specific example of "switching device" of the present disclosure. The memory device 30 corresponds to a specific example of "memory device" of the present disclosure.

For example, memory device 30 is disposed proximate to word line WL and switching device 20 is disposed proximate to bit line BL. It is noted that the memory device 30 may be disposed close to the bit line BL, and the switching device 20 may be disposed close to the word line WL. Further, in the case where the memory device 30 is disposed near the word line WL and the switching device 20 is disposed near the bit line BL in a certain layer, the memory device 30 may be disposed near the bit line BL and the switching device 20 may be disposed near the word line WL in a layer adjacent to the certain layer. Further, in each layer, the memory device 30 may be disposed on the switching device 20, or conversely, the switching device 20 may be disposed on the memory device 30.

[ memory device 30]

Fig. 2A and 2B each illustrate an example of a cross-sectional configuration of the memory cell 10 in the memory cell array 1. The memory device 30 comprises an intermediate electrode 23, a second electrode 32 and a memory layer 31. The second electrode 32 faces the intermediate electrode 23. The memory layer 31 is disposed between the intermediate electrode 23 and the second electrode 32. The memory layer 31 has, for example, a stacked structure in which a resistance change layer and an ion source layer are stacked from the intermediate electrode 23 side, or a single-layer structure having a resistance change layer.

The ion source layer contains a movable element that forms a conduction path in the resistance change layer in response to electric field application. Examples of the movable element include transition metal elements, aluminum (Al), copper (Cu), and chalcogen elements. Examples of chalcogens include tellurium (Te), selenium (Se), and sulfur (S). Examples of the transition metal element include elements of groups 4 to 6 of the periodic table, such as titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W). The ion source layer contains one or two or more of the above-described movable elements. In addition, the ion source layer may contain oxygen (O), nitrogen (N), elements other than the above-described movable elements, such as manganese (Mn), cobalt (Co), iron (Fe), nickel (Ni), and platinum (Pt), silicon (Si), and other elements.

The resistance change layer is made of, for example, an oxide of a metal element or a non-metal element, or a nitride of a metal element or a non-metal element. When a predetermined voltage is applied between the intermediate electrode 23 and the second electrode 32, the resistance value of the resistance variable layer changes. For example, when a voltage is applied between the intermediate electrode 23 and the second electrode 32, the transition metal element contained in the ion source layer moves into the resistance change layer to form a conduction path, which decreases the resistance of the resistance change layer. In addition, structural defects (such as oxygen defects and nitrogen defects) occur in the resistance change layer to form a conduction path, which reduces the resistance of the resistance change layer. In addition, when a voltage is applied in a direction opposite to the direction of the voltage applied when the resistance of the variable resistance layer decreases, the conduction path is broken or the conductivity changes to increase the resistance of the variable resistance layer.

Note that the metal element and the nonmetal element contained in the resistance change layer are not necessarily both in an oxidized state and may be partially oxidized. Further, it is sufficient that the initial resistance value of the resistance change layer realizes a device resistance of, for example, about several M Ω to about several hundreds G Ω, and the film thickness of the resistance change layer may preferably be, for example, about 1nm to about 10nm, but the optimum value thereof varies depending on the size of the device and the resistance value of the ion source layer.

Further, in the memory cell array 1 of the present embodiment, the memory device 30 is not limited to the above-described configuration. The memory device 30 may have any memory form such as one-time programmable (OTP) memory that uses fuses and antifuses and can be written only once, unipolar phase change memory PCRAM, and magnetic memory that uses magnetoresistive devices.

The intermediate electrode 23 may also serve as an electrode of the switching device 20, or may be provided separately from the electrode of the switching device 20. The second electrode 32 may also function as a word line WL or a bit line BL, or may be provided separately from the word line WL and the bit line BL. In the case where the second electrode 32 is provided separately from the word line WL and the bit line BL, the second electrode 32 is electrically coupled to the word line WL or the bit line BL. The second electrode 32 is made of a wiring material used for a semiconductor process. The second electrode 32 includes, for example, tungsten (W), tungsten nitride (WN), titanium nitride (TiN), carbon (C), copper (Cu), aluminum (Al), molybdenum (Mo), tantalum (Ta), tantalum nitride (TaN), titanium Tungsten (TiW), silicide, or the like.

The intermediate electrode 23 is preferably made of a material that prevents the chalcogen element contained in the switching layer 22 and the ion source layer from diffusing in response to application of an electric field. This is because, for example, the ion source layer contains a transition metal element as an element that allows a memory operation and maintains a written state, and when such a transition metal element diffuses into the switching layer 22 in response to application of an electric field, there is a possibility that switching characteristics deteriorate. Thus, the intermediate electrode 23 preferably contains a barrier material having barrier properties against diffusion of the transition metal element and ion conduction. Examples of the barrier material include tungsten (W), tungsten nitride (WN), titanium nitride (TiN), carbon (C), copper (Cu), aluminum (Al), molybdenum (Mo), tantalum (Ta), tantalum nitride (TaN), titanium Tungsten (TiW), and silicide.

[ switching device 20]

The switching device 20 comprises a first electrode 21, an intermediate electrode 23 and a switching layer 22. The intermediate electrode 23 faces the first electrode 21. The switching layer 22 is disposed between the first electrode 21 and the intermediate electrode 23. The first electrode 21 and the intermediate electrode 23 correspond to specific examples of "first electrode" and "second electrode" of the present disclosure, respectively. The first electrode 21 may also function as a bit line BL, or may be provided separately from the bit line BL. In the case where the first electrode 21 is provided separately from the bit line BL, the first electrode 21 is electrically coupled to the bit line BL. Note that, in the case where the switching device 20 is provided close to the word line WL, the first electrode 21 may also serve as the word line WL, or may be provided separately from the word line WL. In the case where the first electrode 21 is provided separately from the word line WL, the first electrode 21 is electrically coupled to the word line WL.

The intermediate electrode 23 may also serve as an electrode of the memory device 30, or may be provided separately from the electrode of the memory device 30. In the case where the intermediate electrode 23 is provided separately from the electrode of the memory device 30, the intermediate electrode 23 is electrically coupled to the electrode of the memory device 30. The first electrode 21 is made of a wiring material used for a semiconductor process. The first electrode 21 includes, for example, tungsten (W), tungsten nitride (WN), titanium nitride (TiN), carbon (C), copper (Cu), aluminum (Al), molybdenum (Mo), tantalum (Ta), tantalum nitride (TaN), titanium Tungsten (TiW), silicide, or the like. In the case where the first electrode 21 is made of a material in which ion conduction is likely to occur in response to an electric field, such as Cu, the surface of the first electrode 21 including, for example, Cu may be coated with a barrier material in which ion conduction and heat dissipation are difficult to occur. Examples of barrier materials in which ion conduction and heat dissipation are difficult to occur include tungsten (W), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN).

The switching layer 22 contains an element of group 16 of the periodic table, specifically, one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S). In the switching device 20 having the OTS phenomenon, the switching layer 22 preferably stably maintains an amorphous structure even when receiving application of a voltage bias for switching. As the amorphous structure becomes more stable, it is possible to stably generate the OTS phenomenon. In addition to the above-described chalcogen element, the switching layer 22 preferably contains one or more elements selected from boron (B), aluminum (Al), gallium (Ga), carbon (C), silicon (Si), germanium (Ge), nitrogen (N), phosphorus (P), arsenic (As), antimony (Ab), and bismuth (Bi). In addition to the above-described chalcogen element, the switching layer 22 more preferably further contains one or more elements selected from boron (B), carbon (C), silicon (Si), and nitrogen (N). The switching layer 22 preferably contains any one of BTe, CTe, BCTe, CSiTe, BSiTe, BCSiTe, BTeN, CTeN, BCTeN, CSiTeN, BSiTeN, and BCSiTeN.

When an element having a relatively small atomic radius is added to an element having a relatively large atomic radius, the difference between the atomic radii of the constituent elements becomes large, and the crystal structure is not easily formed accordingly, so that it is easier to stabilize the amorphous structure. Thus, in the case where an element having a relatively small atomic radius, such as boron (B), is added to a layer containing a chalcogen element having a relatively large atomic radius, such as Te, a plurality of elements having different atomic radii are contained in the layer, as with the switching layer 22, which stabilizes an amorphous structure.

Boron (B) has low conductivity among semimetals, even when used alone, in particular. Therefore, boron (B) is included in the switching layer 22, which increases the resistance value of the switching layer 22. In addition, boron (B) has a small atomic radius compared to chalcogen elements. Therefore, boron (B) is included in the switching layer 22, which stabilizes the amorphous structure of the switching layer 22 and stably generates the OTS phenomenon.

Carbon (C) makes it possible to increase the resistance of the switching layer 22 in a structure other than a structure including an sp2 orbital observed in graphite or the like. In addition, carbon (C) has a small ion radius compared to chalcogen elements, which stabilizes the amorphous structure of the switching layer 22 and stably generates the OTS phenomenon.

Nitrogen (N) is bonded to one of boron (B), carbon (C), and silicon (Si). Therefore, in the switching layer 22, nitrogen (N) and one of boron (B), carbon (C), and silicon (Si) in the switching layer 22 increase the resistance value of the switching layer 22. For example, the a-BN band gap as a bonding of nitrogen (N) and boron (B) is 5.05 even in an amorphous state. As described above, in the case where nitrogen (N) is contained in the switching layer 22, the resistance value of the switching layer 22 is larger than that in the case where nitrogen (N) is not contained in the switching layer 22, thereby reducing the leakage current. Further, dispersing the bonding of nitrogen (N) and one of boron (B), carbon (C), and silicon (Si) into the switching layer 22 stabilizes the amorphous structure.

The switching layer 22 is changed to a low resistance state by increasing the applied voltage to a predetermined threshold voltage (switching threshold voltage) or higher, and the switching layer 22 is changed to a high resistance state by decreasing the applied voltage to a voltage lower than the above threshold voltage (switching threshold voltage). In other words, the amorphous structure of the switching layer 22 is stably maintained regardless of the application of a voltage pulse or a current pulse from a power supply circuit (pulse applicator), not shown, through the first electrode 21 and the intermediate electrode 23. Also, even after the applied voltage is removed, the switching layer 22 does not perform a memory operation such as retention of a conductive path formed by ion movement in response to the voltage application.

Fig. 3 illustrates an example of a cross-sectional configuration of the switching device 20 and its periphery in the memory cell array 1. The memory cell 10 includes a diffusion suppression layer 14 that is in contact with at least one side surface of the switching layer 22 as shown in fig. 3, among side surfaces of the switching device 20 and the memory device 30. The diffusion suppression layer 14 is provided at a position different from the region between the switching layer 22 and the first electrode 21 and the region between the switching layer 22 and the intermediate electrode 23. The diffusion-inhibiting layer 14 includes a material that inhibits diffusion of oxygen into the switching layer 22. The diffusion reducing layer 14 comprises an insulating nitride, an insulating carbide or an insulating boride. The diffusion suppression layer 14 includes a single layer or a stacked layer of two or more selected from, for example, one of silicon nitride (SiN), tantalum nitride (TaN), silicon carbide (SiC), silicon carbonitride (SiCN), aluminum nitride (AlN), Boron Nitride (BN), and Boron Carbonitride (BCN). The diffusion suppression layers 14, 23, and 24 cover the switching layer 22, and suppress diffusion of oxygen into the switching layer 22.

Fig. 4A and 4B each illustrate an example of a cross-sectional configuration of a portion of the switching device 20 of fig. 2A and the periphery thereof. Fig. 5A and 5B each illustrate an example of a cross-sectional configuration of a portion of the switching device 20 of fig. 2B and the periphery thereof. Fig. 4A and 5A each illustrate an example of a cross section of the memory cell array 1 when viewed from a direction in which the bit line BL or the word line WL extends in the depth direction. Fig. 4B illustrates an example of a cross-section along line a-a in fig. 4A. Fig. 5B illustrates an example of a cross-section along line a-a in fig. 5A. In fig. 4A, 4B, 5A, and 5B, it is assumed that the first electrode 21 also functions as a bit line BL or a word line WL, and the first electrode 21 has a small width so as to be in contact with only a portion of the top surface or the bottom surface of the switching layer 22. In this case, any portion of the top surface or the bottom surface of the switching layer 22 is in contact with a member (such as the interlayer insulating film 13) other than the first electrode 21. At this time, oxygen is likely to diffuse into the switching layer 22 through a portion of the top surface or the bottom surface of the switching layer 22 that is in contact with a member other than the first electrode 21. Therefore, in the case where the area in contact with the switching layer 22 in the surface of the first electrode 21 is smaller than the area in contact with the first electrode 21 in the surface of the switching layer 22, each memory cell 10 preferably includes the diffusion suppression layer 15. The diffusion suppression layer 15 is provided to cover a portion not in contact with the first electrode 21 among the surface of the switching layer 22 in contact with the first electrode 21. The diffusion suppression layer 15 is in contact with a portion of the surface of the switching layer 22 that is not in contact with the first electrode 21, and is made of a material that suppresses diffusion of oxygen into the switching layer 22. The diffusion suppressing layer 15 includes an insulating nitride or an insulating carbide (carbide). The diffusion suppression layer 14 includes a single layer or a stacked layer of two or more selected from, for example, one of silicon nitride (SiN), tantalum nitride (TaN), silicon carbide (SiC), silicon carbonitride (SiCN), aluminum nitride (AlN), Boron Nitride (BN), and Boron Carbonitride (BCN).

In fig. 4A and 5A, the interlayer insulating film 13 may be made of a material common to the material of the diffusion suppressing layer 15. Also, in the case where the area in contact with the switching layer 22 in the surface of the intermediate electrode 23 is smaller than the area in contact with the intermediate electrode 23 in the surface of the switching layer 22, each memory cell 10 preferably includes the diffusion suppression layer 15. The diffusion suppression layer 15 is provided so as to cover a portion of the surface of the switching layer 22 that is in contact with the intermediate electrode 23, which is not in contact with the intermediate electrode 23. Here, the diffusion suppression layer 15 is in contact with a portion of the surface of the switching layer 22 that is not in contact with the intermediate electrode 23.

Each of the first electrode 21 and the intermediate electrode 23 is preferably made of a metal material that suppresses diffusion of oxygen into the switching layer 22. Specifically, each of the first electrode 21 and the intermediate electrode 23 preferably includes a single-layer film of one kind or an alloy layer film or a stacked-layer film of two or more kinds selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), zirconium (Zr), zirconium nitride (ZrN), hafnium (Hf), hafnium nitride (HfN), tantalum oxide (TaN), tungsten (W), tungsten nitride (WN), platinum (Pt), gold (Au), ruthenium (Ru), and iridium (Ir).

Fig. 6 illustrates a modification of the cross-sectional configuration of the switching device 20. The switching device 20 further includes diffusion suppression layers 24 and 25 sandwiching the switching layer 22. The diffusion suppression layer 24 is provided between the first electrode 21 and the switching layer 22, and is in contact with the surface of the switching layer 22. The diffusion suppression layer 25 is provided between the intermediate electrode 23 and the switching layer 22, and is in contact with the surface of the switching layer 22. Each of the diffusion-suppressing

layers

24 and 25 is made of a material that suppresses diffusion of oxygen into the switching layer 22. Each of the diffusion suppression layers 24 and 25 includes a single-layer film or an alloy layer film or a stacked-layer film of two or more kinds selected from, for example, one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), zirconium (Zr), zirconium nitride (ZrN), hafnium (Hf), hafnium nitride (HfN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), platinum (Pt), gold (Au), ruthenium (Ru), and iridium (Ir). In the case where the material configurations of the diffusion-suppressing

layers

24 and 25 are different from each other, the thicknesses of the diffusion-suppressing

layers

24 and 25 may be different from each other. In the case where the first electrode 21 and the intermediate electrode 23 are made of a material different from the material of the diffusion suppression layers 24 and 25, the diffusion suppression layers 24 and 25 are preferably made of a material having a high effect of suppressing diffusion of oxygen into the switching layer, as compared with the material of the first electrode 21 and the intermediate electrode 23. The first electrode 21 and the intermediate electrode 23 may be made of a material common to the materials of the

diffusion suppressing layers

24 and 25. In this case, the diffusion-suppressing layer 24 constitutes a part of the first electrode 21, and the diffusion-suppressing layer 25 constitutes a part of the intermediate electrode 23.

In the case where the first electrode 21 and the intermediate electrode 23 are made of an electrode material different from the materials of the diffusion suppression layers 24 and 25, the film thickness of each of the diffusion suppression layers 24 and 25 is desirably in the range of 0.1nm to 500nm in terms of oxygen diffusion suppression effect and process. In the case where each of the diffusion suppression layers 24 and 25 is made of a material having relatively high resistance, such as hafnium nitride (HfN), zirconium nitride (ZrN), and tantalum nitride (TaN), the film thickness of each of the diffusion suppression layers 24 and 25 is preferably adjusted so that the diffusion suppression layers 24 and 25 are thinned, for example, in the range of about 0.1nm to about 10 nm.

The diffusion suppression layers 24 and 25 may each be an insulating film such as a film of silicon nitride (SiN). In this case, it is preferable that each of the

diffusion suppressing layers

24 and 25 is sufficiently thin so as not to affect the switching characteristics of the switching device 20. The diffusion suppression layers 24 and 25 are preferably silicon nitride (SiN) films each having a film thickness of, for example, 0.1nm to 5 nm.

Fig. 7A, 7B, and 7C each illustrate a modification of the cross-sectional configuration of a part of the memory cell array 1, and illustrate an example of combining the above-described configurations. Fig. 7A illustrates an example of a cross-sectional configuration of the memory cell 10 including the switching device 20 having the configuration of fig. 4A and the periphery thereof. Fig. 7B illustrates an example of a cross-sectional configuration of the memory cell 10 and its periphery when the diffusion reducing layer 14 is applied to the sidewalls of the memory device 30. Fig. 7C illustrates an example of a cross-sectional configuration of the memory cell 10 and its periphery when the diffusion suppression layer 15 is removed from the memory cell array 1 of fig. 7B. As for those examples, the diffusion suppression layer 14 is disposed between the switching layer 22 and the interlayer insulating film 13, which suppresses diffusion of oxygen from the interlayer insulating film 13 into the switching layer 22. In particular, in the case where the interlayer insulating film 13 includes an oxide (such as SiOx), disposing the diffusion suppression layer 14 between the switching layer 22 and the interlayer insulating film 13 suppresses diffusion of oxygen from the interlayer insulating film 13 into the switching layer 22. Note that, in terms of suppressing diffusion of oxygen into the switching layer 22, it is preferable that the switching layer 22 is in contact with only a layer other than an oxide, as shown in fig. 7A and 7B.

[ IV characteristics of memory cell 10 ]

Next, the IV characteristic of the memory cell 10 is described. Fig. 8 to 11 each illustrate a relationship between an applied voltage and a value of a current flowing through an electrode at the time of writing (e.g., forward bias) and erasing (e.g., reverse bias) of the memory cell 10. The solid line indicates the IV characteristic when the voltage is applied, and the dotted line indicates the IV characteristic when the applied voltage is scanned in the decreasing direction.

Fig. 8 illustrates the IV characteristic of the switching device 20. When a forward bias voltage (a write voltage in this case) is applied to the switching device 20, the current in the switching device 20 increases as the applied voltage increases. When the current exceeds a predetermined threshold voltage (switching threshold voltage), the current sharply increases or the resistance decreases by the OTS operation, thereby placing the switching device 20 in the ON state. Thereafter, when the applied voltage is decreased, the value of the current flowing through the electrode of the switching device 20 is gradually decreased. For example, depending on the material and formation conditions of the switching device 20, at a threshold voltage substantially equivalent to the increased threshold voltage, the resistance sharply increases, and the switching device 20 is accordingly placed in the OFF state. Note that "H1" in fig. 8 denotes the selection ratio of the switching device 20.

Fig. 9 illustrates the IV characteristics of the memory device 30. As can be appreciated from fig. 9, as the applied voltage increases, the current value in the memory device 30 increases. By forming a conduction path in the resistance change layer of the memory layer 31, a write operation is performed at a predetermined threshold voltage, thereby changing the memory layer 31 into a low resistance state and increasing a current. In other words, in response to the application of the write voltage, the memory device 30 becomes a low-resistance state, and maintains the low-resistance state even after the voltage application is stopped.

Fig. 10 illustrates the IV characteristic of the memory cell 10. The switching behavior of the current value of the memory cell 10 at the start of application of the write voltage and at the stop of application becomes the IV curve C1 in fig. 10, which is a combination of the IV curve a1 of the switching device 20 and the IV curve B1 of the memory device 30. In such a memory cell 10, for example, in a V/2 bias system, the read voltage (Vread) of the memory cell 10 is set to a voltage (range of arrow a in fig. 10) between voltages at two points at which the resistance sharply changes on the IV curve C1, and Vread/2 is set to a voltage half the read voltage Vread. This makes the selection ratio (ON/OFF ratio) defined by the current ratio of Vread bias to Vread/2 bias larger. Further, since the IV curve C1 of the memory cell 10 is a combination of the IV curve a1 of the switching device 20 and the IV curve B1 of the memory device 30 as described above, the selection ratio (ON/OFF ratio) becomes larger as the resistance change (or current change) before and after the threshold value of the switching device 20 is larger. Further, as the selection ratio is larger, the read margin (read margin) becomes larger, thereby making it possible to increase the cross-point array size without erroneous reading, and further increase the capacity of the memory cell array 1.

This applies not only to read operations but also to write operations. Fig. 11 illustrates the IV characteristics of the memory cell 10 similar to fig. 10. As described above, in the cross-point array, a large number of bits are coupled to the same bit line BL or word line WL as the bit line BL or word line WL of the target memory cell 10. Therefore, as shown in FIG. 11, if the leakage current biased to Vwrite/2 in the unselected state (represented by the intersection of Vwrite/2 and the IV cycle of the dashed line of the IV curve C1 in the set state) is large, there is a possibility that erroneous writing may occur in the unselected memory cell 10. Therefore, in the write operation, it is preferable to suppress the leakage current to such an extent as not to cause erroneous writing of the unselected memory cell 10 biased to Vwrite/2, while setting the write voltage Vwrite to a voltage that supplies a current necessary for writing to the memory device 30. In other words, it is possible to operate a large-sized cross-point array without involving erroneous writing because the leakage current biased to Vwrite/2 in the unselected state is small. Thus, increasing the ON/OFF ratio of the switching device 20 also during the write operation results in a large capacity of the memory cell array 1.

On the other hand, when a reverse bias voltage (in this case, an erase voltage) is applied, a change in the current value of the switching device 20 during the application of the erase voltage exhibits a behavior similar to that during the application of the write voltage (IV curve a2 of fig. 8). In contrast, by applying a voltage equal to or higher than the erase threshold voltage, the current value of the memory device 30 changes from the low resistance state to the high resistance state during the application of the erase voltage (IV curve B2 of fig. 9). In addition, a change in the current value of the memory cell 10 during the application of the erase voltage becomes a combination of the IV curve a2 of the switching device 20 and the IV curve B2 of the memory device 30, like a change in the current value during the application of the write voltage (IV curve C2 of fig. 10 or 11).

It is noted that, in the V/2 bias system, even in the case where, for example, a read bias is set to the write side, the leakage current at the time of erasing at Vreset/2 bias becomes a problem. In other words, in the case where the leakage current is large, there is a possibility that an unintended erroneous erase occurs. Therefore, as in the case of applying a positive bias, as the ON/OFF ratio of the switching device 20 becomes higher and as the leakage current in the OFF state becomes smaller, an increase in the size of the cross-point array is more favorably achieved. In other words, this results in a large capacity of the memory cell array 1.

Incidentally, as can be appreciated from fig. 8 to 11, even when the erase voltage is applied, the switching device 20, the memory device 30, and the memory cell 10 each have an IV curve similar to that when the write voltage is applied. In other words, the switching device 20, the memory device 30, and the memory cell 10 each have a bidirectional characteristic. In fact, the IV characteristics of each of the switching device 20, the memory device 30, and the memory cell 10 involve variations for each device. Therefore, a plurality of (for example, 120) memory cells 10 included in the memory cell array 1 have threshold voltage variations, for example, as schematically shown in fig. 12. Note that the black areas in fig. 12 indicate that the IV curves for each device relate to variations.

In the IV characteristic at the time of writing of fig. 12, the IV curve on the right side is the IV curve of the memory cell 10 when the switching device 20 is in the OFF state. Thus, a change in the IV curve on the right indicates a change in the threshold voltage of the memory device 30. Further, in the IV characteristic at the time of writing of fig. 12, the IV curve ON the left side is an IV curve of the memory cell 10 when the memory device 30 is in the ON state. Thus, a change in the IV curve on the left indicates a change in the threshold voltage of the switching device 20. In the IV characteristic at the time of writing of fig. 12, the gap between the IV curve on the right side and the IV curve on the left side corresponds to the read margin RM. When the read margin RM becomes large, an increase in the size of the cross-point array is more advantageously achieved. In other words, this results in a large capacity of the memory cell array 1.

[ threshold voltage variation of switching device 20]

Next, various experiments performed in order to verify the threshold voltage variation of the switching device 20 are described.

[ experiment 1]

In experiment 1, five samples (samples 01 to 05) were produced. A large number of switching devices 20 were formed on the surface of each sample. Each sample was made in the following manner. First, a plurality of MOS transistor circuits and a plurality of first electrodes 21 containing TiN are formed on a substrate while being exposed. The surface of the substrate is cleaned by reverse sputtering. Next, the Te target and the B4C target were simultaneously sputtered while flowing nitrogen gas into the chamber to form a BCTeN layer having a thickness of 20nm on the first electrode 21 containing TiN. Subsequently, a W layer having a thickness of 30nm was formed on the surface of the BCTeN layer. Thereafter, patterning is performed to form a large number of switching devices 20 on the substrate, in which a first electrode 21 containing TiN, a switching layer 22 composed of a BCTeN layer, and an intermediate electrode 23 composed of a W layer are stacked. The sample thus prepared was subjected to a heat treatment at 320 ℃ for 2 hours. In experiment 1, the degree of vacuum in the chamber was changed for each sample as shown in fig. 13. Note that, in order to change the degree of vacuum in the chamber, the sputtering apparatus was changed for each sample.

XPS analysis was performed on each sample manufactured in the above manner to find the composition of the corresponding element of the switching device 20 in each sample. As a result, it was confirmed that the proportions of the respective elements other than oxygen were the same among the respective samples. The oxygen content of the switching device 20 in the corresponding sample is shown in fig. 14. As can be seen from fig. 14, the oxygen content of the switching device 20 becomes larger as the degree of vacuum in the chamber becomes larger.

Next, the gate voltage of the transistor provided in each sample was adjusted for each sample so that the maximum current for 120 switching devices 20 became 80mA and the source-drain voltage was increased from 0V by 0.1V to 6V to measure the voltage at which the resistance sharply changed. Fig. 15 illustrates measurement results obtained from 120 switching devices 20 provided in a sample 05. It is confirmed from fig. 16 that a similar IV curve is obtained regardless of whether the voltage applied to the switching device 20 is a positive voltage or a negative voltage, and the switching device 20 has a bidirectional characteristic. Further, it is found that the threshold voltages of the 120 switching devices 20 have a variation Δ Vth1 regardless of whether the voltage applied to the switching devices 20 is a positive voltage or a negative voltage.

Next, the standard deviation of the threshold voltage variation of the 120 switching devices 20 obtained for each sample was determined. Fig. 16 illustrates the determined standard deviation plotted for each sample in the graph, where the horizontal axis indicates oxygen content and the vertical axis indicates the standard deviation of the threshold voltage change. It is found from fig. 16 that the threshold voltage variation becomes larger as the oxygen content becomes larger. In other words, it was found that the oxygen content of the switching device 20 increased as the degree of vacuum in the chamber before film formation decreased, and the threshold voltage variation deteriorated accordingly. In particular, it can be recognized that the threshold voltage variation is drastically deteriorated at an oxygen content with 5 at% as a boundary. In a certain film-forming apparatus, film formation is performed in a chamber at a vacuum degree of about 1.0E-5 Pa; however, when film formation starts at about that degree of vacuum, the oxygen content exceeds 5 at% and the threshold voltage variation is accordingly greatly deteriorated. Therefore, in order to further reduce the oxygen content and to suppress the threshold voltage variation, film formation is preferably performed with the degree of vacuum in the chamber before film formation set to 1.0E-6Pa or in a more favorable state. This suppresses the oxygen content of the switching layer 22 to 5 at% or less, thereby suppressing the threshold voltage variation of the switching device 20 to be low. Further, as a method to be performed for reducing the oxygen content before film formation, it is expected that pre-sputtering of an object to be used, electric discharge of an oxygen-absorbing getter material, baking of a chamber, and the like are sufficiently performed.

Although not necessarily clear, the presence of even small amounts of oxygen in chalcogenide materials, such as BCTeN, may cause bonding of oxygen to Te or any other element and partial segregation of the bonded elements, which may begin to cause threshold voltage variations. When the oxygen content exceeds 5 at%, the Te — O bonding rate and the bonding rate of any other element and oxygen may also increase, causing large segregation in a wide region of the chalcogenide material, which may result in a sharp increase in threshold voltage variation. In fact, it can be recognized that according to the TEM photograph of the BCTeN layer shown in fig. 17 (in which the oxygen content is 7 at%), segregation occurs in the entire BCTeN layer. Thus, it can be assumed that the switching device characteristics (such as the threshold voltage) become more stable and the threshold voltage variation decreases more as the oxygen content becomes smaller.

The switching device characteristics are obtained from the OTS characteristics of the chalcogen element (Te). Therefore, the switching device characteristics can be obtained not only by the combination of one of B, C and N with any other element, but also by the combination of a chalcogen element with any other element. Thus, it can be understood that the threshold voltage variation becomes larger as the amount of oxygen increases with respect to the chalcogen element (Te). Examples of the elements constituting the material of the switching device include elements of group 13 (B, Al and Ga), elements of group 14 (C, Si and Ge), and elements of group 15 (N, P, As, Sb, and Bi). The use of these elements prevents the resistance from being greatly lowered. In addition, the adjustment of the composition of the combination of the execution element and the chalcogen element makes it possible to obtain switching device characteristics that allow the resistance value not to be maintained. Examples of switching device materials that achieve such switching device characteristics include GaTeN, GeTeN, and AsGeSiNTe. In addition, a transition metal element (such as Ti, Zr, and Hf) and/or other metal elements (such as Mg and Gd) may be added to the chalcogen element to such an extent that the characteristics of the switching device are not impaired. Examples of such switching device materials include MgBTeN. Reducing the oxygen contained in the switching device material having a combination of these elements with the chalcogen element as much as possible makes it possible to make the threshold voltage variation small.

[ experiment 2]

In experiment 2, two samples (samples 06 and 07) were made. A large number of switching devices 20 are formed on the surface of each sample. Each sample was made in the following manner. Sample 06 is described first. Upon exposure, a plurality of MOS transistor circuits and a plurality of first electrodes 21 containing TiN are formed on the substrate. The surface of the substrate is cleaned by reverse sputtering. Thereafter, a SiNx layer was formed on the first electrode 21 containing TiN by sputtering. Thereafter, the sample 06 was taken out of the chamber to the atmosphere once, and then the sample 06 was put in a photolithography processing step to form a contact hole on the SiNx layer. Thereafter, the surface of the sample 06 was cleaned by reverse sputtering, and then a TiN layer having a thickness of 10nm was formed in the contact hole. Subsequently, while flowing nitrogen gas into the chamber, a BCTeN layer having a thickness of 20nm was formed on the surface of the TiN layer, and a W layer having a thickness of 30nm was further formed on the surface of the BCTeN layer by sputtering. The composition of the BCTeN layer at this time was the same as that in experiment 1. Thereafter, patterning is performed to form a large number of switching devices 20 on the substrate, in which a first electrode 21 containing TiN, a switching layer 22 composed of a BCTeN layer, and an intermediate electrode 23 composed of a W layer are stacked. Sample 06 having a structure in which BCTeN was sandwiched between first electrode 21 containing TiN and intermediate electrode 23 composed of a W layer and the periphery thereof was covered with SiNx was manufactured in the above-described manner. The heat treatment was performed on the sample 06 at 320 ℃ for 2 hours. Note that in the above-described process of manufacturing sample 07, a SiOx layer was formed instead of the SiNx layer.

Next, the gate voltage of the transistor provided in each sample was adjusted for each sample so that the maximum current for 120 switching devices 20 became 80mA and the source-drain voltage was increased from 0V by 0.1V to 6V to measure the voltage at which the resistance sharply changed. Next, the standard deviation of the threshold voltage variation of the 120 switching devices 20 obtained for each sample was determined. Fig. 18 illustrates the standard deviation determined for each sample. As can be seen from fig. 18, in the case where the switching device 20 is surrounded by the SiNx layer, the threshold voltage variation of the switching device 20 is reduced, and in the case where the switching device 20 is surrounded by the SiOx layer, the threshold voltage variation of the switching device 20 is increased.

In the case where oxygen is contained in a layer in contact with the switching device 20 when forming the switching device material, there is a possibility that oxygen diffuses into the switching device material due to high temperature or heat treatment during film formation or a process of increasing the oxygen content. According to experiment 1, in the case where the oxygen content in the switching device material BCTeN was 5 at% or less, the threshold voltage variation became less than 0.1. In contrast, in the case of using the SiNx layer as the interlayer film in experiment 2, it is assumed that the oxygen content of the switching device material is 5 at% or less at any position. However, in the case where the SiOx layer was used as the interlayer film in experiment 2, oxygen diffuses from the interlayer film into the switching device 20, which increases the oxygen content of the surface of the switching device material in contact with the SiOx layer or the oxygen content of the switching device material as a whole to 5 at% or more. This may result in a relatively easy occurrence of segregation due to bonding of oxygen with Te or any other element and an occurrence of a change in threshold voltage.

[ experiment 3]

In experiment 3, two samples (samples 08 and 09) were made. A large number of switching devices 20 were formed on the surface of each sample. Each sample was made in the following manner. Sample 08 is described first. Upon exposure, a plurality of MOS transistor circuits and a plurality of first electrodes 21 containing TiN are formed on the substrate. The surface of the substrate is cleaned by reverse sputtering. Thereafter, while flowing nitrogen gas into the chamber, a BCTeN layer was formed on the first electrode 21 containing TiN, and a W layer was formed on the surface of the BCTeN layer. Thereafter, patterning is performed to form a large number of switching devices 20 on the substrate, in which a first electrode 21 containing TiN, a switching layer 22 composed of a BCTeN layer, and an intermediate electrode 23 composed of a W layer are stacked. Finally, each switching device 20 is entirely covered by a SiN layer. The treatment is performed in such a way that the switching layer is not in contact with air and oxygen at all during these treatment steps. The sample 08 thus manufactured was subjected to a heat treatment at 320 ℃ for 2 hours. It is to be noted that sample 09 was fabricated by entirely covering each switching device 20 with a SiNx layer after a large number of switching devices 20 formed on a substrate had been subjected to processing steps using oxygen (such as atmospheric exposure and ashing in the above-described processing).

Fig. 19 illustrates a TEM photograph of sample 08. Fig. 20 illustrates a TEM photograph of sample 09. Fig. 21 illustrates the threshold voltage variation of the switching device 20 of the corresponding sample. It was found that no oxide film was formed around the switching device 20 in fig. 19, but an oxide film was formed around the switching device 20 in fig. 20. The oxide film is an oxide of Si and an element contained in the switching device 20. This means that oxide is generated between the switching layer 22 and the interlayer insulating film 13 due to exposure of the switching device 20 to oxygen through atmospheric exposure or exposure to oxygen in an ashing step for register movement in the middle of the process, even when SiNx is used for the interlayer insulating film 13. It is found from fig. 21 that the threshold voltage variation of the switching device 20 of sample 08 is extremely smaller than that of the switching device 20 of sample 09. Thus, in the case where an oxide film is thus present around the switching layer 22 and in contact with the switching layer 22, there is a possibility that the threshold voltage variation of the switching device 20 is greatly deteriorated regardless of whether the oxide film is intentionally formed as in experiment 2 or unintentionally formed by processing as in experiment 3. Therefore, manufacturing a device structure in which the periphery of the switching device 20 is in contact with only a layer other than the oxide film makes it possible to make the threshold voltage variation small.

Next, the effect of the memory cell array 1 according to the present embodiment is described.

As a result of experiment 2, in the case where an oxide is used for a layer in contact with the switching device 20, the oxygen content of the switching device 20 increases and the threshold voltage variation of the switching device 20 increases accordingly. Therefore, in the case of forming an insulating layer covering the memory cell 10, using a nitride layer such as SiNx instead of an oxide layer such as SiOx as the insulating layer makes it possible to suppress the oxygen content of the switching device 20 to 5 at% or less and suppress an increase in the threshold voltage variation of the switching device 20. Further, in the case where the interlayer insulating film 13 contains a large amount of oxide or oxygen, providing the diffusion suppression layer 14 on the side surface of the switching device 20 to prevent the interlayer insulating film 13 from being in direct contact with the side surface of the switching device 20 makes it possible to suppress the oxygen content of the switching device 20 to 5 at% or less and suppress an increase in the variation in the threshold voltage of the switching device 20.

In the case where, for example, the switching layer 22 is used in combination with a PRAM (in which oxygen is used in the memory device 30) or in combination with a PCM memory material (in which oxygen is added), the oxygen content of the switching layer 22 may be increased due to diffusion of oxygen from electrodes (the first electrode 21 and the intermediate electrode 23) above and below the switching layer 22. Further, since the interlayer insulating film 13 is used in the memory cell array 1, there is similarly a possibility of diffusion of oxygen in the up-down direction. However, even in this case, when at least the upper and lower electrodes (the first electrode 21 and the intermediate electrode 23) of the switching layer 22 are each made of a metal material that inhibits diffusion of oxygen into the switching layer 22 in the present embodiment, it is possible to inhibit diffusion of oxygen into the switching layer 22. Therefore, it is possible to allow the oxygen content of the switching device 20 to be 5 at% or less and suppress an increase in the threshold voltage variation of the switching device 20. Further, in the case where the diffusion suppression layers 24 and 25 are provided between the switching layer 22 and the first electrode 21 and between the switching layer 22 and the intermediate electrode 23, respectively, in the present embodiment, it is also possible to suppress diffusion of oxygen into the switching layer 22. This makes it possible to allow the oxygen content of the switching device 20 to be 5 at% or less and suppress an increase in the threshold voltage variation of the switching device 20.

In addition, in the case of the structure in which the first electrode 21 and the second electrode 32 are embedded in the interlayer insulating film 13, when the switching layer 22 is in direct contact with the first electrode 21, a part of the top surface or the bottom surface of the switching layer 22 may sometimes not be covered with the first electrode 21. In particular, when the line width of the first electrode 21 is small, a portion of the top surface or the bottom surface of the switching layer 22 may sometimes not be covered with the first electrode 21. Even in this case, in the case where the diffusion suppression layer 15 is provided between the switching layer 22 and the interlayer insulating film 13 in this embodiment so as to prevent the switching layer 22 from directly contacting the interlayer insulating film 13, it is possible to suppress diffusion of oxygen into the switching layer 22. Therefore, this makes it possible to allow the oxygen content of the switching device 20 to be 5 at% or less and suppress an increase in the threshold voltage variation of the switching device 20.

<2. modification >

Some modifications of the memory cell array 1 according to the above-described embodiment are described below. Note that, hereinafter, the components common to those of the above-described embodiment are denoted by the same reference numerals as those of the above-described embodiment. Further, components different from the above-described embodiment are mainly described, and any description of components common to the components of the above-described embodiment is omitted as appropriate.

[ modification A ]

Fig. 22 illustrates a modification of the memory cell array 1 according to the above-described embodiment. In the present modification, in the memory cell array 1, the switching device 20 is disposed in contact with the bit line BL, and is disposed not only at the intersection but also in an expanding manner in the extending direction of the bit line BL. Therefore, it is possible to form a switching device layer or a memory device layer at the same time as a layer which eventually becomes a bit line BL or a word line WL, and to perform shaping collectively by photolithography, which allows reduction in processing steps. In the present modification, the layers (for example, the first electrode 21, the intermediate electrode 23, and the interlayer insulating film 13 around them) that are in direct contact with the switching layer 22 are each composed of a material that suppresses diffusion of oxygen into the switching layer 22. This makes it possible to allow the oxygen content of the switching device 20 to be 5 at% or less and suppress an increase in the threshold voltage variation of the switching device 20.

[ modification B ]

Fig. 23 illustrates a modification of the memory cell array 1 according to the above-described embodiment. In the present modification, the diffusion suppression layers 14, 15, 24, and 25 are not provided, and the switching layer 22 is in direct contact with the interlayer insulating film 13 and other layers. In the present modification, the layers (e.g., the first electrode 21, the intermediate electrode 23, and the interlayer insulating film 13) that are in direct contact with the switching layer 22 are each composed of a material that suppresses diffusion of oxygen into the switching layer 22. This makes it possible to allow the oxygen content of the switching device 20 to be 5 at% or less and suppress an increase in the threshold voltage variation of the switching device 20. Note that, in the present modification, it is preferable to perform a manufacturing process similar to the above-described manufacturing process of the samples 01 to 03 in experiment 1 when forming the switching device 20. This makes it possible to allow the oxygen content of the switching device 20 to be 5 at% or less and suppress an increase in the threshold voltage variation of the switching device 20.

[ modification C ]

In the above-described embodiment and modifications a and B, the word lines WL or the bit lines BL may extend in the stacking direction of the memory cell array 1. In this case, each word line WL and each bit line BL face each other in the stacking plane direction of the memory cell array 1, and the switching device 20 and the memory device 30 included in each memory cell 10 are thus coupled in series to each other in the stacking plane direction of the memory cell array 1.

Hereinabove, although the present technology has been described by referring to the embodiments and modifications a to C, the present technology is not limited to the above-described embodiments and modifications, and various modifications may be made. It is to be noted that the effects described in this specification are merely illustrative. The effects achieved by the present technology are not limited to the effects described in the present specification. The present technology may have other effects than those described in the present specification.

Further, for example, the present technology may also have the following configuration.

(1) A switching device, comprising:

a first electrode;

a second electrode facing the first electrode;

a switching layer disposed between the first electrode and the second electrode and including one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S); and

a diffusion suppression layer that is in contact with at least a portion of a surface of the switching layer and suppresses diffusion of oxygen into the switching layer.

(2) The switching device according to (1), wherein the switching layer is changed to the low-resistance state by increasing the applied voltage to a predetermined threshold voltage or more, and the switching layer is changed to the high-resistance state by decreasing the applied voltage to a voltage lower than the threshold voltage.

(3) The switching device according to (1) or (2), wherein the diffusion suppression layer is provided at a position different from a region between the first electrode and the switching layer or a region between the second electrode and the switching layer, and contains one of an insulating nitride, an insulating carbide, and an insulating boride.

(4) The switching device according to (3), wherein the diffusion suppressing layer comprises a single layer of one or a stacked layer of two or more selected from silicon nitride (SiN), tantalum nitride (TaN), silicon carbide (SiC), silicon carbonitride (SiCN), aluminum nitride (AlN), Boron Nitride (BN), and Boron Carbonitride (BCN).

(5) The switching device according to (1) or (2), wherein the diffusion suppression layer is provided between the first electrode and the switching layer or between the second electrode and the switching layer.

(6) The switching device according to (5), wherein the diffusion suppressing layer comprises a single-layer film of one kind or an alloy layer film or a stacked-layer film of two or more kinds selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), zirconium (Zr), zirconium nitride (ZrN), hafnium (Hf), hafnium nitride (HfN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), platinum (Pt), gold (Au), ruthenium (Ru), and iridium (Ir).

(7) The switching device according to (5), wherein the diffusion suppressing layer is a silicon nitride (SiN) film having a thickness in the range of 0.1nm to 5 nm.

(8) The switching device according to any one of (1) to (7), wherein the first electrode and the second electrode each contain a metal material that inhibits diffusion of oxygen into the switching layer.

(9) The switching device according to (8), wherein the first electrode and the second electrode each comprise a single-layer film or an alloy layer film or a stacked layer film of two or more selected from one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), zirconium (Zr), zirconium nitride (ZrN), hafnium (Hf), hafnium nitride (HfN), tantalum oxide (TaN), tungsten (W), tungsten nitride (WN), platinum (Pt), gold (Au), ruthenium (Ru), and iridium (Ir).

(10) The switching device according to any one of (1) to (9), wherein the switching layer further contains one or more elements selected from boron (B), aluminum (Al), gallium (Ga), carbon (C), silicon (Si), germanium (Ge), nitrogen (N), phosphorus (P), arsenic (As), antimony (Ab), and bismuth (Bi).

(11) The switching device according to any one of (1) to (10), wherein the switching layer further contains one or more elements selected from boron (B), carbon (C), silicon (Si), and nitrogen (N).

(12) The switching device according to (11), wherein the switching layer comprises any one of BTe, CTe, BCTe, CSiTe, BSiTe, BCSiTe, BTeN, CTeN, BCTeN, CSiTeN, BSiTeN, and BCSiTeN.

(13) The switching device according to any one of (1) to (12), wherein an oxygen content of the switching layer is equal to or less than 5 at%.

(14) The switching device according to any one of (1) to (13), wherein the switching layer is in contact with only the non-oxide layer.

(15) A switching device, comprising:

a first electrode;

a second electrode facing the first electrode; and

a switching layer disposed between the first electrode and the second electrode and including one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), the switching layer having an oxygen content of 5 at% or less.

(16) A memory device having a plurality of memory cells, each memory cell including a memory device and a switching device directly coupled to the memory device, the switching device comprising:

a first electrode;

a second electrode facing the first electrode;

(17) A memory device having a plurality of memory cells, each memory cell including a memory device and a switching device directly coupled to the memory device, the switching device comprising:

a first electrode;

a second electrode facing the first electrode; and

This application is based on and claims priority from Japanese patent application No.2015-073054, filed 2015, 3, 31, to the patent office, the entire contents of which are incorporated herein by reference.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may be made depending on design requirements and other factors as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A switching device, comprising:

a first electrode;

a second electrode facing the first electrode;

a diffusion-suppressing layer that is in contact with at least a part of a surface of the switching layer and suppresses diffusion of oxygen into the switching layer,

wherein the switching layer is changed to a low resistance state by increasing the applied voltage to a predetermined threshold voltage or more, and the switching layer is changed to a high resistance state by decreasing the applied voltage to a voltage lower than the threshold voltage.

2. The switching device according to claim 1, wherein the diffusion suppressing layer is provided at a position different from a region between the first electrode and the switching layer or a region between the second electrode and the switching layer, and includes one of an insulating nitride, an insulating carbide, and an insulating boride.

3. The switching device according to claim 2, wherein the diffusion suppressing layer comprises a single layer of one selected from silicon nitride (SiN), tantalum nitride (TaN), silicon carbide (SiC), silicon carbonitride (SiCN), aluminum nitride (AlN), Boron Nitride (BN), and Boron Carbonitride (BCN), or a stacked layer of two or more thereof.

4. The switching device of claim 1, wherein a diffusion inhibiting layer is disposed between the first electrode and the switching layer or between the second electrode and the switching layer.

5. The switching device according to claim 4, wherein the diffusion suppressing layer comprises a single-layer film of one selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), zirconium (Zr), zirconium nitride (ZrN), hafnium (Hf), hafnium nitride (HfN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), platinum (Pt), gold (Au), ruthenium (Ru), and iridium (Ir), or an alloy layer film or a stacked layer film of two or more thereof.

6. The switching device according to claim 4, wherein the diffusion suppressing layer is a silicon nitride (SiN) film having a thickness in a range of 0.1nm to 5 nm.

7. The switching device of claim 1, wherein the first electrode and the second electrode each comprise a metallic material that inhibits diffusion of oxygen to the switching layer.

8. The switching device according to claim 7, wherein the first electrode and the second electrode each comprise a single-layer film selected from one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), zirconium (Zr), zirconium nitride (ZrN), hafnium (Hf), hafnium nitride (HfN), tantalum oxide (TaN), tungsten (W), tungsten nitride (WN), platinum (Pt), gold (Au), ruthenium (Ru), and iridium (Ir), or an alloy layer film or a stacked layer film of two or more thereof.

9. The switching device of claim 1, wherein the switching layer further comprises one or more elements selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), carbon (C), silicon (Si), germanium (Ge), nitrogen (N), phosphorus (P), arsenic (As), antimony (Ab), and bismuth (Bi).

10. The switching device of claim 1, wherein the switching layer further comprises one or more elements selected from the group consisting of boron (B), carbon (C), silicon (Si), and nitrogen (N).

11. The switching device of claim 10, wherein the switching layer comprises any one of BTe, CTe, BCTe, CSiTe, BSiTe, BCSiTe, BTeN, CTeN, BCTeN, CSiTeN, BsiTeN, and BCSiTeN.

12. The switching device of claim 1, wherein the oxygen content of the switching layer is equal to or less than 5 at%.

13. The switching device of claim 1, wherein the switching layer is in contact with only the non-oxide layer.

14. A switching device, comprising:

a first electrode;

a second electrode facing the first electrode; and

a switching layer disposed between the first electrode and the second electrode and including one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), the switching layer having an oxygen content of 5 at% or less,

15. A memory device provided with a plurality of memory cells each including a memory device and a switching device directly coupled to the memory device, the switching device comprising:

a first electrode;

a second electrode facing the first electrode;

16. A memory device provided with a plurality of memory cells each including a memory device and a switching device directly coupled to the memory device, the switching device comprising:

a first electrode;

a second electrode facing the first electrode; and