CN107425957B - Password attack method and device and heterogeneous acceleration platform - Google Patents
Password attack method and device and heterogeneous acceleration platform Download PDFInfo
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
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- H—ELECTRICITY
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0877—Generation of secret information including derivation or calculation of cryptographic keys or passwords using additional device, e.g. trusted platform module [TPM], smartcard, USB or hardware security module [HSM]
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Abstract
The invention discloses a password attack method, a device and a heterogeneous acceleration platform, wherein the method is applied to the heterogeneous platform comprising a CPU end and an FPGA end and comprises the following steps: reading a pre-stored rainbow table and ciphertext data to be attacked by the FPGA terminal; the FPGA terminal performs parallel processing on cipher text data to be attacked according to a preset cipher attack algorithm to obtain cipher data to be selected; the FPGA terminal matches the password data to be selected with a rainbow table according to a preset matching algorithm, and searches out an alternative password; and the FPGA end returns a completion signal to the CPU end. Therefore, the hardware acceleration of the password attack algorithm is carried out by using the FPGA, and the FPGA executes the password attack algorithm in parallel, so that the parallelism of the algorithm is improved, the throughput performance during the algorithm execution is improved, and the performance of the password attack algorithm based on the rainbow table is further improved. Furthermore, the redundancy fine-grained parallelism of the FPGA end enables the hardware cost to be lower.
Description
Technical Field
The invention relates to the technical field of reconfigurable computing, in particular to an attack method, an attack device and a heterogeneous acceleration platform.
Background
With the explosive increase of data volume in the information age, the privacy and safety of information and data seriously affect the life and work of people. Password authentication is an identity authentication and system protection method which is widely applied at present.
Passwords can generally comprise passwords and secret keys, and in a specific application, defects such as too short passwords, single characters and the like easily cause security holes. Keys and passwords tend to be the main targets of rainbow table attacks.
In order to secure the information system and user authentication, the system needs to recognize a weak password and give a mark. At present, when weak passwords or attack passwords are identified through a ciphertext and a rainbow table, a performance bottleneck exists in a theoretical algorithm and a program.
Disclosure of Invention
The invention aims to provide a password attack method, a password attack device and a heterogeneous acceleration platform, and aims to solve the problem of performance bottleneck existing when the existing rainbow table identifies passwords.
In order to solve the technical problems, the invention provides the following technical scheme:
a password attack method is applied to a heterogeneous platform comprising a CPU end and an FPGA end, and comprises the following steps:
the FPGA end reads a pre-stored rainbow table and ciphertext data to be attacked;
the FPGA terminal carries out parallel processing on the ciphertext data to be attacked according to a preset password attack algorithm to obtain password data to be selected;
the FPGA terminal matches the password data to be selected with the rainbow table according to a preset matching algorithm to find out an alternative password;
and the FPGA end returns a completion signal to the CPU end.
Optionally, before the FPGA reads the pre-stored rainbow table and the ciphertext data to be attacked, the method further includes:
the CPU transmits the rainbow table and the ciphertext data to be attacked to a cache region of the FPGA end through a preset interface; setting operation parameters of the FPGA end; and sending a starting instruction to the FPGA terminal according to the operation parameters.
Optionally, the FPGA matches the password data to be selected with the rainbow table according to a preset matching algorithm, and finds out an alternative password, including:
and the FPGA end marks the password data to be selected successfully matched with the rainbow table as true according to the preset matching algorithm and takes the true as the alternative password.
Optionally, after the FPGA end returns a completion signal to the CPU end, the method further includes:
and the CPU end reads the alternative password from the cache region of the FPGA end.
Optionally, the preset interface is a PCI-E interface, and the cache area is DDR 3; the preset password attack algorithm is an algorithm described by using an OpenCL language.
A password attack device is applied to a heterogeneous platform comprising a CPU end and an FPGA end, and comprises a first reading module, a processing module, a matching module and a returning module which are integrated at the FPGA end;
the first reading module is used for reading a pre-stored rainbow table and ciphertext data to be attacked;
the processing module is used for carrying out parallel processing on the ciphertext data to be attacked according to a preset password attack algorithm to obtain password data to be selected;
the matching module is used for matching the password data to be selected with the rainbow table according to a preset matching algorithm to find out an alternative password;
the return module is used for returning a completion signal to the CPU end.
Optionally, the system further comprises a transmission module, an operation parameter setting module and a starting instruction sending module which are integrated at the CPU end;
the transmission module is used for transmitting the rainbow table and the ciphertext data to be attacked to a cache region of the FPGA end through a preset interface;
the operation parameter setting module is used for setting operation parameters of the FPGA end;
and the starting instruction sending module is used for sending a starting instruction to the FPGA terminal according to the operation parameters.
Optionally, the matching module comprises:
and the marking submodule is used for marking the password data to be selected successfully matched with the rainbow table as true according to the preset matching algorithm and taking the true as the alternative password.
Optionally, the system further comprises a second reading module integrated at the CPU end, and configured to read the alternative password from the cache area at the FPGA end.
A heterogeneous acceleration platform comprises a CPU end and an FPGA end;
the FPGA end is used for reading a pre-stored rainbow table and ciphertext data to be attacked; according to a preset password attack algorithm, parallel processing is carried out on the ciphertext data to be attacked to obtain password data to be selected; matching the password data to be selected with the rainbow table according to a preset matching algorithm, and finding out an alternative password; and returning a completion signal to the CPU end.
The invention provides a password attack method, which is applied to a heterogeneous platform comprising a CPU end and an FPGA end and comprises the following steps: reading a pre-stored rainbow table and ciphertext data to be attacked by the FPGA terminal; the FPGA terminal performs parallel processing on cipher text data to be attacked according to a preset cipher attack algorithm to obtain cipher data to be selected; the FPGA terminal matches the password data to be selected with a rainbow table according to a preset matching algorithm, and searches out an alternative password; and the FPGA end returns a completion signal to the CPU end.
Therefore, the method utilizes the FPGA to carry out the password attack based on the rainbow table, namely, the FPGA is utilized to carry out the hardware acceleration of the password attack algorithm, and the FPGA executes the password attack algorithm in parallel, so that the parallelism of the algorithm is improved, the throughput performance during the algorithm execution is improved, and the performance of the password attack algorithm based on the rainbow table is further improved. Furthermore, the redundancy fine-grained parallelism of the FPGA end enables the hardware cost to be lower. The password attack device and the heterogeneous acceleration platform provided by the invention also have the beneficial effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic flowchart of a specific implementation of a password attack method according to an embodiment of the present invention;
fig. 2 is a schematic block diagram of a structure of a password attack apparatus according to an embodiment of the present invention;
fig. 3 is a block diagram illustrating a structure of a heterogeneous acceleration platform according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic flowchart of a specific implementation of a password attack method provided in an embodiment of the present invention, where the method is specifically applied to a heterogeneous platform including a CPU end and an FPGA end, and may include the following steps:
step 101: and reading the pre-stored rainbow table and the ciphertext data to be attacked by the FPGA terminal.
It can be understood that the rainbow table and the ciphertext data to be attacked may be a cache pre-stored at the FPGA end, and specifically, the CPU end may transmit the relevant data to the FPGA end.
The FPGA end is used as a coprocessor, and the password attack algorithm performed by the FPGA end is mainly controlled by the CPU end. Therefore, in some specific embodiments, before the FPGA reads the pre-stored rainbow table and the ciphertext data to be attacked, the method may further include: the CPU transmits the rainbow table and the ciphertext data to be attacked to a cache region of the FPGA end through a preset interface; setting operation parameters of an FPGA end; and sending a starting instruction to the FPGA terminal according to the operation parameters.
It should be noted that the preset interface may be, but is not limited to, a PCI-E interface, that is, data interaction between the CPU end and the FPGA end may be performed through the PCI-E interface. The buffer on the FPGA side may be, but is not limited to, DDR 3.
The operation parameters can be obtained by the CPU terminal through corresponding setting according to the received parameter setting instruction. The operation parameters may be, for example, FPGA read-in bit number information, loop expansion size information, storage information, and the like.
After the FPGA end receives a starting instruction of the CPU end, rainbow tables and ciphertext data to be attacked are read from the DDR to the on-chip cache of the FPGA end in batches.
Step 102: and the FPGA terminal performs parallel processing on the cipher text data to be attacked according to a preset cipher attack algorithm to obtain cipher data to be selected.
It should be noted that the preset password attack algorithm may be selected according to actual requirements, that is, a corresponding password attack algorithm may be selected according to a type of ciphertext data to be attacked and the like.
The preset password attack algorithm can be described by OpenCL language, namely OpenCL is used for describing the password attack algorithm based on a rainbow table, and a host end program running at a CPU end and a Kernel program running at an FPGA end are respectively generated; secondly, performing edge processing on a host end program by using a GCC compiler to generate an executable program file which can be executed at a CPU end, and compiling the Kernel program file by using an Altera SDK for OpenCL high-level comprehensive tool to generate an executable AOCX file which can be executed at an FPGA end; and finally, running a host program at the CPU end, and calling a password attack core algorithm hardware circuit based on the rainbow table on the FPGA end to accelerate the hardware.
It can be understood that the OpenCL language is used for describing the cipher attack algorithm based on the rainbow table, and compared with the traditional RTL hardware description, the method can effectively improve the algorithm implementation efficiency and reduce the development period of the algorithm implementation.
And performing parallel processing on the password data to be attacked by using a preset password attack algorithm, for example, performing processing operations such as hash calculation and rainbow table lookup to obtain corresponding password data.
Furthermore, the parallel processing of the cipher attack algorithm based on the rainbow table is realized by utilizing the FPGA end, and the characteristic of easiness in realizing fine-grained parallel processing based on the FPGA end is realized by utilizing the FPGA end, compared with the characteristic of starting multiple threads by utilizing a CPU, the parallel processing of the cipher attack algorithm by utilizing the FPGA does not need an expensive server or cluster, namely, the hardware cost for realizing the parallel processing of the cipher attack algorithm by utilizing the FPGA is lower.
Step 103: and the FPGA terminal matches the password data to be selected with the rainbow table according to a preset matching algorithm to find out an alternative password.
After the corresponding password data is obtained through calculation, the password data can be matched with the password of the rainbow table, and then the alternative password can be obtained.
In some embodiments, the step may be specifically: and the FPGA end marks the data of the password to be selected successfully matched with the rainbow table as true according to a preset matching algorithm and takes the data as an alternative password. The data of the password to be selected is matched with the rainbow table one by one, if the matching is successful, the password is marked as true (true), and the password marked as true is used as an alternative password.
It should be noted that the preset matching algorithm may be selected according to actual requirements, and is not limited herein.
Step 104: and the FPGA end returns a completion signal to the CPU end.
When the FPGA end finishes executing all the steps and waits for the end of the data processing of the password to be processed in the cache, a completion signal can be returned to the CPU end to inform the CPU end that the current password attack algorithm is completed.
And the CPU end receives a completion signal returned by the FPGA end and can directly read the corresponding alternative password from the cache region of the FPGA end. Therefore, in some embodiments, after the FPGA end returns the completion signal to the CPU end, the method may further include: and the CPU end reads the alternative password from the cache region of the FPGA end.
According to the password attack method provided by the embodiment, the FPGA is used for performing the password attack based on the rainbow table, namely the FPGA is used for performing hardware acceleration of the password attack algorithm, and the FPGA executes the password attack algorithm in parallel, so that the parallelism of the algorithm is improved, the throughput performance during the algorithm execution is improved, and the performance of the password attack algorithm based on the rainbow table is further improved. Furthermore, the redundancy fine-grained parallelism of the FPGA end enables the hardware cost to be lower.
In the following, the password attack apparatus provided by the embodiment of the present invention is introduced, and the password attack apparatus described below and the password attack method described above may be referred to correspondingly.
Referring to fig. 2, fig. 2 is a schematic block diagram of a structure of a cryptographic attack apparatus according to an embodiment of the present invention, where the apparatus is specifically applied to a heterogeneous acceleration platform including a CPU end and an FPGA end, and specifically includes a first reading module 21, a processing module 22, a matching module 23, and a returning module 24, which are integrated at the FPGA end;
the first reading module 21 is configured to read a pre-stored rainbow table and ciphertext data to be attacked;
the processing module 22 is configured to perform parallel processing on ciphertext data to be attacked according to a preset password attack algorithm to obtain password data to be selected;
the matching module 23 is configured to match the password data to be selected with the rainbow table according to a preset matching algorithm, and find out an alternative password;
the return module 24 is used for returning a completion signal to the CPU side.
In some embodiments, the system may further include a transmission module, an operation parameter setting module, and a start instruction sending module integrated at the CPU end;
the transmission module is used for transmitting the rainbow table and the ciphertext data to be attacked to a cache region of the FPGA end through a preset interface;
the operation parameter setting module is used for setting operation parameters of the FPGA end;
and the starting instruction sending module is used for sending a starting instruction to the FPGA terminal according to the operation parameters.
In some embodiments, the matching module 23 may include:
and the marking submodule is used for marking the data of the password to be selected, which is successfully matched with the rainbow table, as true according to a preset matching algorithm and taking the data as the alternative password.
In some specific embodiments, the system may further include a second reading module integrated at the CPU end, and configured to read the alternative password from the buffer at the FPGA end.
In the embodiment, the device performs the password attack based on the rainbow table by using the FPGA, namely, the FPGA performs the hardware acceleration of the password attack algorithm, and the FPGA executes the password attack algorithm in parallel, so that the parallelism of the algorithm is improved, the throughput performance during the algorithm execution is improved, and the performance of the password attack algorithm based on the rainbow table is further improved. Furthermore, the redundancy fine-grained parallelism of the FPGA end enables the hardware cost to be lower.
Referring to fig. 3, a schematic block diagram of a structure of a heterogeneous acceleration platform provided in this embodiment of the present invention, the heterogeneous acceleration platform may include a CPU terminal 31 and an FPGA terminal 32;
the FPGA end is used for reading a pre-stored rainbow table and ciphertext data to be attacked; according to a preset password attack algorithm, parallel processing is carried out on cipher text data to be attacked to obtain password data to be selected; matching the password data to be selected with a rainbow table according to a preset matching algorithm, and finding out an alternative password; and returning a completion signal to the CPU.
The CPU end is specifically used for creating a cache for data communication between the CPU end and the FPGA end, transmitting the rainbow table and the ciphertext data to the FPGA end, setting the operation parameters of the FPGA end, and controlling the starting of a password attack algorithm of the FPGA end based on the rainbow table.
It should be noted that, the similarities between the present embodiment and the above embodiments may be referred to each other, and are not described herein again.
The CPU + FPGA heterogeneous acceleration platform utilizes the FPGA to carry out the cipher attack based on the rainbow table, namely the FPGA is utilized to carry out the hardware acceleration of the cipher attack algorithm, and the FPGA executes the cipher attack algorithm in parallel, so that the parallelism of the algorithm is improved, the throughput performance during the algorithm execution is improved, and the performance of the cipher attack algorithm based on the rainbow table is further improved. Furthermore, the redundancy fine-grained parallelism of the FPGA end enables the hardware cost to be lower.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The password attack method, the password attack device and the heterogeneous acceleration platform provided by the invention are described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (8)
1. A password attack method is characterized in that the method is applied to a heterogeneous platform comprising a CPU end and an FPGA end, and comprises the following steps:
the FPGA end reads a pre-stored rainbow table and ciphertext data to be attacked;
the FPGA terminal carries out parallel processing on the ciphertext data to be attacked according to a preset password attack algorithm to obtain password data to be selected;
the FPGA terminal matches the password data to be selected with the rainbow table according to a preset matching algorithm to find out an alternative password;
the FPGA end returns a completion signal to the CPU end;
the preset password attack algorithm is an algorithm described by using an OpenCL language;
correspondingly, the parallel processing is carried out on the ciphertext data to be attacked by the FPGA end according to a preset password attack algorithm to obtain password data to be selected, and the method comprises the following steps:
generating a Kernel program running at the FPGA end by using a preset password attack algorithm described by using an OpenCL language;
compiling the Kernel program by using an Altera SDK for OpenCL high-level comprehensive tool to generate an executable AOCX file executed at the FPGA end;
the FPGA terminal executes the executable AOCX file so as to perform parallel processing on the ciphertext data to be attacked and obtain password data to be selected;
before the FPGA reads the pre-stored rainbow table and the ciphertext data to be attacked, the method further includes:
the CPU transmits the rainbow table and the ciphertext data to be attacked to a cache region of the FPGA end through a preset interface; setting operation parameters of the FPGA end; and sending a starting instruction to the FPGA terminal according to the operation parameters, wherein the operation parameters comprise FPGA read-in digit information, cycle expansion size information and storage information.
2. The password attack method according to claim 1, wherein the FPGA end matches the password data to be selected with the rainbow table according to a preset matching algorithm to find out an alternative password, and the method comprises:
and the FPGA end marks the password data to be selected successfully matched with the rainbow table as true according to the preset matching algorithm and takes the true as the alternative password.
3. The password attack method according to claim 2, wherein after the FPGA end returns the completion signal to the CPU end, the method further comprises:
and the CPU end reads the alternative password from the cache region of the FPGA end.
4. The password attack method according to claim 2 or 3, wherein the predetermined interface is a PCI-E interface, and the cache area is DDR 3.
5. A password attack device is characterized by being applied to a heterogeneous platform comprising a CPU end and an FPGA end, and comprising a first reading module, a processing module, a matching module and a returning module which are integrated on the FPGA end;
the first reading module is used for reading a pre-stored rainbow table and ciphertext data to be attacked;
the processing module is used for carrying out parallel processing on the ciphertext data to be attacked according to a preset password attack algorithm to obtain password data to be selected;
the matching module is used for matching the password data to be selected with the rainbow table according to a preset matching algorithm to find out an alternative password;
the return module is used for returning a completion signal to the CPU end;
the preset password attack algorithm is an algorithm described by using an OpenCL language;
accordingly, the processing module is configured to:
generating a Kernel program running at the FPGA end by using a preset password attack algorithm described by using an OpenCL language;
compiling the Kernel program by using an Altera SDK for OpenCL high-level comprehensive tool to generate an executable AOCX file executed at the FPGA end;
the FPGA terminal executes the executable AOCX file so as to perform parallel processing on the ciphertext data to be attacked and obtain password data to be selected;
the password attack device also comprises a transmission module, an operation parameter setting module and a starting instruction sending module which are integrated at the CPU end;
the transmission module is used for transmitting the rainbow table and the ciphertext data to be attacked to a cache region of the FPGA end through a preset interface;
the operation parameter setting module is used for setting operation parameters of the FPGA end;
the starting instruction sending module is used for sending a starting instruction to the FPGA terminal according to the operation parameters, wherein the operation parameters comprise FPGA read-in digit information, cycle expansion size information and storage information.
6. The cryptographic attack apparatus according to claim 5, wherein the matching module comprises:
and the marking submodule is used for marking the password data to be selected successfully matched with the rainbow table as true according to the preset matching algorithm and taking the true as the alternative password.
7. The password attack apparatus according to claim 6, further comprising a second reading module integrated at the CPU end, configured to read the alternative password from the buffer at the FPGA end.
8. A heterogeneous acceleration platform is characterized by comprising a CPU end and an FPGA end;
the FPGA end is used for reading a pre-stored rainbow table and ciphertext data to be attacked; according to a preset password attack algorithm, parallel processing is carried out on the ciphertext data to be attacked to obtain password data to be selected; matching the password data to be selected with the rainbow table according to a preset matching algorithm, and finding out an alternative password; returning a completion signal to the CPU, where the preset password attack algorithm is an algorithm described in an OpenCL language, and the FPGA side performs parallel processing on the ciphertext data to be attacked according to the preset password attack algorithm to obtain password data to be selected, including: generating a Kernel program running at the FPGA end by using a preset password attack algorithm described by using an OpenCL language; compiling the Kernel program by using an Altera SDK for OpenCL high-level comprehensive tool to generate an executable AOCX file executed at the FPGA end; the FPGA terminal executes the executable AOCX file so as to perform parallel processing on the ciphertext data to be attacked and obtain password data to be selected;
the CPU end is used for transmitting the rainbow table and the ciphertext data to be attacked to a cache region of the FPGA end through a preset interface; setting operation parameters of the FPGA end; and sending a starting instruction to the FPGA terminal according to the operation parameters, wherein the operation parameters comprise FPGA read-in digit information, cycle expansion size information and storage information.
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| CN108921289B (en) * | 2018-06-20 | 2021-10-29 | 郑州云海信息技术有限公司 | FPGA heterogeneous acceleration method, device and system |
| CN109803068A (en) * | 2019-01-21 | 2019-05-24 | 郑州云海信息技术有限公司 | A kind of isomery hybrid system and method based on safety monitoring |
| CN112286756A (en) * | 2020-09-29 | 2021-01-29 | 深圳致星科技有限公司 | FPGA power consumption prediction method and system for federated learning heterogeneous processing system |
| CN112887093B (en) * | 2021-03-30 | 2022-09-30 | 矩阵元技术（深圳）有限公司 | Hardware acceleration system and method for implementing cryptographic algorithms |
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