CN107425841B - A kind of timing error detection unit based on jump error check structure - Google Patents
A kind of timing error detection unit based on jump error check structure Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
A kind of timing error detection unit based on jump error check structure, is related to technical field of integrated circuits.Including time-series rules part and data sampling section, wherein time-series rules part only can be achieved with timing error detection with 8 MOS transistors, and structure is simple, and area overhead is small；And data sampling part uses the effective latch of level, so will not be influenced by metastable；In addition the present invention separates timing error detection part and data sampling part, and two parts autonomous working is independent of each other, and improves the stability of circuit.When the present invention is applied to pipelining, suspend error correcting technique in conjunction with global clock, even if there are multiple timing errors in same period, also only needs an additional period energy error correction, the power consumption of flow line circuit can be greatly lowered.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of timing error detection based on jump error check structure
Unit.
Background technique
With the development of integrated circuit fabrication process and the diminution of characteristic size, the integrated level of semiconductor circuit sharply increases
Add.How using limited energy consumption to realize that the high-performance of circuit is work that present IC design is rich in challenge, especially
It is with the prevalence of mobile communication product and personal wearable device, the demand to Low-power Technology is especially urgent.Integrated circuit
In power consumption it is related with frequency with supply voltage, supply voltage and working frequency are lower, and power consumption is lower；But reduce frequency meeting
Greatly damage the speed of service and performance of circuit.Due to integrated circuit power consumption and voltage it is square in direct ratio, so drop
Low supply voltage is to reduce circuit power consumption most efficient method.In traditional design, even if in order to prolong circuit in the worst
Late when also can correctly work, the decline of voltage is restricted, cannot infinitely decline, it is necessary to the point that circuit can correctly work with
On.However the delay approximation in path is in normal distribution in circuit, the probability that the worst delay path is triggered is very low.Therefore people mention
Other technology is gone out, has further decreased supply voltage, the point for making voltage drop that can correctly work as low as circuit is hereinafter, allow electricity
There is timing error in road, by correcting the timing error of probability of occurrence very little, enables circuit to continue correctly to run, from error-detection error-correction
Technology is exactly to realize low-power consumption using this principle.
It has to be able to achieve data sampling from the error checking unit of error detection error correcting technique and timing error detects two big functions.Allusion quotation
The error checking unit of type includes structure double sampled and with transition detection device.Double sampled structure due to needing two groups of timing in the paths
Unit carries out sampling comparison, and area and power dissipation overhead are relatively large, reduces limited power consumption.In the past with the error detection list of transition detection device
Meta structure, transition detection device area overhead are larger.Other structure, transition detection device and data sampling section share certain sections
Point, data sampling and timing error detection can interact, and bring adverse effect to the stability of circuit.
Summary of the invention
In view of the above shortcomings, the present invention proposes a kind of base on the basis of based on traditional transition detection device structure
In the timing error detection unit of novel jump error check structure, the structure is simple, is not influenced by metastable state, data sampling and when
Sequence error detection separates, and does not influence each other；And when applying in a pipeline, suspend error correcting technique in conjunction with global clock, substantially
Reduce the power consumption of assembly line.
Technical scheme is as follows:
A kind of timing error detection unit based on jump error check structure, including time-series rules part and data sampling unit
Point,
The time-series rules part includes the first PMOS tube M1, the second PMOS tube M2, third PMOS tube M4, the 4th PMOS tube
M7, the first NMOS tube M3, the second NMOS tube M5, third NMOS tube M6 and the 4th NMOS tube M8,
The grid of first PMOS tube M1 connects the grid of the first NMOS tube M3 and as the timing error detection unit
Data input pin, drain electrode connect the source electrode of the second PMOS tube M2 and the grid of third PMOS tube M4；
The grid of second PMOS tube M2 connects the drain electrode and second of the first NMOS tube M3 as the first Clock control end, drain electrode
The grid of NMOS tube M5；The drain electrode of second NMOS tube M5 connects third PMOS tube M4 drain electrode；
The grid of third NMOS tube M6 connects the first NMOS tube M3 and the second NMOS tube as second clock control terminal, drain electrode
The grid of the source electrode of M5 and the 4th PMOS tube M7 and the 4th NMOS tube M8；
The drain electrode of 4th PMOS tube M7 meets the drain electrode of the 4th NMOS tube M8 and output timing error signal error；
The source electrode of first PMOS tube M1, third PMOS tube M4 and the 4th PMOS tube M7 connect supply voltage, third NMOS tube M6,
The source electrode of 4th NMOS tube M8 is grounded；
The data sampling part includes the 5th PMOS tube M9, the 6th PMOS tube M11, the 7th PMOS tube M13, the 8th PMOS
Pipe M15, the 5th NMOS tube M10, the 6th NMOS tube M12, the 7th NMOS tube M14 and the 8th NMOS tube M16,
The source electrode of 5th PMOS tube M9 and the 5th NMOS tube M10 connects the data input of the timing error detection unit
End, the grid connection drain electrode of the 5th PMOS tube M9 and the 5th NMOS tube M10 of the 7th PMOS tube M13, the 6th PMOS tube M11 and the
The source electrode of six NMOS tube M12 and the grid of the 7th NMOS tube M14, the drain electrode and the of the 7th NMOS tube M14 of drain electrode connection
The grid of eight PMOS tube M15 and the 8th NMOS tube M16 simultaneously exports oppisite phase data output signal；
The leakage of the 6th NMOS tube M12, the 8th PMOS tube M15 and the 8th NMOS tube M16 of drain electrode connection of 6th PMOS tube M11
Pole and output data output signal；
The grid of 5th PMOS tube M9 and the 6th NMOS tube M12 connects the second clock control terminal, the 5th NMOS tube M10
With the gate interconnection of the 6th PMOS tube M11 and as third Clock control end；
The source electrode of 7th PMOS tube M13 and the 8th PMOS tube M15 meets supply voltage, the 7th NMOS tube M14 and the 8th NMOS
The source electrode of pipe M16 is grounded.
The invention has the benefit that structure is simple, area overhead is small, only can be achieved with timing mistake with 8 MOS transistors
Error detection；Since data sampling part uses the effective latch of level, so this structure will not be influenced by metastable；And
And the present invention separates timing error detection part and data sampling part, two parts autonomous working is independent of each other, and improves electricity
The stability on road.The present invention should suspend error correcting technique in conjunction with global clock when pipelining, even if occurring in same period
Multiple timing errors also only need an additional period energy error correction, assembly line electricity can be greatly lowered in this way
The power consumption on road.
Detailed description of the invention
Fig. 1 is the circuit diagram that the present invention is applied to pipeline organization in embodiment.
Fig. 2 is a kind of timing error detection unit schematic diagram based on jump error check structure proposed by the invention.
Fig. 3 is a kind of operation timing diagram of timing error detection unit based on jump error check structure proposed by the invention
Fig. 4 is the circuit diagram of the single-stage latch group module of pipeline organization in embodiment.
Fig. 5 is the clock control of pipeline organization and the circuit diagram of correction module in embodiment.
Fig. 6 is that the circuit that the present invention is applied to pipeline organization in embodiment runs timing diagram.
Specific embodiment
The present invention is described in detail in the following with reference to the drawings and specific embodiments:
The timing error detection unit of band jump error check structure proposed by the present invention can be used for pipelining, such as Fig. 1 institute
It is shown as that timing error detection unit of the invention is used for the circuit diagram of pipelining, including multiple strings in the present embodiment
It the single-stage latch group of connection, multiple combinational logic modules connect between the single-stage latch group and a clock control and entangles
Mismatch block, the input of the first order single-stage latch group terminate input signal IN, the single-stage latch group of afterbody it is defeated
Outlet output signal OUT.
Wherein single-stage latch group includes multiple timing error detection units and a wrong summarizing module, timing error inspection
The number of unit is surveyed depending on physical circuit, the input terminal of single-stage latch group is the input terminal of each timing error detection unit
The output of D connection higher level's pipelined combination logic module or input signal IN, output end are each timing error detection unit
Data output end Q the input or afterbody single-stage of junior's pipelined combination logic module are connected with oppisite phase data output end QN
The output end output signal OUT of latch group.
The wrong summarizing module of each single-stage latch group receives the detection of multiple timing errors in the single-stage latch group
The timing error signal error of unit output simultaneously exports single-stage assembly line error signal error_total to clock control and entangles
Clock signal clk _ S of the input terminal of mismatch block, clock control and correction module also input system, and generate erroneous resets signal
Error_rstn feeds back to the wrong collection unit in each single-stage latch group, while clock control and wrong summarizing module are also
Redundancy charge electric discharge clock signal clk N, error detection window clock signal CLKN_D and local clock pulses CLK_L is generated to connect respectively
Connect the first Clock control end, second clock control terminal and third Clock control end of timing error detection unit.
Fig. 2 is the timing error detection unit schematic diagram proposed by the invention based on novel jump error check structure, and Fig. 3 is
Its timing diagram run.There is a bit of prolong between redundancy charge electric discharge clock signal clk N and error detection window clock signal CLKN_D
When δ, this section delay it is very small, for ease of description, enhanced processing has been done in Fig. 3.
Timing error detection unit is divided into two parts: first part includes the first PMOS tube M1, the second PMOS tube M2, third
PMOS tube M4, the 4th PMOS tube M7, the first NMOS tube M3, the second NMOS tube M5, third NMOS tube M6, the 4th NMOS tube M8 are used
Come whether detection circuit timing error occurs；Second part includes the 5th PMOS tube M9, the 6th PMOS tube M11, the 7th PMOS tube
M13, the 8th PMOS tube M15, the 5th NMOS tube M10, the 6th NMOS tube M12, the 7th NMOS tube M14 and the 8th NMOS tube M16 are used
Carry out sampled data.
When local clock pulses CLK_L is low level, the electric discharge of redundancy charge clock signal clk N, error detection window clock signal
CLKN_D is high level, i.e. when 1 region in Fig. 3, the second PMOS tube M2 is disconnected, third NMOS tube M6 conducting, net3 node
It being pulled low, net3 node becomes high level after the phase inverter that the 4th PMOS tube M7 and the 4th NMOS tube M8 is formed, so this
When timing error signal error be high level.Since the second PMOS tube M2 is disconnected, at this moment the input of timing error detection unit is believed
The jump of number D will not influence timing error signal error.If the input signal D of timing error detection unit is low level at this time,
Then the first PMOS tube M1 is connected, and net1 node is electrically charged；First if being high level if the input signal D of timing error detection unit
NMOS tube M3 conducting, net2 node are dragged down by net3 node.
When local clock pulses CLK_L, error detection window clock signal CLKN_D are high level, redundancy charge electric discharge clock letter
Number CLKN is low level, i.e. when 2 region in Fig. 3, the second PMOS tube M2 conducting, and third NMOS tube M6 conducting, timing error
Signal error is still high level.If the input signal D of timing error detection unit continues to keep low level, the first PMOS at this time
Pipe M1 conducting, the first NMOS tube M3 are disconnected, and net1 node is charged to height, since the second PMOS tube of M2 is connected, so being stored in
The charge of net1 node draws high net2 node, and then the second NMOS tube M5 is connected, and net3 node drags down net4 node.If
The input signal D of timing error detection unit continues to keep high level at this time, and the first PMOS tube M1 is disconnected, and the first NMOS tube M3 is led
Logical, net2 node and net3 node will continue as low.If the input signal D of timing error detection unit is jumped by low level at this time
For high level, the first PMOS tube M1 is disconnected, the first NMOS tube M3 conducting, then the charge for being stored in net1 node will be by the
Two PMOS tube M2, the first NMOS tube M3 and third NMOS tube M6 are let go, and net1 node becomes low level, and then third PMOS tube
M4 conducting, net4 node are charged to height, store charge.If the input signal D of timing error detection unit is by high level at this time
Jump is low level, then the first NMOS tube M3 is disconnected, the first PMOS tube M1 conducting, net1 node will be charged to height.
When local clock pulses CLK_L is high level, the electric discharge of redundancy charge clock signal clk N, error detection window clock signal
When CLKN_D is 3 region of low level, i.e. Fig. 3, the second PMOS tube M2 conducting, third NMOS tube M6 is disconnected.If timing error
The input signal D of detection unit generates rising edge jump, i.e. D is jumped from low level to high level, at this point, the first NMOS tube M3 is led
Logical, net3 node is charged as height, net3 node through the second PMOS tube M2 and the first NMOS tube M3 by the charge of net1 node storage
Become low level after the phase inverter that the 4th PMOS tube M7 and the 4th NMOS tube M8 is formed, so timing error signal at this time
Error is low level.If the input signal D of timing error detection unit generates failing edge jump, i.e. timing error detection at this time
The input signal D of unit is jumped from high level to low level, and at this moment the first PMOS tube M1 is connected, and net1 node is charged to height,
Since the second PMOS tube M2 is connected, and then net2 node is height, so the second NMOS tube M5 is connected, in this way, being stored in net4 section
Net3 node is just charged as height by the charge of point, after the phase inverter that the 4th PMOS tube M7 and the 4th NMOS tube M8 is formed, when
Sequence error signal error becomes low level.
When redundancy charge electric discharge clock signal clk N is high level, local clock pulses CLK_L, error detection window clock signal
CLKN_D is low level, i.e. when 4 region in Fig. 3, the second PMOS tube M2 and third NMOS tube M6 are disconnected, this structure is not at this time
Timing error can be detected, the input signal D of timing error detection unit cannot be jumped within this range.In actual electricity
In the design of road, since delay δ very little can almost be ignored so this region is very narrow.And we can reinforce constraining, and make
The jump of the input signal D of timing error detection unit is unlikely to occur in this region.The error detection of timing error detection unit
Window is that the high level width of local clock pulses CLK_L subtracts delay δ.The worst delay path must be smaller than a cycle and add
The length of upper error detection window.Have between redundancy charge electric discharge clock signal clk N and error detection window clock signal CLKN_D a bit of
Delay δ primarily to make the second PMOS tube M2 shift to an earlier date δ time conducting, by the input signal D of timing error detection unit by
The charge that low level jump is stored in net1 node for high level is bled off, in case net1 node is to net3 node in error detection window
Electric discharge generates spurious error.
As a whole, if circuit does not have timing error generation, timing error signal error is high level, if when
The data of the input signal D of sequence error detection units are jumped in the error detection window of timing error detection unit, then timing
Error signal error will be jumped and be continued for some time for low level, then be jumped as high level.As local clock pulses CLK_L
For high level, when error detection window clock signal CLKN_D is low level, the biography of the 5th PMOS tube M9 and the 5th NMOS tube M10 composition
The transmission gate of defeated door conducting, the 6th PMOS tube M11 and the 6th NMOS tube M12 composition disconnects.At this point, timing error detection unit
The transmission gate that the data of input signal D are made up of the 5th PMOS tube M9 and the 5th NMOS tube M10, the 7th PMOS tube M13 and the
The phase inverter of the phase inverter of seven NMOS tube M14 composition, the 8th PMOS tube M15 and the 8th NMOS tube M16 composition arrives separately at timing
Data output end, the oppisite phase data of error detection units store up output end, complete the number in local clock pulses CLK_L high level
According to sampling.When local clock pulses CLK_L is low level, and error detection window clock signal CLKN_D is high level, the 5th PMOS
The transmission gate of pipe M9 and the 5th NMOS tube M10 composition disconnects, the transmission gate of the 6th PMOS tube M11 and the 6th NMOS tube M12 composition
Conducting.In the transmission gate that the data of data output end are made up of the 6th PMOS tube M11 and the 6th NMOS tube M12, the 7th PMOS
The phase inverter lock of the phase inverter of pipe M13 and the 7th NMOS tube M14 composition, the 8th PMOS tube M15 and the 8th NMOS tube M16 composition
It deposits.As shown in figure 3, when the data of the input signal D of timing error detection units are when error detection window jumps, timing error signal
Error becomes low level, and after error detection window clock signal CLKN_D becomes high level, timing error signal error becomes high
Level.When local clock pulses CLK_L is high level, the data output end of timing error detection unit to data input pin into
Row sampling, when local clock pulses CLK_L is low level, the data of the data output end of timing error detection unit are latched.
Be illustrated in figure 4 the structure chart of single-stage latch group in the present embodiment, including multiple timing error detection units and
One wrong collection unit, mistake collection unit include pull-up PMOS tube M17, a pull-down NMOS pipe M18 and it is multiple simultaneously
The PMOS tube of connection, the source electrode of pull-up PMOS tube M17 connect supply voltage, and drain electrode connects the source electrode of the PMOS tube of the multiple parallel connection；
The source electrode of pull-down NMOS pipe M18 is grounded, and drain electrode meets the drain electrode of the PMOS tube of the multiple parallel connection, the PMOS of the multiple parallel connection
The grid of pipe respectively meets the timing error signal error of timing error detection unit output, pulls up PMOS tube M17 and drop-down
The grid wrong of NMOS tube M18 misses reset signal error_rstn, and the drain electrode of the PMOS tube of multiple parallel connections exports single-stage assembly line
Error signal error_total.
When there are no errors, erroneous resets signal error_rstn is low level, pull-up PMOS tube M17 conducting, drop-down
NMOS tube M18 is disconnected, and single-stage assembly line error signal error_total is low level, when timing error detection units detect
When timing error, the timing error signal error signal end jump of timing error detection unit is low level, at this point, single-stage is locked
PMOS tube between storage group module error collection unit pull-up PMOS tube M17 and pull-down NMOS pipe M18 at least has one and leads
It is logical, so that single-stage assembly line error signal error_total node is pulled to high level.As erroneous resets signal error_rstn
When becoming high level, pull-down NMOS pipe M18 conducting, pull-up PMOS tube M17 is disconnected, single-stage assembly line error signal error_
Total node is pulled to low level.Erroneous resets signal error_rstn is single-stage assembly line error signal error_total's
Reset signal can carry out mistake next time and summarize detection.
The input of combinational logic module is data output signal Q and the oppisite phase data output of multiple timing error detection units
Signal QN, the output of combinational logic module is the data input signal D of multiple timing error detection units, according to different circuits
The content of structure, combinational logic module is different.
Clock control and correction module in the present embodiment as shown in figure 5, include or door, first with door, second with door, lock
Storage, phase inverter and delay unit, the latch low level are effective；Described or door input terminal connection error collection unit is defeated
Single-stage assembly line error signal error_total out, output end connect the D input terminal of the latch；The clock of system
Signal CLK_S connect the input end of clock of the latch with described first with door and second with the first input end of door；It is described
First connect the Q output of the latch, output end output error reset signal error_ with the second input terminal of door
rstn；Described second connect the QN output end of the latch with the second input terminal of door, and output end connects the phase inverter
Input terminal and export local clock pulses CLK_L；The output end output redundancy charge electric discharge clock signal of the phase inverter
The output end of CLKN and the input terminal for connecting the delay unit, the delay unit exports error detection window clock signal CLKN_
D.The single-stage assembly line error signal error_total of the output of multiple single-stage latch group modules is by one or obtains complete
Office error signal error_global, then global error signal error_global signal is connected to a low level and effectively locks
The D input terminal of storage.Low level effective latch output clock stop signal stall and clock stop inversion signal~
stall.Clock stop signal stall and clock signal clk _ S of system obtains erroneous resets signal with door by first
Error_rstn, erroneous resets signal error_rstn are sent to the wrong collection unit input terminal of single-stage latch group module.
Clock signal of system CLK_S and clock stop inversion signal~stall and obtain local clock pulses CLK_L with door by second,
Local clock pulses CLK_L obtains redundancy charge electric discharge clock signal clk N, redundancy charge electric discharge clock by a reverser
Signal CLKN obtains error detection window clock signal CLKN_D after a delay unit is delayed δ.
Fig. 6 is the operation timing diagram of clock control and correction module.When the single-stage of any one single-stage latch group module
Assembly line error signal error_total signal becomes high level, by one or behind the door, global error signal error_
Global signal becomes high level.Then global error signal error_global signal is connected to a low level and effectively latches
The input terminal of device, the clock port of this latch are clock signal of system CLK_S.The end Q and QN of latch is respectively that clock stops
Stop signal stall and clock stop inversion signal~stall.When the low level of clock signal of system CLK_S arrives, latch
By the global error signal error_global sampling to high level, clock stop signal stall is obtained.As shown in fig. 6, clock
Stop signal stall can keep a clock cycle.Clock signal of system CLK_S and clock stop signal stall passes through and door
Obtain erroneous resets signal error_rstn, clock high level width and the system clock letter of erroneous resets signal error_rstn
Number CLK_S is the same.After erroneous resets signal error_rstn becomes high level, the single-stage assembly line of single-stage latch group module is wrong
Error signal error_total is pulled to low level, summarizes for mistake next time and prepares.Clock signal of system CLK_S and clock
Stop inversion signal~stall by one with obtain local clock pulses CLK_L behind the door, by local clock pulses CLK_L into
And obtain the electric discharge of redundancy charge clock signal clk N, error detection window clock signal CLKN_D.Generally speaking, when circuit because of power supply
When voltage declines and generates timing error, as shown in fig. 6, global error signal error_global jump is high level, latch
Device samples to obtain clock stop signal stall to global error signal error_global and clock stop inversion signal~
Stall ,~stall signal make local clock pulses CLK_L, redundancy charge electric discharge clock signal clk N, error detection window clock letter
Number CLKN_D suspends a clock cycle, completes error correction.Clock stop signal is by stall and global error signal error_
The erroneous resets signal error_rstn that global is generated makes the single-stage assembly line error signal error_ of single-stage latch group
Total resets, and is ready for error detection next time.After the completion of error correction procedure, circuit will continue to execute next input.
Compared to traditional error check structure, structure of the invention is very simple；Data path is the latch by level-sensitive
Composition, so not influenced by metastable state.Also, this structure separates timing error detection part and data sampling section, the two
Independent operating is independent of each other, and improves the stability of circuit.Using global clock suspend error correcting technique, multiple timing errors also only
It needs an additional clock cycle that can correct, significantly reduces the power consumption of circuit.
Those skilled in the art disclosed the technical disclosures can make various do not depart from originally according to the present invention
Various other specific variations and combinations of essence are invented, these variations and combinations are still within the scope of the present invention.
Claims (1)
1. a kind of timing error detection unit based on jump error check structure, which is characterized in that including time-series rules part sum number
According to sampling section,
The time-series rules part includes the first PMOS tube (M1), the second PMOS tube (M2), third PMOS tube (M4), the 4th PMOS
(M7), the first NMOS tube (M3), the second NMOS tube (M5), third NMOS tube (M6) and the 4th NMOS tube (M8) are managed,
The grid of first PMOS tube (M1) connects the grid of the first NMOS tube (M3) and as the timing error detection unit
Data input pin, drain electrode connect the source electrode of the second PMOS tube (M2) and the grid of third PMOS tube (M4)；
The grid of second PMOS tube (M2) connects the drain electrode and second of the first NMOS tube (M3) as the first Clock control end, drain electrode
The grid of NMOS tube (M5)；The drain electrode of second NMOS tube (M5) connects the drain electrode of third PMOS tube (M4)；
The grid of third NMOS tube (M6) connects the first NMOS tube (M3) and the second NMOS tube as second clock control terminal, drain electrode
(M5) grid of source electrode and the 4th PMOS tube (M7) and the 4th NMOS tube (M8)；
The drain electrode of 4th PMOS tube (M7) connects the drain electrode of the 4th NMOS tube (M8) and output timing error signal (error)；
The source electrode of first PMOS tube (M1), third PMOS tube (M4) and the 4th PMOS tube (M7) connects supply voltage, third NMOS tube
(M6) it is grounded with the source electrode of the 4th NMOS tube (M8)；
The data sampling part includes the 5th PMOS tube (M9), the 6th PMOS tube (M11), the 7th PMOS tube (M13), the 8th
PMOS tube (M15), the 5th NMOS tube (M10), the 6th NMOS tube (M12), the 7th NMOS tube (M14) and the 8th NMOS tube (M16),
5th PMOS tube (M9) connects the data input of the timing error detection unit with the source electrode of the 5th NMOS tube (M10)
End, drain electrode, the 6th PMOS tube of grid connection the 5th PMOS tube (M9) and the 5th NMOS tube (M10) of the 7th PMOS tube (M13)
(M11) and the grid of the source electrode of the 6th NMOS tube (M12) and the 7th NMOS tube (M14), drain electrode connect the 7th NMOS tube
(M14) grid of drain electrode and the 8th PMOS tube (M15) and the 8th NMOS tube (M16) simultaneously exports oppisite phase data output signal；
The drain electrode of 6th PMOS tube (M11) connects the 6th NMOS tube (M12), the 8th PMOS tube (M15) and the 8th NMOS tube (M16)
Drain electrode and output data output signal；
5th PMOS tube (M9) connects the second clock control terminal, the 5th NMOS tube with the grid of the 6th NMOS tube (M12)
(M10) and the gate interconnection of the 6th PMOS tube (M11) and as third Clock control end；
The source electrode of 7th PMOS tube (M13) and the 8th PMOS tube (M15) connects supply voltage, the 7th NMOS tube (M14) and the 8th
The source electrode of NMOS tube (M16) is grounded；
The third Clock control end connects local clock pulses, the first Clock control end connection redundancy charge electric discharge clock
Signal, the second clock control terminal connect error detection window clock signal, the redundancy charge electric discharge clock signal with described
Ground clock signal reverse phase, the error detection window clock signal are delayed to obtain by redundancy charge electric discharge clock signal.
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| CN101651455A (en) * | 2008-06-10 | 2010-02-17 | 阿尔特拉公司 | Apparatus for power consumption reduction in programmable logic devices and associated methods |
| CN101924545A (en) * | 2009-03-16 | 2010-12-22 | Arm有限公司 | Error detection in precharged logic |
| CN106462553A (en) * | 2014-05-09 | 2017-02-22 | 南加利福尼亚大学 | A timing violation resilient asynchronous template |
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| CN101651455A (en) * | 2008-06-10 | 2010-02-17 | 阿尔特拉公司 | Apparatus for power consumption reduction in programmable logic devices and associated methods |
| CN101924545A (en) * | 2009-03-16 | 2010-12-22 | Arm有限公司 | Error detection in precharged logic |
| CN106462553A (en) * | 2014-05-09 | 2017-02-22 | 南加利福尼亚大学 | A timing violation resilient asynchronous template |
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