CN107424987B - Stacked semiconductor structure and manufacturing method thereof - Google Patents

Stacked semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN107424987B
CN107424987B CN201710524769.7A CN201710524769A CN107424987B CN 107424987 B CN107424987 B CN 107424987B CN 201710524769 A CN201710524769 A CN 201710524769A CN 107424987 B CN107424987 B CN 107424987B
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substrate
contact
semiconductor structure
surface mount
stacked semiconductor
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CN107424987A (en
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沈家贤
颜瀚琦
刘盈男
李维钧
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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    • H01L2223/66—High-frequency adaptations
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract

A stacked semiconductor structure and a method for fabricating the same. The stacked semiconductor structure comprises a first substrate, a second substrate, a first semiconductor chip, a second semiconductor chip and a surface adhesive element. The first substrate has an upper surface. The second substrate has a lower surface. The first semiconductor chip is arranged on the upper surface of the first substrate. The second semiconductor chip is arranged on the lower surface of the second substrate. The first surface-mount component is arranged between the upper surface of the first substrate and the lower surface of the second substrate and electrically connected with the first substrate and the second substrate. Because the first surface pasting element is positioned between the first substrate and the second substrate, the size of the semiconductor structure can be reduced.

Description

Stacked semiconductor structure and manufacturing method thereof
The present application is a divisional application of an invention patent application having an application date of 28/3/2014, an application number of "201410122664.5", and an invention name of "stacked semiconductor structure and manufacturing method thereof".
Technical Field
The present invention relates to a stacked semiconductor structure and a method for fabricating the same, and more particularly, to a stacked semiconductor structure having a surface mounted device and a method for fabricating the same.
Background
With the development of technology, the demand for the function and size of semiconductor structures is increasing, resulting in the smaller size and more functions of semiconductor structures. Semiconductor structures typically include multiple chips and multiple passive components, with increasing functional requirements.
The conventional semiconductor structure has the passive element disposed outside the substrate, thereby resulting in an increased area of the semiconductor structure. Therefore, how to configure passive devices to reduce the size of semiconductor structures is one of the goals in the industry.
Wireless communication devices/systems typically include a semiconductor structure with an antenna to receive and transmit signals. The semiconductor structure with the antenna can be arranged on a circuit board or a carrier board of the wireless communication device/system, and signal transmission between the semiconductor structure and the circuit board or the carrier board of the wireless communication device/system is achieved through an additionally designed connecting structure.
The additional design of the connection structure not only increases the overall cost of the wireless communication device/system, but also increases the volume of the wireless communication device/system.
Disclosure of Invention
In one embodiment, a surface mount device is positioned between two substrates, thereby reducing the lateral dimension of the semiconductor structure.
According to the present invention, a stacked semiconductor structure is provided. The stacked semiconductor structure comprises a first substrate, a second substrate, a first semiconductor chip, a second semiconductor chip, a first surface mounting element and a packaging body. The first substrate has an upper surface. The second substrate has a lower surface. The first semiconductor chip is disposed on an upper surface of the first substrate. The second semiconductor chip is arranged on the lower surface of the second substrate. The first surface-mount component is arranged between the upper surface of the first substrate and the lower surface of the second substrate and electrically connected with the first substrate and the second substrate. The packaging body wraps the upper surface of the first substrate, the lower surface of the second substrate, the first semiconductor chip, the second semiconductor chip and the first surface adhesive element.
According to the present invention, a stacked semiconductor structure is provided. The stacked semiconductor structure includes a first substrate, a second substrate, at least one surface mount element, an antenna, at least one first conductive via, and at least one second conductive via. The first substrate has an upper surface. The second substrate has an upper surface and a lower surface, the lower surface being opposite to the upper surface, the lower surface of the second substrate facing the upper surface of the first substrate. The at least one surface mounting element is located between the upper surface of the first substrate and the lower surface of the second substrate and is provided with a first contact and a second contact, the first contact and the second contact are respectively attached to the upper surface of the first substrate, and the second contact of the at least one surface mounting element is electrically connected to the ground plane of the first substrate. An antenna is disposed on an upper surface of the second substrate. At least one first conductive via is disposed on the second substrate and electrically connected to the antenna and the first contact of the at least one surface mount device. At least one second conductive via is disposed on the second substrate and electrically connected to the antenna and the second contact of the at least one surface mount device.
According to the present invention, a method for fabricating a stacked semiconductor structure is provided. The manufacturing method includes the following steps. Providing a first substrate; arranging a first semiconductor chip on an upper surface of the first substrate; providing a second substrate, wherein a second semiconductor chip is arranged on the lower surface of the second substrate; connecting the upper surface of the first substrate and the lower surface of a second substrate by a first surface-mount component to electrically connect the first substrate and the second substrate; and forming a packaging body to cover part of the upper surface of the first substrate, part of the lower surface of the second substrate, the first semiconductor chip, the second semiconductor chip and the first surface adhesive element.
According to the present invention, a method for fabricating a stacked semiconductor structure is provided. The manufacturing method comprises the following steps. Providing at least one first substrate, each first substrate having an upper surface; providing at least one second substrate, wherein each second substrate is provided with an upper surface and a lower surface, the lower surface is opposite to the upper surface, the upper surface of each second substrate is provided with an antenna, each second substrate is provided with a first conductive hole and a second conductive hole, the first conductive hole is arranged on the second substrate and is electrically connected with the antenna, and the second conductive hole is arranged on the second substrate and is electrically connected with the antenna; providing at least one surface mount component having a first contact and a second contact between a lower surface of each second substrate and an upper surface of each first substrate, electrically connecting the first contact of the at least one surface mount component to the first surface of the first substrate and the first conductive via, and electrically connecting the second contact of the at least one surface mount component to the ground plane of the first substrate and the second conductive via.
According to the present invention, an electronic device is provided. An electronic device includes a carrier having a corner and a stacked semiconductor structure located on the corner of the carrier and including a first substrate, a second substrate, at least one surface mount component, an antenna, at least one first conductive via, and at least one second conductive via. The first substrate has an upper surface. The second substrate has an upper surface and a lower surface, the lower surface being opposite to the upper surface, the lower surface of the second substrate facing the upper surface of the first substrate. The at least one surface mounting element is located between the upper surface of the first substrate and the lower surface of the second substrate and is provided with a first contact and a second contact, the first contact and the second contact are respectively attached to the upper surface of the first substrate, and the second contact of the at least one surface mounting element is electrically connected to the ground plane of the first substrate. An antenna is disposed on an upper surface of the second substrate. At least one first conductive via is disposed on the second substrate and electrically connected to the antenna and the first contact of the at least one surface mount device. At least one second conductive via is disposed on the second substrate and electrically connected to the antenna and the second contact of the at least one surface mount device.
In order to make the aforementioned and other objects of the present invention more comprehensible, embodiments accompanied with figures are described in detail as follows:
drawings
Fig. 1A shows a cross-sectional view of a stacked semiconductor structure according to an embodiment of the invention.
FIG. 1B is a top view of FIG. 1A.
Fig. 2 is a top view of a stacked semiconductor structure according to another embodiment of the invention.
Fig. 3 is a top view of a stacked semiconductor structure according to another embodiment of the invention.
Fig. 4 is a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention.
Fig. 5 is a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention.
Fig. 6 is a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention.
Fig. 7 shows a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention.
Fig. 8 is a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention.
Fig. 9 shows a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention.
Fig. 10A to 10G are process diagrams illustrating the manufacturing process of the stacked semiconductor structure of fig. 1A.
Fig. 11A to 11E are process diagrams illustrating the manufacturing process of the stacked semiconductor structure of fig. 4.
Fig. 12A-12C illustrate a process diagram for fabricating the stacked semiconductor structure of fig. 7.
Fig. 13A shows a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention.
Fig. 13B is a circuit diagram of the stacked semiconductor structure of fig. 13A.
Fig. 14A shows a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention.
Fig. 14B is a circuit diagram of the stacked semiconductor structure of fig. 14A.
Fig. 15 is a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention.
FIG. 16 is a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention.
Fig. 17-21 illustrate fabrication process diagrams of the stacked semiconductor structure of fig. 13A.
Fig. 22-26 illustrate fabrication process diagrams of the stacked semiconductor structure of fig. 15.
Fig. 27A is a schematic diagram of an antenna of the stacked semiconductor structure of fig. 13A.
Fig. 27B is a schematic diagram illustrating reflection loss of the antenna of fig. 27A.
Fig. 28A is a schematic diagram of an antenna of the stacked semiconductor structure of fig. 13A.
Fig. 28B is a reflection loss diagram of the antenna of fig. 28A.
Fig. 29A is a schematic diagram illustrating the stacked semiconductor structure of fig. 13A applied to a system carrier.
Fig. 29B is a schematic diagram illustrating a current distribution of the antenna of the stacked semiconductor structure illustrated in fig. 29A.
Fig. 29C is a schematic view of current distribution of the system carrier and the antenna of the stacked semiconductor structure shown in fig. 29A.
Fig. 30 is a schematic block circuit diagram of the stacked semiconductor structure of fig. 13A.
Description of the main element symbols:
100. 200, 300, 400, 500, 600, 700: stacked semiconductor structure
110. 510, 610: first substrate
111: a first substrate
111b, 131b, 132 b: lower surface
111s, 131s, 151s, 152s, 515s, 535 s: outer side surface
111u, 112u, 131 u: upper surface of
112: first circuit layer
113: second circuit layer
114. 114', 114 ": first conductive via
120: first semiconductor chip
125: bonding wire
126: antenna with a shield
130. 530, 630: second substrate
131: second base material
132: third circuit layer
133: a fourth circuit layer
134: second conductive via
140: second semiconductor chip
150: package body
151: first package
152: second package
160. 161, 161', 162, 163, 164, 165', 165 ", 165 '": first surface pasting element
160a, 161a, 162a, 163a, 164a, 165a, 170 a: first contact
160b, 161b, 162b, 163b, 164b, 165b, 170 b: second contact
170: second surface pasting component
175: solder
190: support plate
515: first grounding member
535: second grounding member
580: shielding film
616: first shielding layer
636: second shielding layer
H1: height
H2: distance between two adjacent plates
P1: cutting path
S: space(s)
1: electronic device
800. 810, 900, 910: stacked semiconductor structure
18. 181, 182: conductive connecting material
Detailed Description
Referring to fig. 1, a cross-sectional view of a stacked semiconductor structure according to an embodiment of the invention is shown. The stacked semiconductor structure 100 includes a first substrate 110, at least one first semiconductor chip 120, a second substrate 130, at least one second semiconductor chip 140, a package body 150, at least one Surface Mount Device (SMD) 160, and at least one second SMD 170.
The first substrate 110 includes a first base 111, a first circuit layer 112, a second circuit layer 113, and at least one first conductive via 114. The upper surface 111u of the first base 111 and the upper surface 112u of the first circuit layer 112 define an upper surface of the first substrate 110. The first circuit layer 112 and the second circuit layer 113 are respectively formed on the upper surface 111u and the lower surface 111b of the first substrate 111 for electrically connecting devices thereon. The first conductive via 114 extends between the upper surface 111u and the lower surface 111b of the first substrate 111 and electrically connects the first circuit layer 112 and the second circuit layer 113.
The first semiconductor chip 120 is disposed on the upper surface of the first substrate 110 with its active surface facing upward, and is electrically connected to the first circuit layer 112 through at least one bonding wire 125. The first semiconductor chip 120 may be electrically connected to the second substrate 130 through the first circuit layer 112, the first surface mount device 160, and the second surface mount device 170, and/or may be electrically connected to an external ground (not shown), an external ac power source (not shown), or an external dc power source (not shown) through the first circuit layer 112, the first conductive via 114, and the second circuit layer 113. In another example, the first semiconductor chip 120 may also be a flip chip (flip chip) disposed on the upper surface of the first substrate 110 with its active surface facing downward and electrically connected to the first circuit layer 112 through at least one solder ball.
The second substrate 130 includes a second base 131, a third circuit layer 132, a fourth circuit layer 133, and at least one second conductive via 134. The lower surface 131b of the second base 131 and the lower surface 132b of the third circuit layer 132 together define the lower surface of the second substrate 130. The third circuit layer 132 and the fourth circuit layer 133 are respectively formed on the lower surface 131b and the upper surface 131u of the second substrate 131 for electrically connecting the devices thereon. The second conductive via 134 extends between the upper surface 131u and the lower surface 131b of the second substrate 131 and electrically connects the third circuit layer 132 and the fourth circuit layer 133.
The second semiconductor chip 140 is, for example, a flip chip, and is disposed on the lower surface of the second substrate 130 with the active surface facing upward, and is electrically connected to the third circuit layer 132 through at least one solder ball. The second semiconductor chip 140 can be electrically connected to the first substrate 130 through the third circuit layer 132, the second surface mount device 170 and the first surface mount device 160. In another example, the second semiconductor chip 140 may also be disposed on the lower surface of the second substrate 130 with its active surface facing downward, and electrically connected to the third circuit layer 132 through at least one bonding wire.
In this embodiment, the package body 150 covers a portion of the upper surface of the first substrate 110, a portion of the lower surface of the second substrate 130, the first semiconductor chip 120, the second semiconductor chip 140, the first surface mount device 160, and the second surface mount device 170. The encapsulant 150 may include a phenolic-based resin (Novolac-based resin), an epoxy-based resin (epoxy-based resin), a silicone-based resin (silicone-based resin), or other suitable coating agent. The package body 150 may also include a suitable filler, such as powdered silicon dioxide. The package body can be formed by several packaging techniques, such as compression molding (compression molding), injection molding (injection molding), liquid encapsulation (liquid molding), or transfer molding (transfer molding).
The first surface mount device 160 is, for example, a passive device, such as a resistor, a capacitor or an inductor. The first surface mount device 160 is disposed on the upper surface of the first substrate 110, and is located between the upper surface of the first substrate 110 and the lower surface of the second substrate 130 and electrically connects the first substrate 110 and the second substrate 130. The first surface mount device 160 can be electrically connected to the second circuit layer 113 through the first circuit layer 112 and the first conductive via 114, and can be electrically connected to an external ground, an external ac power source or an external dc power source through the second circuit layer 113. In one example, the length x width of the first surface mount component 160 may be 40 filament x 20 filament, with a thickness of 0.5 mm; alternatively, the length x width of the first surface mount component 160 may be 60 filament x 30 filament, with a thickness of 0.8mm, or other suitable gauge.
The second surface mount device 170 is, for example, a passive device such as a resistor, a capacitor or an inductor. In this embodiment, the second surface mount device 170 is disposed on the lower surface of the second substrate 130 and is connected to the first surface mount device 160 by at least one solder 175. Since the first surface mount device 160 and the second surface mount device 170 are vertically stacked, the lateral dimension of the stacked semiconductor structure 100 can be reduced. In addition, the second surface mount device 170 has a similar dimension to the first surface mount device 160, and thus the description thereof is omitted.
The second surface mount device 170 is electrically connected to the fourth circuit layer 133 through the second conductive via 134, and is electrically connected to an external ground, an external ac power source, or an external dc power source through the fourth circuit layer 133. In addition, the height H1 of the first surface mount component 160 and the second surface mount component 170 after being abutted is greater than the total thickness of the first semiconductor chip 120 and the second semiconductor chip 140, so that a space S is formed between the first semiconductor chip 120 and the second semiconductor chip 140, and the space S can accommodate the bonding wire 125, so that the bonding wire 125 cannot easily interfere with the second semiconductor chip 140. In addition, the package body 150 fills the space S to further fix the bonding wires 125, the first semiconductor chip 120 and the second semiconductor chip 140.
The first surface mount device 160 and the second surface mount device 170 can be connected in parallel. In detail, the first surface mount device 160 includes a first contact 160a and a second contact 160b, and the second surface mount device 170 includes a first contact 170a and a second contact 170b, wherein the first contact 160a and the second contact 160b of the first surface mount device 160 are respectively connected to the first contact 170a and the second contact 170b of the second surface mount device 170 in parallel. However, the embodiment of the invention is not limited thereto, and the first surface mount device 160 and the second surface mount device 170 may be connected in series, for example, the first contact 160a of the first surface mount device 160 is connected in series with the second contact 170b of the second surface mount device 170; or the second contact 160b of the first surface mount device 160 is connected in series with the first contact 170a of the second surface mount device 170.
Referring to fig. 1B, a top view of fig. 1A is shown (for clarity, fig. 1B does not show the first substrate 130, the second semiconductor chip 140 and the second surface mount device 170). A predetermined circuit structure can be obtained by serial/parallel connection of the surface mount devices. Taking the first surface mount devices 161 as an example, one of the first surface mount devices 161 is an inductor, and includes a first contact 161a and a second contact 161b, wherein the first contact 161a is grounded through the first conductive hole 114', and the second contact 161b is electrically connected to the outside through the first conductive hole 114 ″ and is electrically connected to the first semiconductor chip 120 through the first circuit layer 112 and the bonding wire 125, so that static electricity from the outside can be conducted to the ground end electrically connected to the first conductive hole 114' through the first conductive hole 114 ″ and the second contact 161b, thereby preventing the static electricity from damaging the first semiconductor chip 120.
In another example, the first surface mount device 161 is a capacitor, wherein the first contact 161a is grounded through the first conductive via 114', and the second contact 161b is electrically connected to an external power source through the first conductive via 114 ″ and electrically connected to the first semiconductor chip 120 through the first circuit layer 112 and the bonding wire 125, so that direct current interference (Noise) or low frequency interference of the external power source can be conducted to the ground electrically connected to the first conductive via 114' through the first surface mount device 161.
In another example, the first surface mount device 161' is a capacitor, for example, which is connected in series with the first semiconductor chip 120 to form a DC blocking device (DC blocking) for blocking a DC signal from entering the first semiconductor chip 120.
In other examples, the two first surface mount devices 162 are connected in series and electrically connected to the first semiconductor chip 120 through the first circuit layer 112 and the bonding wires 125. In detail, each of the two first surface mount devices 162 includes a first contact 162a and a second contact 162b, wherein the first contact 162a of one first surface mount device 162 is electrically connected to the second contact 162b of the other first surface mount device 162 directly or through the first circuit layer 112. In this embodiment, the two first surface mount devices 162 are resistors, and the first semiconductor chip 120 is electrically connected between the two first surface mount devices 162 through the bonding wires 125 and the first circuit layer 112 to form a voltage divider circuit (Bias circuit).
In another example, another two first surface mount devices 163 can be connected in parallel. In detail, each of the two first surface mount components 163 includes a first contact 163a and a second contact 163b, wherein the first contact 163a and the second contact 163b of one first surface mount component 163 are electrically connected to the first contact 163a and the second contact 163b of the other first surface mount component 163 directly or through the first circuit layer 112 and are connected in parallel.
Referring to fig. 2, a top view of a stacked semiconductor structure according to another embodiment of the invention is shown. In this embodiment, the first surface mount device 164 is, for example, an inductor, and includes a first terminal 164a and a second terminal 164b, wherein the first terminal 164a is electrically connected to a Direct Current (DC) power source through the first conductive via 114, and the second terminal 164b is electrically connected to the first semiconductor chip 120 and the antenna 126 or the high frequency circuit, so that the high frequency signal from the antenna 126 or the high frequency circuit is not conducted to the DC power source electrically connected to the first conductive via 114 through the first surface mount device 164. Structurally, the antenna 126 (or the high frequency circuit) may be at least a part of the fourth circuit layer 133 or an antenna layer additionally formed on the upper surface 131u of the second substrate 131.
Referring to fig. 3, a top view of a stacked semiconductor structure according to another embodiment of the invention is shown. In this example, three first surface mount components 165', 165 ", and 165'" are connected in series to form a pi impedance match, wherein the first surface mount component 165 "is coupled between the first surface mount component 165 'and the first surface mount component 165'". The first contact 165a of the first surface mount device 165' is electrically connected to the ground terminal through the first conductive via 114, and the second contact 165b of the first surface mount device 165 is electrically connected to the antenna 126 and the first surface mount device 165 ".
The above-mentioned circuit features composed of the first surface mount device 160 are only some embodiments of the present invention. According to the spirit of the present invention, various circuits such as a filter (filter), a balun (balun), a power divider (power divider), a diplexer (duplexer), an attenuator (attenuator) or the like may be designed by connecting a plurality of first surface mount devices 160 in series/parallel. In addition, the connection manner of the second surface mount component 170 is similar to that of the first surface mount component 160, and thus the description thereof is omitted. In addition, the first surface mount device 160 and the second surface mount device 170 can be connected in series or in parallel in a similar manner.
Referring to fig. 4, a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention is shown. The stacked semiconductor structure 200 includes a first substrate 110, at least one first semiconductor chip 120, a second substrate 130, at least one second semiconductor chip 140, a first package 151, a second package 152, at least one first surface mount device 160, and at least one second surface mount device 170.
The first package 151 and the second package 152 are independently formed packages, wherein the first package 151 encapsulates the first semiconductor chip 120 and the first surface mount device 160, and the second package 152 encapsulates the second semiconductor chip 140 and the second surface mount device 170. The first package 151 and the second package 152 may be made of a material similar to that of the package 150, and thus, the description thereof is omitted. In addition, the materials of the first package 151 and the second package 152 may be the same or different.
Although the stacking of two layers of surface mount devices is described as an example between the first substrate 110 and the second substrate 130 in the above embodiment, more than two layers of surface mount devices may be stacked between the first substrate 110 and the second substrate 130; alternatively, a single layer of surface mount devices may be stacked, as illustrated in FIG. 5 below.
Referring to fig. 5, a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention is shown. The stacked semiconductor structure 300 includes a first substrate 110, at least one first semiconductor chip 120, a second substrate 130, at least one second semiconductor chip 140, a package body 150 and at least one first surface mount device 160.
In this embodiment, the surface mount devices between the first substrate 110 and the second substrate 130 are single first surface mount devices 160, or devices in the same stacked layer. The first contact 160a and the second contact 160b of the first surface mount device 160 are respectively connected to the upper surface of the first substrate 110 and the lower surface of the second substrate 130, and electrically connected to the first substrate 110 and the second substrate 130. In this embodiment, the first surface mount device 160 can be used as a transmission medium for electrical signals between the first substrate 110 and the second substrate 130, and does not provide a circuit function, but can also provide a circuit function, such as a passive device function.
The distance H2 between the first contact 160a and the second contact 160b of the first surface mount device 160 is greater than the total thickness of the first semiconductor chip 120 and the second semiconductor chip 140, so that a space S is formed between the first semiconductor chip 120 and the second semiconductor chip 140. The package body 150 fills the space and covers the bonding wires 125, thereby further fixing the bonding wires 125, the first semiconductor chip 120 and the second semiconductor chip 140.
Referring to fig. 6, a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention is shown. Stacked semiconductor structure 400 includes stacked semiconductor structure 100 and stacked semiconductor structure 300, which are stacked on top of each other. The second circuit layer 113 of the stacked semiconductor structure 100 is stacked on and electrically connected to the fourth circuit layer 133 of the stacked semiconductor structure 300, such that the semiconductor chips 120 and 140 of the stacked semiconductor structure 100 are electrically connected to the semiconductor chips 120 and 140 of the stacked semiconductor structure 300 through the first circuit layer 112, the second circuit layer 113, the fourth circuit layer 133 of the stacked semiconductor structure 300, and the third circuit layer 132.
Although the stacked semiconductor structure of fig. 6 is illustrated as stacking two semiconductor structures, more than two semiconductor structures may be stacked.
Referring to fig. 7, a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention is shown. The stacked semiconductor structure 500 includes a first substrate 510, at least one first semiconductor chip 120, a second substrate 530, at least one second semiconductor chip 140, a first package 151, a second package 152, at least one first surface mount device 160, at least one second surface mount device 170, and a shielding film 580.
The first substrate 510 includes a first substrate 111, a first circuit layer 112, a second circuit layer 113, at least one first conductive via 114, and at least one first ground element 515. The upper surface 111u of the first base 111 and the upper surface 112u of the first circuit layer 112 together define an upper surface of the first substrate 510. The first circuit layer 112 and the second circuit layer 113 are respectively formed on the upper surface 111u and the lower surface 111b of the first substrate 111 to electrically connect the components thereon. The first conductive via 114 extends between the upper surface 111u and the lower surface 111b of the first substrate 111, and electrically connects the first circuit layer 112 and the second circuit layer 113. The first grounding element 515 extends between the upper surface 111u and the lower surface 111b of the first substrate 111, and is exposed from the outer surface 111s of the first substrate 111 to be electrically connected to the shielding film 580. The first grounding element 515 is, for example, a grounding rod, and is electrically connected to a grounding terminal (not shown), so that the first surface mount device 160 can be electrically connected to the grounding terminal through the first grounding element 515. However, the first surface mount device 160 can also be electrically connected to the ground terminal through the shielding film 580 and the first ground element 515.
The first semiconductor chip 120 is, for example, a flip chip, which is disposed on the upper surface of the first substrate 510 with its active surface facing downward and is electrically connected to the first circuit layer 112 through at least one solder ball. The first semiconductor chip 120 can be electrically connected to the second substrate 530 through the first circuit layer 112 and the first surface mount device 160. In another example, the first semiconductor chip 120 may also be disposed on the upper surface of the first substrate 510 with the active surface facing upward and electrically connected to the first circuit layer 112 through at least one bonding wire.
The second substrate 530 includes the second base 131, the third circuit layer 132, the fourth circuit layer 133, at least one second conductive via 134, and at least one second ground 535. The lower surface 131b of the second base 131 and the lower surface 132b of the third circuit layer 132 together define an upper surface of the second substrate 530. The third circuit layer 132 and the fourth circuit layer 133 are respectively formed on the upper surface 131u and the lower surface 131b of the second substrate 131 to electrically connect the devices thereon. The second conductive via 134 extends between the upper surface 131u and the lower surface 131b of the second substrate 131 and electrically connects the third circuit layer 132 and the fourth circuit layer 133. The second grounding element 535 extends between the upper surface 131u and the lower surface 131b of the second substrate 131, and is exposed from the outer side surface 131s of the second substrate 131 to be electrically connected to the shielding film 580. The second grounding member 535 can be electrically connected to the ground terminal through the second substrate 530, the first surface mount device 160 and the first conductive via 114 of the first substrate 510; alternatively, the first grounding member 515 of the first substrate 510 and the shielding film 580 may be electrically connected to the ground terminal.
The second semiconductor chip 140 is disposed on the upper surface of the second substrate 530 with the active surface facing upward, and is electrically connected to the third circuit layer 132 through at least one bonding wire. The second semiconductor chip 140 can be electrically connected to the first substrate 530 through the third circuit layer 132, the second surface mount device 170 and the first surface mount device 160. In another example, the second semiconductor chip 140 is, for example, a flip chip, which is disposed on the upper surface of the second substrate 530 with its active surface facing downward and electrically connected to the third circuit layer 132 through at least one solder ball.
The shielding film 580 is formed on the outer side surface 111s of the first substrate 111, the outer side surface 131s of the second substrate 131, the outer side surface 515s of the first ground element 515, the outer side surface 535s of the second ground element 535, the outer side surface 151s of the first package 151, and the outer side surface 152s of the second package 152, and is electrically connected to the ground terminal through the first ground element 515 and/or the second ground element 535.
The shielding film 580 is made of aluminum, copper, chromium, tin, gold, silver, nickel, stainless steel or a combination thereof, and can be formed by Chemical Vapor Deposition (CVD), electroless plating (electroless plating), electroplating, printing (printing), spraying (sputtering), sputtering or vacuum Deposition (vacuum Deposition). The shielding film 580 may be a single layer or a multi-layer material. For example, the shielding film 580 has a three-layer structure with an inner stainless steel layer, a middle copper layer, and an outer stainless steel layer; alternatively, the shielding film 580 has a two-layer structure with an inner copper layer and an outer stainless steel layer.
Referring to fig. 8, a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention is shown. The stacked semiconductor structure 600 includes a first substrate 610, at least one first semiconductor chip 120, a second substrate 630, at least one second semiconductor chip 140, a first package 151, a second package 152, at least one first surface mount device 160, at least one second surface mount device 170, and a shielding film 580.
The first substrate 610 includes a first substrate 111, a first circuit layer 112, a second circuit layer 113, at least one first conductive via 114, at least one first ground element 515, and a first shielding layer 616. The first shielding layer 616 is electrically connected to the first ground element 515. The first shielding layer 616 is formed inside the first substrate 111 and laterally extends to protect the first semiconductor chip 120 from electromagnetic interference. In addition, the first shielding layer 616 continuously extends inside the first substrate 111 and has at least one opening 616a to isolate the first conductive via 114 and prevent the first conductive via 114 from being electrically shorted with the first shielding layer 616.
The second substrate 630 includes a second base 131, a third circuit layer 132, a fourth circuit layer 133, at least one second conductive via 134, at least one second grounding member 535, and a second shielding layer 636. The second shielding layer 636 is electrically connected to the second ground element 535. The second shielding layer 636 is formed inside the second substrate 131 and laterally extends to protect the first semiconductor chip 120 and the second semiconductor chip 140 from electromagnetic interference. Further, the first semiconductor chip 120 is surrounded by the first shielding layer 616, the second shielding layer 636 and the shielding film 580, so that the first semiconductor chip 120 can be prevented or reduced from being negatively affected by electromagnetic interference. Similarly, the second semiconductor chip 140 is surrounded by the second shielding layer 636 and the shielding film 580, so that the second semiconductor chip 140 can be prevented or influenced negatively by electromagnetic interference.
Referring to fig. 9, a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention is shown. The stacked semiconductor structure 700 includes a first substrate 510, at least one first semiconductor chip 120, a second substrate 530, at least one second semiconductor chip 140, a first package 151, a second package 152, at least one first surface mount device 160, at least one second surface mount device 170, and a shielding film 580. In this embodiment, the configuration of the first surface mount device 160 is similar to the first surface mount device 160 of the stacked semiconductor structure 300 of fig. 5, and the description thereof is omitted.
Referring to fig. 10A to 10G, a process of fabricating the stacked semiconductor structure of fig. 1A is illustrated.
As shown in fig. 10A, a first substrate 110 is provided. The first substrate 110 includes a first base 111, a first circuit layer 112, a second circuit layer 113, and at least one first conductive via 114. The upper surface 111u of the first base 111 and the upper surface 112u of the first circuit layer 112 define an upper surface of the first substrate 110. The first circuit layer 112 and the second circuit layer 113 are respectively formed on the upper surface 111u and the lower surface 111b of the first substrate 111, and the first conductive via 114 penetrates through the first substrate 111 and electrically connects the first circuit layer 112 and the second circuit layer 113.
As shown in fig. 10B, at least one first semiconductor chip 120 is disposed on the upper Surface of the first substrate 110 by, for example, Surface Mount Technology (SMT), and the first semiconductor chip 120 and the first circuit layer 112 are electrically connected by at least one bonding wire 125.
As shown in fig. 10C, at least one first surface mount device 160 is disposed on the upper surface of the first substrate 110 by, for example, a surface mount technology. The first surface mount device 160 is electrically connected to the second circuit layer 113 and the first semiconductor chip 120 through the first circuit layer 112.
As shown in fig. 10D, at least one solder 175 is formed on the first contact 160a and the second contact 160b of the first surface mount device 160.
As shown in fig. 10E, a combination structure of the second substrate 130, the second semiconductor chip 140 and the second surface mount device 170 is formed by a process similar to that shown in fig. 10A to 10D. Then, the second surface mount component 170 is abutted with the first surface mount component 160, for example, by surface mount technology or other suitable bonding technology. Then, a reflow process is performed to bond the second surface mount device 170 and the first surface mount device 160 by the solder 175.
As shown in fig. 10F, the package body 150 is formed by, for example, compression molding, injection molding, liquid encapsulation or transfer molding, so as to encapsulate a portion of the upper surface of the first substrate 110, a portion of the lower surface of the second substrate 130, the first semiconductor chip 120, the first surface mounting element 160, the bonding wires 125, the second semiconductor chip 140 and the second surface mounting element 170.
As shown in fig. 10G, the structure of fig. 10F is singulated. For example, a cutter or a laser is used to form at least one scribe line P1 passing through the second substrate 130, the package body 150 and the first substrate 110, so as to form at least one stacked semiconductor structure 100 as shown in fig. 1A.
Referring to fig. 11A to 11E, a process of manufacturing the stacked semiconductor structure of fig. 4 is shown.
As shown in fig. 11A, a first package body 151 is formed to cover the first semiconductor chip 120, the first surface mount device 160 and the bonding wires 125 by, for example, compression molding, injection molding or transfer molding.
As shown in fig. 11B, a portion of the material of the package body 150 is removed by, for example, grinding until the first contact 160a and the second contact 160B of the first surface mount device 160 are exposed.
As shown in fig. 11C, at least one solder 175 is formed on the first surface mount device 160 exposed on the first contact 160a and the second contact 160b of the package body 150.
As shown in fig. 11D, a combination structure of the second substrate 130, the second semiconductor chip 140, the second package body 152 and the second surface mount device 170 is formed by a process similar to that shown in fig. 11A to 10C. Then, the second surface mount component 170 is mated with the first surface mount component 160, such as by surface mount technology or other suitable bonding technology. Then, a reflow process is performed to bond the second surface mount device 170 and the first surface mount device 160 by the solder 175.
As shown in fig. 11E, the structure of fig. 11D is singulated. For example, a cutting tool or a laser is used to form at least one scribe line P1 passing through the second substrate 130, the first package 151, the second package 152 and the first substrate 110, so as to form at least one stacked semiconductor structure 200 as shown in fig. 4.
The manufacturing process of the stacked semiconductor structure 300 of fig. 5 is similar to the manufacturing process of the stacked semiconductor structure 100 of fig. 1A, and thus the description thereof is omitted. In the fabrication process of stacked semiconductor structure 400 of fig. 6, stacked semiconductor structure 100 is stacked on stacked semiconductor structure 300.
Referring to fig. 12A to 12C, a process diagram of the stacked semiconductor structure of fig. 7 is shown.
As shown in fig. 12A, a combined structure of the first substrate 510, the first semiconductor chip 120, the first package body 151 and the first surface mount device 160 is provided, and the forming process of the combined structure is similar to the manufacturing process of fig. 11A to 11B. Moreover, a combined structure of the second substrate 530, the second semiconductor chip 140, the second package body 152 and the second surface mount device 170 is provided, and the forming process of the combined structure is similar to the manufacturing process of fig. 11A to 11B.
In fig. 12A, the fourth circuit layer 133 of the second substrate 530 is stacked on the first surface mount device 160 by, for example, a surface mount technology, so that the second semiconductor chip 140 can be electrically connected to the first semiconductor chip 120 through the third circuit layer 132, the fourth circuit layer 133 and the first surface mount device 160.
As shown in fig. 12B, the structure of fig. 12A is disposed on a carrier 190. Then, for example, a cutting tool or a laser is used to form at least one cutting path P1 passing through the second package 152, the second substrate 530, the first package 151, the first substrate 510 and a portion of the carrier 190 to cut off the entire structure shown in fig. 12A, such a cutting method is called full cut.
As shown in fig. 12C, a shielding film 580 is formed to cover the outer side surface 111s of the first substrate 111, the outer side surface 131s of the second substrate 131, the outer side surface 515s of the first ground element 515, the outer side surface 535s of the second ground element 535, the outer side surface 151s of the first package 151, and the outer side surface 152s of the second package 152 by using a technique such as chemical vapor deposition, electroless plating, electroplating, printing, spraying, sputtering, or vacuum deposition, so as to form at least one stacked semiconductor structure 500 shown in fig. 7. The shielding film 580 is electrically connected to a ground terminal (not shown) through the first ground element 515 and/or the second ground element 535.
The manufacturing processes of the stacked semiconductor structure 600 of fig. 8 and the stacked semiconductor structure 700 of fig. 9 and the manufacturing process similar to the stacked semiconductor structure 500 of fig. 7 are not repeated.
Referring to fig. 13A, a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention is shown. The stacked semiconductor structure 800 may include, but is not limited to, a first substrate 110, at least one surface mount element 160, a package body 150, a shielding film 580, a conductive connection material 18, and a second substrate 130.
As shown in fig. 13A, the first substrate 110 has an upper surface 111u, a lower surface 111b, and a side surface 111S. The lower surface 111b is opposite to the upper surface 111 u. The side surface 111S connects the upper surface 111u and the lower surface 111 b. In embodiments of the present invention, the first substrate 110 may be or may include, but is not limited to, an organic substrate, glass, silicon dioxide, or other silicide, for example. The upper surface 111u of the first substrate 110 may have connection pads (not shown) or traces (not shown) thereon, which may be electrically connected to a ground layer (not shown) of the first substrate 110 via an inter-layer circuit (not shown). The first substrate 110 may have a thickness from 10 μm to 3000 μm, for example, in an embodiment of the present invention, the thickness may be a distance between the first surface 101 and the second surface 102.
At least one surface mount component 160 is located on the upper surface 111u of the first substrate 110 and has a first contact 160a and a second contact 160 b. The first contact 160a and the second contact 160b are respectively attached to the upper surface 111u of the first substrate 110, wherein the second contact 160b of the at least one surface mount device 160 can be connected to the connection pad or trace for electrically connecting with the ground layer of the first substrate 110. In an embodiment of the present invention, the at least one surface mount component 160 may be, but is not limited to, a two-terminal package (two-terminal package) component with an imperial code (imperial code) of 0603, or a two-terminal package component with a metric code (metric code) of 1608, for example. For example, the at least one surface mount component 160 may have a length of substantially 1.6 millimeters (mm), a width of 0.8mm, and a height of 0.8 mm. The at least one surface mount component 160 may be, but is not limited to, a passive component (e.g., a capacitor or an inductor), a discrete component (e.g., a transistor or a diode), or other two terminal package component. In an embodiment of the present invention, the height of at least one surface mount component 160 is relatively greater than the height of other components on the upper surface 111 u. At least one surface mount component 160 connects the first substrate 110 and the second substrate 130 to form a receiving space for receiving other components (described later) on the upper surface 111 u. In another embodiment (not shown), the height of the at least one surface mount component 160 may be relatively smaller than the height of other components on the upper surface 111u, and the at least two surface mount components 160 may be stacked to have a height relatively larger than the height of other components on the upper surface 111 u. The at least two surface mount devices 160 are electrically connected, one of the at least two surface mount devices is electrically connected to the first substrate 110, and the other of the at least two surface mount devices is electrically connected to the second substrate 130, so as to form a receiving space for receiving other devices on the upper surface 111 u.
The stacked semiconductor structure 800 may further include, but is not limited to, a radio frequency Front End Module (FEM) 110a, a Transceiver chip set (Transceiver chip) 110b, a Memory (Memory)110c, a surface mount device (smt) 110d, a regulator (regulator)110e, and a Micro Controller (MCU)/Application-specific integrated circuit (ASIC) 110 f. The rf front-end module 110a, the transceiver chipset 110b, the memory 110c, the surface mount device 110d, the voltage regulator 110e and the micro-controller/asic 110f can be connected to the circuits on the upper surface 111u of the first substrate 110 by wire bonding, soldering or flip chip technique according to the device package type.
A package (encapsulation material)150 is located on the upper surface 111u of the first substrate 110, and has an upper surface 1501 and a side surface 1502, and the side surface 1502 of the package 150 is flush with the side surface 111S of the first substrate 110, so that the stacked semiconductor structure 800 has a relatively flat appearance and a small size. The package body 150 covers the upper surface 111u of the first substrate 110 and the at least one surface mount component 160, and exposes the first contact 160a and the second contact 160b of the at least one surface mount component 160. The encapsulant 150 may be or may include, but is not limited to, for example, novolac resin (novolac resin), Epoxy resin (Epoxy resin), silicone resin (silicone resin), or other suitable materials.
Shielding film 580 is an electromagnetic wave shielding (EMI shielding) mask, which may be, but is not limited to, a conformal shielding (conformal shielding). The shielding film 580 includes a first shielding layer 5801 and a second shielding layer 5802, and the first shielding layer 5801 is connected to the second shielding layer 5802. The first shielding layer 5801 covers the side 111S of the first substrate 110 and the side 1502 of the package body 150. The first shielding layer 5801 has a lower surface substantially flush with the lower surface 111b of the first substrate 110, and can completely cover the first substrate 110 to effectively isolate electromagnetic wave interference. The second shielding layer 5802 covers a portion of the upper surface 1501 of the package body 150 and a portion of the at least one surface mount component 160. The second shielding layer 5802 exposes the first contact 160a of the at least one surface mount component 160 and the second contact 160b contacting the at least one surface mount component 160. The shielding film 580 is electrically connected to the ground layer of the first substrate 110. In embodiments of the present invention, shielding film 580 may be formed in a manner that may include, but is not limited to, for example, by chemical vapor deposition, electroless plating, electrolytic plating, spraying, printing, and sputtering. The shielding film 580 may be or may include, but is not limited to, aluminum, copper, chromium, tin, gold, silver, nickel, stainless steel, or other suitable metal or alloy, for example.
A conductive connection material 18 is located on the upper surface 1501 of the package body 150. The conductive connection material 18 includes a first conductive connection material 181 and a second conductive connection material 182. The first conductive connecting material 181 is electrically isolated from the second conductive connecting material 182, so that a short circuit phenomenon is not generated. The first conductive connection material 181 is connected to the first contact 160a of the at least one surface mount component 160 and the second conductive connection material 182 is connected to the second shielding layer 5802. In an embodiment of the present invention, the conductive connection material 18 may be, but is not limited to, a conductive adhesive. In another embodiment of the present invention, the conductive connection material 18 may be, but is not limited to, solder (solder).
The second substrate 130 is located above the upper surface 1501 of the package body 150. The second substrate 130 has an upper surface 131u, a lower surface 131b, and a side surface 131S. Lower surface 131b is opposite to upper surface 131 u. In embodiments of the present invention, the second substrate 130 may be or may include, but is not limited to, for example, silicon dioxide, or other silicides. The second substrate 130 may have a thickness from 10 μm to 3000 μm, for example, in an embodiment of the present invention, the thickness may be a distance between the upper surface 131u and the lower surface 131 b.
A third trace layer 132 is formed on the lower surface 131b of the second substrate 130. The third trace layer 132 includes a first metal layer 132f and a second metal layer 132 g. The first and second metal layers 132f and 132g are separated by a space 132S to avoid short circuits. In an embodiment of the present invention, the first metal layer 132f may be, but is not limited to, a connection pad (connection pad), for example, and the second metal layer 132g may be, but is not limited to, a ground pad (ground pad), for example. First metal layer 132f and second metal layer 132g may be or may include, but are not limited to, copper or other suitable metals or alloys, for example. In another embodiment of the present invention, the first and second metal layers 132f and 132g may be composed of different metals or alloys. The first metal layer 132f may have a thickness from 1 μm to 72 μm, and the second metal layer 132g has a thickness from 1 μm to 72 μm. In the embodiment of the present invention, the area of the second metal layer 132g is relatively larger than that of the first metal layer 132 f. In another embodiment of the present invention, the second metal layer 132g can be used as, but not limited to, a ground plane of the second substrate 130. In the embodiment of the present invention, the second metal layer 132g is formed on the lower surface 131b of the second substrate 130 and is electrically connected to the ground layer of the first substrate 110 through the shielding film 580. As shown in fig. 13A, the area of the second substrate 130 is relatively larger than that of the second shielding layer 5802, and the area of the second metal layer 132g is relatively larger than that of the second shielding layer 5802, so that the shielding area of the second metal layer 132g is larger, and the preferred metal shielding effect is achieved.
The second substrate 130 includes a conductive via 134. The conductive vias 134 include at least one first conductive via 134a and at least one second conductive via 134 b. At least one first conductive via 134a extends through the second substrate 130 to connect the first metal layer 132f with the fourth trace layer 133. And at least one second conductive via 134b extends through the second substrate 130 to connect the second metal layer 132g with the fourth trace layer 133. In the embodiment of the present invention, the at least one first conductive via 134a and the at least one second conductive via 134b may be, but not limited to, cylinders, cones, or other shapes, and the at least one first conductive via 134a and the at least one second conductive via 134b may be formed on the second substrate 130 by laser, sandblasting (sandblasting), and/or etching, if necessary. The openings of the at least one first conductive via 134a and the at least one second conductive via 134b at the upper surface 131u and the lower surface 131b may include, but are not limited to, a circle, a square, or other shapes.
The antenna 126 is formed on the upper surface 131u of the second substrate 130. The antenna 126 may be at least a portion of the fourth trace layer 133 or an antenna layer additionally formed on the upper surface 131u of the second substrate 130. The antenna 126 connects the first at least one conductive via 134a and the at least second conductive via 134 b. In embodiments of the present invention, the antenna 126 may be or may include, but is not limited to, copper or other suitable metal or alloy, for example. The antenna 126 may have a thickness from 1 μm to 72 μm. In the embodiment of the invention, the antenna 126 is formed on the second substrate 130, and the second substrate 130 is located on the package body 150, so that the space occupied by the stacked semiconductor structure 800 disposed on the circuit board or carrier board of the device/system can be reduced to accommodate other elements or to facilitate other related designs. Since the antenna 126 is electrically connected to the first substrate 110 through the conductive via 134 formed in the second substrate 130, there is a preferable process yield compared to electrically connecting to the first substrate 110 through the conductive via formed in the package body 150.
In an embodiment of the present invention, a signal (not shown) received by the stacked semiconductor structure 800 via the antenna 126 can feed (feed) the received signal into the rf front-end module 110a via the at least one first conductive via 134a, the first metal layer 132f, the first conductive connecting material 181 and the first contact 160a of the at least one surface mount component 160, but is not limited thereto. In another embodiment of the present invention, the rf front end module 110a may transmit a signal to be transmitted to the antenna 126 via the first contact 160a of the at least one surface mount component 160, the first conductive connection material 181, the first metal layer 132f, and the at least one first conductive via 134 a. That is, the at least one first conductive via 134a, the first metal layer 132f, the first conductive connection material 181, and the first contact 160a of the at least one surface mount component 160 may serve as signal feeding and transmitting paths of the stacked semiconductor structure 800 in the embodiment of the present invention. In an embodiment of the present invention, the at least one second conductive via 134b, the second metal layer 132g, the second conductive connection material 182, and the second contact 160b of the at least one surface mount device 160 are electrically connected to a ground layer (not shown) of the first substrate 110, so as to serve as a signal return path (return path) or a ground path (ground path) of the stacked semiconductor structure 800. In another embodiment of the present invention, the at least one second conductive via 134b, the second metal layer 132g, the second conductive connection material 182, and the shielding film 580 are electrically connected to the ground layer of the first substrate 110 to serve as a signal return path or a ground path of the stacked semiconductor structure 800. In the embodiment of the present invention, when the antenna 126 is to receive or transmit a high frequency signal, the structure composed of the antenna 126, the first conductive via 134a, the second conductive via 134b, the second substrate 130, the first metal layer 132f and the second metal layer 132g may generate signal resonance at an operating frequency, so that the high frequency signal is transmitted to a circuit in the package or radiated to the air and then received by another external receiver.
In the embodiment of the present invention, when at least one surface mount device 160 is an inductor, high frequency noise from the outside can be prevented from damaging the stacked semiconductor structure 800, and can be used as electrostatic discharge (ESD) protection. In another embodiment of the present invention, when at least one surface mount device 160 is an inductor, a direct current spike (DC spike) from the outside may be grounded to avoid damaging the stacked semiconductor structure 800. In another embodiment of the present invention, when the at least one surface mount component 160 is a capacitor, it can be used as part of an impedance matching circuit to adjust the impedance of the antenna 126.
Referring to fig. 13B, a circuit diagram of the stacked semiconductor structure of fig. 13A is shown. The first metal layer 132f and the second metal layer 132g located on the lower surface 131b of the second substrate 130 of the stacked semiconductor structure 800 of fig. 13A do not contact each other. As shown in fig. 13B, a space 132S is provided between the first metal layer 132f and the second metal layer 132 g. At least one first conductive via 134a is connected to the first end 160a of at least one surface mount component 160 at an opening in the first metal layer 132f, and at least one second conductive via 134b is connected to the second end 160b of at least one surface mount component 160 at an opening in the second metal layer 132 g. As shown in the equivalent circuit in fig. 13B, at least one surface mount component 160 may be connected in parallel with the equivalent impedance 110aP of the front end module 110 a. In the embodiment of the present invention, when at least one surface mount device 160 is an inductor, the stacked semiconductor structure 800 can be protected from high frequency noise from the outside, and can be used as an electrostatic discharge (ESD) protection. In another embodiment of the present invention, when at least one surface mount device 160 is an inductor, a direct current spike (DC spike) from the outside may be grounded to avoid damaging the stacked semiconductor structure 800. In another embodiment of the present invention, when the at least one surface mount component 160 is a capacitor, it can be used as part of an impedance matching circuit to adjust the impedance of the antenna 126.
Referring to fig. 14A, a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention is shown. The stacked semiconductor structure 900 may be similar to the stacked semiconductor structure 800 except that the first and second metal layers 132f, 132g of the stacked semiconductor structure 900 have different shapes than the first and second metal layers 132f, 132g of the stacked semiconductor structure 800. And in the stacked semiconductor structure 900, the relative positions of the at least one first conductive via 134a and the at least one second conductive via 134b are different from the relative positions of the at least one first conductive via 134a and the at least one second conductive via 134b in the stacked semiconductor structure 800. The connection relationship of the at least one first conductive via 134a and the at least one second conductive via 134b to other elements in the stacked semiconductor structure 900 is similar to the connection relationship of the at least one first conductive via 134a and the at least one second conductive via 134b to other elements in the stacked semiconductor structure 800.
Referring to fig. 14B, a circuit diagram of the stacked semiconductor structure of fig. 14A is shown. The circuit of fig. 14B is similar to the circuit of fig. 13B except that the relative positions of the at least one first conductive via 134a and the at least one second conductive via 134B are different from the relative positions of the at least one first conductive via 134a and the at least one second conductive via 134B of fig. 13B. And the shapes of the first and second metal layers 132f and 132g are different from those of the first and second metal layers 132f and 132g in fig. 13B.
Referring to fig. 15, a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention is shown. The stacked semiconductor structure 810 may be similar to the stacked semiconductor structure 800 illustrated in fig. 13A, except that the second metal layer 132g of the stacked semiconductor structure 810 replaces the second conductive connection material 182 and the second shielding layer 5802 of the stacked semiconductor structure 800. The second metal layer 132g and the first shielding layer 5801 of the stacked semiconductor structure 810 form a shielding film 580. In other words, the second metal layer 132g of the stacked semiconductor structure 810 constitutes a part of the shielding film 580. The side 131S of the second substrate 130 of the stacked semiconductor structure 810 is substantially flush with the first shield layer 5801, which may have smaller dimensions relative to the stacked semiconductor structure 800 of fig. 13A.
Referring to fig. 16, a cross-sectional view of a stacked semiconductor structure according to another embodiment of the invention is shown. Stacked semiconductor structure 910 may be similar to stacked semiconductor structure 900 depicted in fig. 14A, except that second metal layer 132g of stacked semiconductor structure 910 replaces second conductive connection material 182 and second shield layer 5802 of stacked semiconductor structure 900. The second metal layer 132g and the first shielding layer 5801 of the stacked semiconductor structure 910 form a shielding film 580. In other words, the second metal layer 132g of the stacked semiconductor structure 910 constitutes a portion of the shielding film 580. The side 131S of the second substrate 130 of the stacked semiconductor structure 910 is substantially flush with the first shield layer 5801, which may have smaller dimensions relative to the stacked semiconductor structure 900 of fig. 14A.
Referring to fig. 17-21, a process diagram of the stacked semiconductor structure of fig. 13A is shown.
Referring to fig. 17, a first substrate 110, at least one surface mount component 160, an rf front end module 110a, a transceiver chipset 110b, a memory 110c, a surface mount component 110d, a voltage regulator 110e, and a microcontroller/asic 110f are provided.
The first substrate 110 has an upper surface 111u and a lower surface 111b, and the lower surface 111b opposes the upper surface 111 u.
At least one surface mount device 160 has a first contact 160a and a second contact 160b, and the first contact 160a and the second contact 160b are respectively attached to the upper surface 111u of the first substrate 110. The second contact 160b of the at least one surface mount device 160 is electrically connected to a ground plane (not shown) of the first substrate 110. In an embodiment of the present invention, the upper surface 111u of the first substrate 110 may have connection pads or traces thereon that are electrically connected to a ground plane via an interlayer circuit, and the second contacts 160b of the at least one surface mount component 160 may be connected to the connection pads or traces so as to be electrically connected to the ground plane of the first substrate 110.
At least one of the surface mount device 160, the rf front end module 110a, the transceiver chipset 110b, the memory 110c, the surface mount device 110d, the voltage regulator 110e and the micro-controller/asic 110f can be connected to the circuits on the upper surface 111u of the first substrate 110 by wire bonding, soldering or flip chip technique according to the packaging type of the respective devices. In an embodiment of the present invention, the surface mount component 110d is similar to the at least one surface mount component 160 except that the surface mount component 110d has a smaller size compared to the size of the at least one surface mount component 160, e.g., the height of the surface mount component 110d is less than the height of the at least one surface mount component 160. In an embodiment of the present invention, the height of at least one surface mount component 160 is relatively greater than the height of other components on the upper surface 111 u. In another embodiment of the present invention, the at least one surface mount component 160 may be, but is not limited to, a 0603 component and may be replaced with a terminal (terminal) component of a larger size as needed, such that the at least one surface mount component 160 is the highest-height component on the upper surface 111 u.
Referring to fig. 18, the package body 150 may be used to package at least one surface mount component 160, the rf front end module 110a, the transceiver chip set 110b, the memory 110c, the surface mount component 110d, the voltage regulator 110e, and the microcontroller/asic 110f, as well as the upper surface 111u of the first substrate 110, and expose the first and second contacts 160a and 160b of the at least one surface mount component 160. In an embodiment of the present invention, the package body 150 may be used to package the components by using an exposed molding (exposed molding) method and expose the first contact 160a and the second contact 160b of the at least one surface mounting component 160. In another embodiment of the present invention, the package body 150 may be used to encapsulate the above components by over-molding (over-mold), and then the package body 150 is ground by polishing (polishing) to expose the first contact 160a and the second contact 160b of at least one surface mounting component 160.
As shown in fig. 19, the packaged first substrate 110 may be cut along the cut path P1 in fig. 18, and a shielding film 580 may be formed along the side 111S of the packaged first substrate 110, the upper surface 1501 of the package body 150, and the side 1502 to form a package structure 800 a. In an embodiment of the present invention, a shielding film 580 may be formed along the side 111S of the first substrate 110, the upper surface 1501 of the package body 150, and the side 1502, and then a hole may be drilled in the shielding film 580 by laser drilling to expose the first contact 160a of the at least one surface mount component 160 and a portion of the package body 150. In another embodiment of the present invention, the desired pattern of the shielding film 580 may be formed using, but not limited to, a mask (mask) and electroplating.
As shown in fig. 20, a plurality of second substrates 130 may be provided, each second substrate 130 having an upper surface 131u and a lower surface 131b, the lower surface 131b being opposite to the upper surface 131 u.
The antenna 126 is formed on the upper surface 131u of the second substrate 130. A third trace layer 132 is formed on the lower surface 131b of the second substrate 130. The third trace layer 132 includes a first metal layer 132f and a second metal layer 132 g.
The second substrate 130 includes at least one first conductive via 134a and at least one second conductive via 134 b. At least one first conductive via 134a extends through the second substrate 130 to connect the antenna 126 and the first metal layer 132 f. At least one second conductive via 134b extends through the second substrate 130 to connect the antenna 126 and the second metal layer 132 g.
The conductive connection material 18 may be formed on the first and second metal layers 132f and 132g to form the package structure 800 b. In an embodiment of the present invention, the conductive connection material 18 may be, but is not limited to, a conductive adhesive. In another embodiment of the present invention, the conductive connection material 18 may be solder.
Referring to fig. 21, the first metal layer 132f of the package structure 800b of fig. 20 may be connected to the first contact 160a of the at least one surface mount device 160 of the package structure 800a of fig. 19 using the conductive connection material 18, and the second metal layer 132g of the package structure 800b of fig. 20 may be connected to the second contact 160b of the at least one surface mount device 160 of the package structure 800a of fig. 19. The package structures 800a and 800b are connected and then cut along the dicing streets P1 to form individual or single stacked semiconductor structures 800 in fig. 13A. In the embodiment of the present invention, the thickness of the cutter used for cutting the package structure in fig. 21 is smaller than the thickness of the scribe line P1, so that the side surface 131S of the second substrate 130 protrudes from the side surface 1502 of the package body 150. In another embodiment of the present invention, the thickness of the cutter used for cutting the package structure in fig. 21 is substantially close to the width of the cutting path P1, so that the side surface 131S of the second substrate 130 is substantially flush with the side surface 1502 of the package body 150, and has a relatively flat appearance and small size.
Referring to fig. 22-26, a process diagram of the stacked semiconductor structure of fig. 15 is shown.
Referring to fig. 22, a plurality of first substrates 110, at least one surface mount component 160, an rf front end module 110a, a transceiver chipset 110b, a memory 110c, a surface mount component 110d, a voltage regulator 110e, and a microcontroller/asic 110f are provided.
The first substrate 110 has an upper surface 111u and a lower surface 111b, and the lower surface 111b opposes the upper surface 111 u.
At least one surface mount device 160 has a first contact 160a and a second contact 160b, and the first contact 160a and the second contact 160b are respectively attached to the upper surface 111u of the first substrate 110. The second contact 160b of the at least one surface mount device 160 is electrically connected to a ground plane (not shown) of the first substrate 110. In an embodiment of the present invention, the upper surface 111u of the first substrate 110 may have connection pads or traces thereon that are electrically connected to a ground plane via an interlayer circuit, and the second contacts 160b of the at least one surface mount component 160 may be connected to the connection pads or traces so as to be electrically connected to the ground plane of the first substrate 110.
At least one of the surface mount device 160, the rf front end module 110a, the transceiver chipset 110b, the memory 110c, the surface mount device 110d, the voltage regulator 110e and the micro-controller/asic 110f can be connected to the circuits on the upper surface 111u of the first substrate 110 by wire bonding, soldering or flip chip technique according to the packaging type of the respective devices. In an embodiment of the present invention, the surface mount component 110d is similar to the at least one surface mount component 160 except that the surface mount component 110d has a smaller size compared to the size of the at least one surface mount component 160, e.g., the height of the surface mount component 110d is less than the height of the at least one surface mount component 160. In an embodiment of the present invention, the height of at least one surface mount component 160 is relatively greater than the height of other components on the upper surface 111 u. In another embodiment of the present invention, the at least one surface mount component 160 may be, but is not limited to, a 0603 component and may be replaced with a terminal (terminal) component of a larger size as needed, such that the at least one surface mount component 160 is the highest-height component on the upper surface 111 u.
A plurality of second substrates 130 are provided, each second substrate 130 having an upper surface 131u and a lower surface 131b, the lower surface 131b being opposite to the upper surface 131 u. The antenna 126 is formed on the upper surface 131u of the second substrate 130. A third trace layer 132 is formed on the lower surface 131b of the second substrate 130. The third trace layer 132 includes a first metal layer 132f and a second metal layer 132 g.
The second substrate 130 includes at least one first conductive via 134a and at least one second conductive via 134 b. At least one first conductive via 134a extends through the second substrate 130 to connect the antenna 126 and the first metal layer 132 f. At least one second conductive via 134b extends through the second substrate 130 to connect the antenna 126 and the second metal layer 132 g.
As shown in fig. 22, the first metal layer 132f may be connected to the first end 160a of the at least one surface mount component 160 and the second metal layer 132g may be connected to the second end 160b of the at least one surface mount component 160 using a conductive connection material 18, such as solder 18.
Referring to fig. 23, at least one surface mount component 160, the rf front-end module 110a, the transceiver chipset 110b, the memory 110c, the surface mount component 110d, the voltage regulator 110e, the microcontroller/asic 110f, and the upper surface 111u of the first substrate 110 may be encapsulated (encapsulated) with a package body 150 to form a package structure 810 a. In the embodiment of the present invention, the encapsulation process may be performed by injecting the encapsulation body 150 into a space between the first substrate 110 and the second substrate 130 (a space between the upper surface 111u of the first substrate 110 and the lower surface 131b of the second substrate 130) after the at least one surface mount component 160 is connected by using, but not limited to, an opening (not shown) of the first substrate 110 as a molding channel. In another embodiment of the present invention, the package body 150 may be injected into a space between the upper surface 111u of the first substrate 110 and the lower surface 131b of the second substrate 130 using the second substrate 130 as a Mold for injection molding (Mold Chase), so that an additional Mold is not required in the process, which may reduce the cost.
Referring to fig. 24, a trench 5801a may be formed in the package structure 810a of fig. 23. In the embodiment of the present invention, a cutter, but not limited to, may be used to cut from the lower surface 111b of the first substrate 110 toward the upper surface 111u to form the trench 5801a in the first substrate 110 and the encapsulation 150 of the unclad element, and stop the cutting action when reaching the surface of the second metal layer 132g of the second substrate 130. In other words, the trench 5801a extends from the lower surface 111b of the first substrate 110 to the second metal layer 132g of the second substrate 130.
Referring to fig. 25, a trench 5801a may be filled with a conductive material to form a first shielding layer 5801. The conductive material may be, but is not limited to, a conductive glue, for example. The first shielding layer 5801 may contact or electrically connect with the ground plane of the first substrate 110. In other words, the first shielding layer 5801 may electrically connect the second metal layer 132g and the ground plane of the first substrate 110.
Referring to fig. 26, the package structure 810a connected in fig. 25 may be cut along the dicing street P1 using a dicing technique to form the stacked semiconductor structure 810 shown in fig. 15. In an embodiment of the present invention, a cutter, but not limited to, may be used to cut the connected package structure 810a along the cutting path P1 of fig. 25 from the first shielding layer 5801 through the second metal layer 132g, the second substrate 130 and the antenna 126 to form the stacked semiconductor structure 810 as shown in fig. 15. In an embodiment of the present invention, the thickness of the tool used to cut the package structure of fig. 25 is smaller than the thickness of the tool used to form trench 5801a of fig. 24. . As shown in fig. 26 and 15, in an embodiment of the present invention, the length of the second substrate 130 of the stacked semiconductor structure 810 may be greater than the length of the first substrate 110. In other words, the side 111S of the first substrate 110 and the side 131S of the second substrate 130 of the stacked semiconductor structure 810 are not flush.
Fig. 27A is a schematic diagram of the antenna of the stacked semiconductor structure of fig. 13A. In an embodiment of the invention, the antenna 126 of the stacked semiconductor structure 800 of fig. 13A may be patterned as shown in fig. 27A. A rectangular slot 1261 may be formed in the metal layer 126 having a rectangular or square shape to form a slot antenna 126. In another embodiment of the present invention, the antenna 126 may have other patterns, such as a loop antenna (loop antenna).
Fig. 27B is a schematic diagram illustrating reflection loss of the antenna of fig. 27A. When the stacked semiconductor structure 800 of fig. 13A has the slot antenna 126 of fig. 27A, the reflection loss (return loss) of the signal is as shown in fig. 27B, wherein the frequency and the reflection loss corresponding to the point m1 are 2.404GHz and 9.364dB, respectively, the frequency and the reflection loss corresponding to the point m2 are 2.480GHz and 9.461dB, respectively, and the frequency and the reflection loss corresponding to the point m3 are 2.440GHz and 25.059dB, respectively. In other words, the stacked semiconductor structure 800 of fig. 13A has a relatively small reflection loss ratio when the operating frequency is in the vicinity of 2.440 GHz. Thus, the stacked semiconductor structure 800 of the present disclosure may operate effectively, but is not limited to, around an operating frequency of 2.440 GHz.
Referring to fig. 28A, a schematic diagram of an antenna of the stacked semiconductor structure of fig. 13A is shown. In an embodiment of the invention, the antenna 126 of the stacked semiconductor structure 800 of fig. 13A may be, but is not limited to, a loop antenna (loop antenna) 126. The antenna 126 includes at least one first conductive via 134a as a signal feed terminal and at least one second conductive via 134b as a ground terminal.
Please refer to fig. 28B, which illustrates a reflection loss diagram of the antenna of fig. 28A. When the stacked semiconductor structure 800 of fig. 13A has the loop antenna 126 of fig. 28A, the reflection loss of the signal is shown in fig. 28B. The stacked semiconductor structure 800 of figure 13A has a relatively small reflection loss ratio when the operating frequency is near 2.450 GHz. Thus, the stacked semiconductor structure 800 of the present disclosure may operate effectively, but is not limited to, around an operating frequency of 2.450 GHz.
Referring to fig. 29A, a schematic diagram of the stacked semiconductor structure of fig. 13A applied to a system carrier is shown. The electronic device 1 includes a stacked semiconductor structure 800, a Processor (Processor)5, a sensor (sensor)7 and a Power Management unit (Power Management)9 on a system carrier 3. The processor 5 performs an operation process on the system data. The sensor 7 may include, but is not limited to, devices for detecting temperature, humidity, speed, direction, or pressure, for example. Information of the electronic device 1 may be transmitted to or received from an external device through the stacked semiconductor structure 800. The power management unit 9 provides system power and adjusts the output voltage according to the system operation state. In an embodiment of the present invention, the system carrier 3 may be, but is not limited to, for example, a rectangular substrate 3. The stacked semiconductor structure 800 may be mounted near the corners of the system carrier 3, preferably near the long sides of the rectangular carrier 3, thereby generating an induced current (described below) to improve the radiation efficiency and radiation gain, and further increase the wireless transmission distance or achieve signal transmission with less power in the same transmission distance for power saving.
Fig. 29B is a schematic view of current distribution of the antenna of the stacked semiconductor structure shown in fig. 29A. In an embodiment of the present invention, the antenna 126 may be similar to the loop antenna 126 shown in fig. 28A, with arrow a indicating the direction and intensity of the current on the loop antenna 126.
Referring to fig. 29C, a schematic view of current distribution of the system carrier and the antenna of the stacked semiconductor structure shown in fig. 29A is shown. In the embodiment of the present invention, the perimeter of the antenna 126 may be, but is not limited to, one quarter of the wavelength of the receiving or transmitting signal (1/4 λ), and the length of the long side of the system carrier board 3 is greater than or equal to one quarter of the wavelength of the receiving or transmitting signal of the antenna 126 (1/4 λ). As shown in fig. 29C, when the stacked semiconductor structure 800 is mounted on the system carrier 3, the current (shown by arrow a) on the antenna 126 will induce (excite) a reverse current (shown by arrow B) on the system carrier 3, and when the length of the long side of the system carrier 3 is greater than or equal to one quarter (1/4 λ) of the wavelength of the signal received or transmitted by the antenna 17, the current (shown by arrows a and B) will induce (induce) a current (shown by arrow C) on the long side of the system carrier 3. In the embodiment of the present invention, when the operating frequency is 2.45GHz, the peak values of the Radiation efficiency and the Radiation Gain (Radiation Gain) of the stacked semiconductor structure 800 with the antenna 126 before being mounted on the system carrier board 3 are 2% and minus 16.5dB, respectively. When the stacked semiconductor structure 800 with the antenna 126 is mounted on the system carrier 3, the peak values of the Radiation efficiency and the Radiation Gain (Radiation Gain) generated at the same operating frequency are 45% and minus 0.94dB, respectively. In other words, through the design of the antenna 126 and the system board 3, an induced current (as shown by arrow C in fig. 29C) can be generated to improve the radiation efficiency and the radiation gain, so as to increase the wireless transmission distance or complete the signal transmission with less power in the same transmission distance to achieve the power saving effect.
Referring to fig. 30, a schematic block circuit diagram of the stacked semiconductor structure of fig. 13A is shown. The stacked semiconductor structure 800 includes at least one surface mount device 160, an rf front end module 110a, a transceiver chipset 110b, a memory 110c, a surface mount device 110d, a voltage regulator 110e, and a microcontroller/asic 110f and an antenna 126. As shown in fig. 30, the transceiver chipset 110b connects the rf front-end module 110a, the memory 110c and the voltage regulator 110 e. The voltage regulator 110e is connected to the microcontroller/asic 110 f. The rf front-end module 110a is coupled to the antenna 126 through at least one surface mount component 160. Signals received by the antenna 126 are fed to the rf front-end module 110a via at least one surface mount component 160. And the signal to be transmitted is transmitted to the antenna 126 via the at least one surface mount component 160.
In another embodiment of the present invention, the stacked semiconductor structure 800 and the antenna 126 described with reference to the diagrams of fig. 27A, 28A, 29A, and 30 may also be replaced with the stacked semiconductor structure 810, 900, or 910 and the antenna 126 shown in fig. 14A, 3, or 4 without affecting the operation and benefits thereof.
In summary, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims (17)

1. A stacked semiconductor structure, comprising:
a first substrate having an upper surface;
a second substrate having an upper surface, a lower surface opposite the upper surface, at least one first conductive via, and at least one second conductive via, the lower surface of the second substrate facing the upper surface of the first substrate;
at least one passive element, which is located between the upper surface of the first substrate and the lower surface of the second substrate and has a first contact and a second contact electrically connected with the first substrate and the second substrate;
an antenna disposed on the upper surface of the second substrate, electrically connected to the first contact through the at least one first conductive via, and electrically connected to the second contact through the at least one second conductive via;
and the shielding film covers at least one passive element, exposes the first contact and contacts the second contact.
2. The stacked semiconductor structure of claim 1, further comprising a package body covering a portion of the upper surface of the first substrate, a portion of the lower surface of the second substrate, and at least one passive component, wherein the shielding film covers at least a side of the first substrate, a side of the package body, and a portion of the upper surface of the package body.
3. The stacked semiconductor structure of claim 2, further comprising a first metal layer and a second metal layer, the first metal layer and the second metal layer being located on a lower surface of the second substrate, the first metal layer connecting the at least one first conductive via, and the second metal layer connecting the at least one second conductive via.
4. The stacked semiconductor structure of claim 3, wherein the first metal layer is electrically connected to a first contact of the at least one surface mount device, and the second metal layer is electrically connected to a second contact of the at least one passive device.
5. The stacked semiconductor structure of claim 3, wherein the second metal layer constitutes a portion of the shielding film.
6. The stacked semiconductor structure of claim 2, wherein the shielding film is electrically connected to the second contact of the at least one passive component.
7. The stacked semiconductor structure of claim 3, further comprising a conductive connecting material connecting the first metal layer and the first contact of the at least one passive element.
8. The stacked semiconductor structure of claim 7, wherein the conductive connecting material connects the second metal layer and the shielding film.
9. The stacked semiconductor structure of claim 7, wherein the conductive connecting material connects the second metal layer and the second contact of the at least one passive element.
10. An electronic device, comprising:
a carrier plate having corners; and
a stacked semiconductor structure located on the corner of the carrier plate and comprising:
a first substrate;
a package body wrapping the first substrate;
a second substrate located above the package body;
an antenna disposed on an upper surface of the second substrate;
the length of the long edge of the carrier plate is greater than or equal to the perimeter of the antenna;
at least one surface mount component located between the first substrate and the second substrate and having a first contact and a second contact, the first contact and the second contact electrically connecting the first substrate and the second substrate.
11. The electronic device of claim 10, wherein the second contact of the at least one surface mount component is electrically connected to a ground plane of the first substrate.
12. The electronic device according to claim 11, wherein the second substrate comprises:
at least one first conductive via electrically connecting the antenna and the first contact of the at least one surface mount component; and
at least one second conductive via electrically connecting the antenna and the second contact of the at least one surface mount component.
13. A stacked semiconductor structure, comprising:
a first substrate having an upper surface;
a second substrate having a lower surface;
a first semiconductor chip disposed on the upper surface of the first substrate;
a second semiconductor chip disposed on the lower surface of the second substrate;
a first surface-mount component disposed between the upper surface of the first substrate and the lower surface of the second substrate and electrically connecting the first substrate and the second substrate;
a second surface mounted device disposed on the second substrate and in contact with the first surface mounted device, wherein the first surface mounted device and the second surface mounted device are passive devices; and
a package encapsulating a portion of the upper surface of the first substrate, a portion of the lower surface of the second substrate, the first semiconductor chip, the second semiconductor chip, and the first surface mount device, wherein the package comprises:
a first package body which encapsulates the portion of the upper surface of the first substrate, the first semiconductor chip and the first surface mount element; and
and a second package body which encapsulates the portion of the lower surface of the second substrate, the second semiconductor chip and the second surface mount element, wherein the first package body and the second package body are made of different materials.
14. The stacked semiconductor structure as claimed in claim 13, wherein the first surface mount device includes a first contact and a second contact, the first contact and the second contact of the first surface mount device being connected to the upper surface of the first substrate and the lower surface of the second substrate, respectively.
15. The stacked semiconductor structure as claimed in claim 13, wherein the first surface mount device and the second surface mount device each include a first contact and a second contact, the first contact and the second contact of the first surface mount device are butted against the first contact and the second contact of the second surface mount device, respectively.
16. The stacked semiconductor structure as claimed in claim 13, wherein a height of the first surface mounting element and the second surface mounting element is greater than a total thickness of the first semiconductor chip and the second semiconductor chip, such that a space is formed between the first semiconductor chip and the second semiconductor chip;
the stacked semiconductor structure further comprises:
a bonding wire located in the space.
17. The stacked semiconductor structure as claimed in claim 13, wherein the first substrate includes a first circuit layer, the second substrate includes a third circuit layer, the first surface mount device is electrically connected to the first semiconductor chip through the first circuit layer, and the second semiconductor chip is electrically connected to the first semiconductor chip through the third circuit layer and the first surface mount device.
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