CN107408534B - Switching power stage with Integrated passive assembly - Google Patents

Switching power stage with Integrated passive assembly Download PDF

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Publication number
CN107408534B
CN107408534B CN201680014046.6A CN201680014046A CN107408534B CN 107408534 B CN107408534 B CN 107408534B CN 201680014046 A CN201680014046 A CN 201680014046A CN 107408534 B CN107408534 B CN 107408534B
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China
Prior art keywords
inductor
chip
phase
switch
node
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Expired - Fee Related
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CN201680014046.6A
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Chinese (zh)
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CN107408534A (en
Inventor
塔纳·朵思路欧格鲁
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Chaoyang Semiconductor Technology Jiangyin Co ltd
Enran intellectual property Holding Co.,Ltd.
Enran Technology (Hongkong) Co.,Ltd.
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Chaoyang Semiconductor Jiangyin Technology Co Ltd
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Publication of CN107408534A publication Critical patent/CN107408534A/en
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Scalable switch mode regulator framework has integrated inductor.In some embodiments, the area of the switch of the switch mode regulator and current driving ability are matched with the inductor in the area being implemented in above the switch.In some embodiments, packet type switch and inductor are configured to unit cell and can be combined optionally to form large component and be used for high current driving capability and multiphase operation.

Description

Switching power stage with Integrated passive assembly
Background technique
The present invention generally relates to the switch mode regulator of the power for adjusting semiconductor circuit, and more particularly It is related to the integrated inductor for switch mode regulator.
Power distribution network in typical system-on-a-chip (SoC) used in various mobile devices includes via dimpling Block or copper post are connected to metalization layer on the chip of package substrate.One or more redistribution layers are used usually in encapsulation (RDL) by from or go to the signal of dimpling block or copper post and be routed to the ball of the encapsulation, the encapsulation is connected to printing electricity Road (PCB).This can produce significant parasitic inductance, and what the parasitic inductance can be the performance of these devices significantly limits factor, this It is because upper frequency and high current can generate the locally instantaneous of also referred to as decaying due to quickly changing for load current Effect.
The use of embedded voltage regulator (eVR) (usually with the switch mode regulator of inductor) can be used for reducing Or it explains and is changed by parasitic inductance bring.However, being with height with small form factor (every square millimeter of rated current) The eVR embodiment of inductance specific resistance value (L/R: inductance [nH]/every resistance [mohms]), which provides inductor, can have much challenge.
Summary of the invention
Some aspects of the invention be related to the scalable switch mode regulator framework with integrated inductor and/or be related to according to By providing the area of the structure of inductor by the method for various optimizing performance parameters.Preferably, the switch of switch mode regulator Area and current driving ability matched with the inductor in the same area that can be implemented in above the switch.In some implementations In example, packet type switch and inductor be configured to unit cell and can be combined optionally to form large component and be used for compared with High current driving capability and multiphase operation.
One aspect of the present invention is related to a kind of integrated chip package, and the integrated chip package includes: flip-chip class Integrated circuit (IC) chip of type, it includes system-on-a-chip (SoC) and switched mode voltage regulator, the switched mode voltage tune Section device includes at least first switch and second being coupled in series between higher voltage level connection and lower voltage level connection Switch；MULTILAYER SUBSTRATE has at least one inductor with chamber in the chamber, at least one described inductor, which has, to be dissipated Multiple upper trace layers of Ferrite Material are set, the inductor includes first end and second end；And multiple dimpling blocks, it will The IC chip is connected to the substrate, described comprising the node between the first switch and the second switch to be connected to The dimpling block of the first end of inductor.
Another aspect of the present invention relates to a kind of Flip-Chip Using, the Flip-Chip Using includes: flip-chip class Integrated circuit (IC) chip of type, it includes system-on-a-chip (SoC) and multi phase voltage regulator, the multi phase voltage regulators Second pair of transistor of a pair of transistor and series coupled comprising series coupled；And multilayer encapsulation substrate, with multiple Layer and the first inductor and the second inductor are redistributed, first inductor and second inductor are by multiple plating Trace is formed, and each of first inductor and second inductor include first end and second end, the multiple Plating trace formed by the intracavitary conductive layer of the multilayer encapsulation substrate, Ferrite Material in the conductive layer at least one Between a little conductive layers, and wherein be configured to will be described in first inductor at least one of more than first plating trace Second end is connected to the first end of second inductor；And multiple convex blocks, it is configured to institute at multiple nodes It states IC chip and is connected to the multilayer encapsulation substrate, the multiple node includes supply node, ground nodes, load output node And inductor node, the second end of the load output node comprising first inductor and second inductor Connection between the first end, the inductor node includes: being configured to the node between described a pair of transistor It is connected to the node of the first end of the first inductor structure；And it is configured to the node between second pair of transistor It is connected to the node of the second end of the second inductor structure.
In terms of it can be immediately appreciated by these and other of the invention after consulting the present invention.
Detailed description of the invention
Fig. 1 is the partial sectional of the system-on-a-chip (SoC) on the multilayer encapsulation substrate shown according to aspects of the present invention Face figure.
Fig. 2 sample pattern of the switch of the eVR of display diagram 1 and exemplary single-phase switch adjuster for illustrative purposes Partial circuit diagram.
The three-dimensional figure of the inductor structure of Fig. 3 offer according to aspects of the present invention and attached cross section.
Fig. 4 shows the three-dimensional figure of four phase embodiments according to aspects of the present invention.
The cross section of the inductor of Fig. 5 display diagram 4 and magnetic direction.
Fig. 6 is the partial circuit diagram using four phase switch mode regulators of the inductor of Fig. 4.
Fig. 7 shows the cross section of the inductor structure of 8 phase embodiments according to aspects of the present invention.
The step of Fig. 8 diagram illustrating can be used to form inductor structure according to aspects of the present invention.
Fig. 9 is the top view of multilayer encapsulation, shows the first chamber for 2 phase inductor arrays and is used for 4 phase inductors Second chamber of array.
The first cross section and the second cross section of the construction of the multilayer encapsulation of Figure 10 display diagram 9.
Figure 11 shows that the cross section of encapsulation according to certain aspects of the invention, the cross section are illustrated for generating The process steps on the copper surface with convex block.
Specific embodiment
Fig. 1 is the portion of the system-on-a-chip (SoC) 111 on the multilayer encapsulation substrate 113 shown according to aspects of the present invention Divide cross-sectional view.SoC is coupled to the first side of multilayer encapsulation by dimpling block 115, wherein the second opposite side tool of multilayer encapsulation There is the ball 117 for being coupled to printed circuit board (PCB) (not shown).
SoC is the semiconductor device for generally comprising the various circuits for executing operation, for example, in various embodiments In comprising one or more processor cores and in the situation of SoC 111 include embedded voltage regulator (eVR).Citing comes It says, eVR can be switch mode regulator and switch mode regulator may include switch, and the switch is for replacing the side of inductor Ground is coupled to higher voltage level and lower voltage level, and wherein the other side of inductor provides voltage output node (Vout), The voltage output node will provide the power domain of eVR through regulation power.
Multilayer encapsulation include redistribution layer (RDL), it is described redistribution layer include coupling RDL various pieces and/or The metallization trace and via hole of dimpling block and ball.RDL and via hole are used in encapsulation route signal.Multilayer encapsulation Also comprising the chamber for the inductor structure with the first inductor 119a and the second inductor 119b demonstrated in Figure 1.In In Fig. 1, metalized portion 119c separates the region of the first inductor and the second inductor.
In the embodiment in figure 1, dimpling block includes: Vdd convex block is used to provide SoC's for higher voltage level eVR；And ground connection convex block, it is used to providing lower voltage level into the eVR of SoC.Vdd convex block is coupled to by via hole 121a Vdd ball, and be grounded convex block and ground connection ball is coupled to by via hole 121b.Via hole 121a and 121b be located at inductor 119a, The opposite side of 119b.
Dimpling block also includes: output convex block, is used to provide inductor of the common eVR output from multilayer encapsulation substrate To SoC；And (as demonstrated) two inductors input convex block LX1 and LX2, are used to provide input in multilayer encapsulation substrate Inductor.Multiple inductors are used in the embodiment in figure 1, and wherein the eVR of SoC is multiphase switch mode regulator.Although Two inductors of multiphase switch mode regulator are only shown in Fig. 1, but more than two inductors can be used in many examples.
Fig. 2 sample pattern of the switch of the eVR of display diagram 1 and exemplary single-phase switch adjuster for illustrative purposes Partial circuit diagram.In Fig. 2, single-phase switch adjuster is shown for the sake of apparent, it should be understood that multiphase switching regulator is adjusted Device will include extra switch and inductor.Inductor structure constructed can be matched with the size switched with these.The eVR's of Fig. 2 Layout is coupled in series with higher electricity for the switch mode regulator with high side (HS) switch and downside (LS) switch, the switch It presses between (VDD) and lower voltage (GND).Inductor (showing wherein in order to make it easy to understand, only single inductor) has coupling To one end of the node (LX) between HS switch and LS switch.It obtains from the other end of inductor and is opened by operation HS switch and LS Close the output voltage adjusted.It is shown in some embodiments and in the partial circuit diagram of Fig. 2, by-pass switch coupling inductor Opposite end.HS switch and LS switch are located at VDD coupling 221a and couple between 221b with GND.Such as by that can be seen compared with Fig. 1 Arrive, inductor structure 119a, 119b demonstrated in Figure 1 also are located between VDD and GND connection, and therefore inductor structure with The size of HS and LS construction of switch substantially matches.
The three-dimensional figure of the inductor structure of Fig. 3 offer according to aspects of the present invention and attached cross section.In some embodiments In and in Fig. 3, inductor structure is the inductor 119b for Fig. 1.
Inductor structure includes the planar substrates 311 of metal (being copper in some embodiments).It can be considered as the copper of copper beam Trace 313a, 313b are extended vertically upwards along the opposite edges of substrate.Copper platform 315a extends internally from copper beam 313a level, And similar copper platform 315b extends internally from copper beam 313b level.Copper platform towards and close to but does not reach each other and by substrate Dotted line that the midpoint of 311 width is defined and extend.Other copper beam 317a, 317b respectively from copper platform 315a, 315b to Inward flange extends vertically upwards.Other copper platform 319a, 319b, 323a, 323b and 327a, 327b and other copper to intersperse Beam 321a, 321b and 325a, 325b form inductor with serpentine fashion.In the fig. 3 embodiment, the gap filling between copper has Ferrite Material.
In some embodiments, the electrophoretic deposition of the plating and Ferrite Material that utilize (for example) layers of copper is sealed in multilayer The structure is formed in the chamber at fitted lining bottom.Plating can be used to form thick copper tracing wire to reduce resistance.At the top of copper tracing wire Upper electro-deposition ferrite material layer, this generates self aligned ferrite material layer on the top of copper tracing wire.Repeat the process It include copper tracing wire with Ferrite Material between layers and in some embodiments by the copper tracing wire and ferrite until being formed Until the structure of material composition.For the package cavity of 500um, this can have the copper tracing wire of the 20um thickness that is of five storeys with layers of copper it Between 4 layers of 100um thickness Ferrite Material.In various aspects of the invention, the structure, which is formed, is used for switch mode power tune Save the inductor of device.
Be in terms of structure demonstrated in Figure 3 its allow it is of the invention between phase enhanced mutual inductance it is more Phase embodiment embodiment.Fig. 4 shows the three-dimensional figure of four phase embodiments according to aspects of the present invention.Four phase embodiments can In device for (for example) Fig. 1, wherein there are four the inductors of the two in phase for the cross section displaying tool of Fig. 1.In In Fig. 4, the first inductor 119a corresponds to the inductor 119a of Fig. 1, and the second inductor 119b corresponds to the inductor of Fig. 1 119b.Sightless in Fig. 1 is inductor 419a and 419b, and wherein inductor 419a and 419b is located at inductor 119a And behind 119b.Each of described inductor has the form of the inductor discussed in Fig. 3.
For the inductor of Fig. 4, inductor 119a provides phase 1, and inductor 119b provides phase 2, inductor 419a provides phase 3, and inductor 419b provides phase 4.The cross section of the inductor of Fig. 5 display diagram 4 and magnetic direction.Needle To B-B ', with arrow exhibiting magnetic field direction.For A-A ', magnetic direction be vertical and in the surface in the shadow region of schema and Not in the surface filled with parallel lines of schema.As shown in Figure 5, phase 1 and phase 3 be mutually out of phase 180 degree operation and its It is stacked with allow along B-B ' magnetic field in the same direction.This minimizes the variation for making magnetic field (in its 180 degree out-phase When).Phase 2 and phase 4 are same.Four phase switch mode converters can be obtained from the center for the structure for providing another nucleus Output, this is because the electric current from phase 1 and phase 2 will be from edge to center (phase 3 and phase 4 are same).
OUT node 119c at center can also be single solid metal area, and will have electric current from the top to the bottom simultaneously And this is consistent with the magnetic field line around OUT node 119c.This will be helpful to the inductance for enhancing entire 4 phase embodiment. The light gray line for being connected to the bottom of OUT node and coil structure provides barrier for entire 4 phased array.For having bypass crystal For the DC-DC converter of pipe, implement by-pass switch so that LXn node is connected to gray line.VDD can be connect with GND and be placed in On the outside of gray line, this facilitates the parasitic inductance for reducing VDD and GND.
Fig. 6 is the partial circuit diagram using four phase switch mode regulators of the inductor of Fig. 4.Switch mode regulator includes electricity Sensor 119a, 119b and 419a, 419b.Each of inductor 119a, 119b, 419a, 419b, which are respectively provided with, to be coupled to The input terminal of the output end of Vout 621a and the node being coupled between high-side switch 624a to 624d and 626a to 626d.In In the circuit diagram of Fig. 6, by-pass switch is also used for coupling the end of each inductor, and for example by-pass switch 632a, 632b be respectively The end of coupling inductor 119b.
Fig. 7 shows the cross section of the inductor structure of 8 phase embodiments according to aspects of the present invention.For the electricity of Fig. 7 For sensor structure, the inductor structure of Fig. 4 further enhances the mutual inductance between two 4 phased arrays through mirror image.Therefore, In the relevant situation in the cross section B-B ' of Fig. 7 and the equivalent cross section B-B ' of Fig. 4, magnetic direction is by providing in eight phases The arrow of the part of four four inductors 751,753,755 and 757 indicates that wherein magnetic direction is provided between inductor Mutual inductance.For the sake of complete, Fig. 7 also includes the cross section A-A ' relevant to the cross section Equivalent A-A ' of Fig. 4, display diagram 7 The same structure of inductor 719a, 719b of inductor structure.
The step of Fig. 8 diagram illustrating can be used to form inductor structure according to aspects of the present invention.In multilayer encapsulation 811 Chamber in form inductor structure.Biasing connection 817 can be used to provide biasing for plating.Biasing connection 817 is generally used only for Plating and but small trace.The pattern of copper plating can be thin metal (for example metal 818) layer, deposited and etching with Defining wherein copper will be by the area of galavanic growth.By the copper tracing wire formed (for example, copper tracing wire 813,819 and 821) is electroplated The electrophoretic deposition of Ferrite Material (for example Ferrite Material 815,823) can be subsequently used in.By alternately deposit copper and Ferrite Material repeats the process.Final layers of copper 831 can be polished to generate flat surfaces at the top of structure. Therefore, the uniformity of Ferrite Material and actual (real) thickness are not important for flat final surface, and convex with silicon is used for The encapsulation top surface alignment of block engagement.The deposition of Ferrite Material need not have selectivity and between the deposition of ferrite layer its Its deposition technique can also be electroplated with copper and be used together.
In another embodiment according to aspects of the present invention, package substrate wiring layer can be used to generate inductor knot Structure, and Ferrite Material can be deposited in the chamber of each separating layer.Fig. 9 is the top view of multilayer encapsulation 911, shows and is used for 2 First chamber 915 of phase inductor array and the second chamber 913 for 4 phase inductor arrays.The cross-sectional shape of the chamber is substantially Upper is in rectangle.As demonstrated in Figure 9, the second chamber for 4 phase arrays has the first chamber being substantially equal to double for 2 phase arrays Width.
The first cross section and the second cross section of the construction of the multilayer encapsulation of Figure 10 display diagram 9.First cross section shows more The first layer 1011 and the second layer 1013 of layer encapsulation, wherein the second layer is located on the top of first layer.The second layer includes chamber, described Chamber has the copper tracing wire pattern 1015 being layed on the top of first layer, and wherein ferrite deposition portion 1017 is located at copper tracing wire pattern Top on and filled cavity.
The via hole and the third on the top of the second layer that second cross section shows each side of the chamber along the second layer Layer 1021.For illustrate purposes, the second cross section also shows the typical via hole/metal that usually there will be in multilayer encapsulation A part of wiring 1027.Third layer includes the chamber above the chamber of the second layer, and two of them chamber has basically the same Size.Another copper tracing wire pattern 1023 is located in the ferrite deposition portion of the chamber of the second layer, and another ferrite 1025 has deposited In the chamber of third layer, on the top of another copper tracing wire pattern.By this method, copper tracing wire pattern and ferrite deposition portion can be used To form inductor array.
In various embodiments and as about example described in Fig. 8, (for example) plating can be used metal trace It is placed in ferrite deposition portion, then copper is placed in metal trace.In some embodiments, it can be electroplated applying copper It is preceding on the top of 1 pattern of metal by 2 trace patterns of the metal of different-thickness, wherein in some embodiments metal 1 and gold Belong to 2 and be different metal, (for example) can be selectively etched.This generated on final copper surface desired convex block and Increase the surface area of layer.When skin effect becomes principal element, this can be helpful.
Figure 11 shows the cross section of encapsulation according to certain aspects of the invention, illustrates the copper for generating and having convex block The process steps on surface.The first cross section of Figure 11 shows package substrate 1111, and wherein base copper-layer 1113 is located at the substrate Top on.Ferrite 1114 has been deposited at least some parts of base copper-layer, and the first metal trace patterns 1115 On ferritic top.Second metal trace patterns are located in the selected part of the first metal trace patterns, wherein second Metal trace patterns are effectively formed convex block (for example, convex block 1117) in the first metal trace patterns.In some implementations In example, the second metal trace patterns have the metal different from the first metal trace patterns.In some embodiments, alternative Ground etches different metal, to allow to increase low precision between pattern.In some embodiments, one of described metal is titanium Tungsten (TiW) alloy and the other of described metal is aluminium.
The second cross section of Figure 11 shows (two shown in Figure 11 of copper surface 1121 being located above metal trace patterns There is exceptional space between a part to allow convenient for viewing).Can be positioned evenly over copper surface above metal trace patterns due to The heterogeneity of second metal trace patterns and include convex block.Convex block in copper surface is also used for increasing the surface area on copper surface.
Although discussing the present invention about various embodiments, it is appreciated that the present invention includes the novelty that the present invention supports And non-obvious claim.

Claims (14)

1. a kind of integrated chip package comprising:
The IC chip of flip-chip variety, it is described to open it includes system-on-a-chip SoC and switched mode voltage regulator Pass formula voltage regulator includes at least first be coupled in series between higher voltage level connection and lower voltage level connection Switch and second switch；
MULTILAYER SUBSTRATE has at least one inductor with chamber in the chamber, at least one described inductor, which has, to intersperse Multiple upper trace layers of Ferrite Material, the inductor include first end and second end；And
Multiple dimpling blocks, are connected to the substrate for the IC chip, include by the first switch and the second switch Between node be connected to the inductor the first end dimpling block.
2. integrated chip package according to claim 1, wherein the voltage regulator is multi phase voltage regulator, and institute Stating at least one inductor includes multiple inductors.
3. integrated chip package according to claim 2, wherein the voltage regulator includes multiple switch pair, it is described to open It closes to comprising the first switch and the second switch, and the face of the area of the multiple inductor and the multiple switch pair Product is identical.
4. integrated chip package according to claim 3, wherein the multiple inductor is arranged to inductor array, Described in inductor array at least inductor to being arranged such that the electricity when the inductor is with the operation of 180 degree out-phase What the direction in the magnetic field of sensor pair was in alignment with.
5. integrated chip package according to claim 2, wherein at least some of copper tracing wire copper tracing wire is located at least one Above a metal pattern.
6. integrated chip package according to claim 5, wherein at least one described metal pattern includes convex block.
7. integrated chip package according to claim 6, wherein at least one described metal pattern includes two metal figures Case.
8. integrated chip package according to claim 7, wherein described two metal patterns respectively have different metal.
9. a kind of Flip-Chip Using comprising:
The IC chip of flip-chip variety, it includes system-on-a-chip SoC and multi phase voltage regulator, the multiphase Voltage regulator includes a pair of transistor of series coupled and second pair of transistor of series coupled；And
Multilayer encapsulation substrate, with multiple redistribution layers and the first inductor and the second inductor, first inductance Device and second inductor are formed by multiple plating traces, each of first inductor and second inductor Comprising first end and second end, the multiple plating trace is formed by the intracavitary conductive layer of the multilayer encapsulation substrate, iron oxygen Body material is between at least some of conductive layer conductive layer, and wherein at least one of more than first plating trace warp It configures so that the second end of first inductor to be connected to the first end of second inductor；And
Multiple convex blocks are configured at multiple nodes the IC chip being connected to the multilayer encapsulation substrate, described more A node includes supply node, ground nodes, load output node and inductor node, and the load output node includes described Connection between the second end of first inductor and the first end of second inductor, the inductor node packet Contain: being configured to for the node between described a pair of transistor to be connected to the section of the first end of the first inductor structure Point；And it is configured to for the node between second pair of transistor to be connected to the section of the second end of the second inductor structure Point.
10. Flip-Chip Using according to claim 9, wherein the multi phase voltage regulator further includes series connection coupling The third of conjunction to the 4th pair of transistor of transistor and series coupled, and
Wherein the multilayer encapsulation further has the third inductor and the 4th inductor formed by the multiple plating trace, Each of the third inductor and the 4th inductor include first end and second end, and
Wherein more than described first in plating trace it is described at least one be further configured to the third inductor The second end is connected to the first end of the 4th inductor.
11. Flip-Chip Using according to claim 10, wherein the multi phase voltage regulator is that four phase voltages are adjusted Device.
12. Flip-Chip Using according to claim 11, wherein the first phase of the four phase voltages adjuster and Three phases are configured to execute 180 degree out-phase, and the second phase of the four phase voltages adjuster and the 4th phase are configured to Execute 180 degree out-phase.
13. Flip-Chip Using according to claim 9, wherein the multiple plating trace includes copper.
14. Flip-Chip Using according to claim 9, wherein the size of first inductor be configured to it is described The size of each of a pair of transistor matches, and the size of second inductor is configured to and second pair of crystalline substance The size of each of body pipe matches.
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