CN107402895B - Data transmission method, electronic equipment and server - Google Patents
Data transmission method, electronic equipment and server Download PDFInfo
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- CN107402895B CN107402895B CN201710631658.6A CN201710631658A CN107402895B CN 107402895 B CN107402895 B CN 107402895B CN 201710631658 A CN201710631658 A CN 201710631658A CN 107402895 B CN107402895 B CN 107402895B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The application discloses a data transmission method, electronic equipment and a server, wherein the data transmission method is applied to a data storage device, a PCIE interface is arranged on the data storage device, and the method comprises the following steps: and transmitting target data by utilizing a PCIE interface in the data storage device. According to the data transmission method and device, the PCIE interface is arranged on the data storage device to transmit the target data to other data storage devices, so that the target data are transmitted by the switch port, the transmission bottleneck caused by the data transmission of the switch port is removed, and the data transmission efficiency is improved.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a data transmission method, an electronic device, and a server.
Background
At present, when data transmission is performed between a plurality of data storage devices such as data centers or servers, data transmission is generally performed by using switch ports between data storage areas. Data transmission of the switch port usually becomes a bottleneck of data transmission due to a large data transmission amount, which causes a great reduction in data transmission efficiency.
Disclosure of Invention
In view of the above, an object of the present application is to provide a data transmission method, an electronic device, and a server, so as to solve the technical problem in the prior art that the efficiency of data transmission performed by a data storage device is low.
The application provides a data transmission method, which is applied to a data storage device, wherein a Peripheral Component Interconnect Express (PCIE) interface of a high-speed serial computer is arranged on the data storage device, and the method comprises the following steps:
and transmitting target data by utilizing a PCIE interface in the data storage device.
Preferably, the method for transmitting the target data by using the PCIE interface in the data storage apparatus includes:
storing target data into a first storage space in a first data storage device by using a PCIE interface in the first data storage device;
and transmitting the target data in the first storage space to a second storage space in a second data storage device by using an Ethernet interface so as to provide the second data storage device for reading.
The above method, preferably, further comprises:
transmitting control information on the data storage device using a switch port on the data storage device, the control information being different from the target data.
Preferably, the method for transmitting the target data by using the PCIE interface in the data storage apparatus includes:
storing target data into a first storage space in a first data storage device by using a PCIE interface in the first data storage device;
transmitting the target data in the first storage space to a second storage space in a second data storage device by using an Ethernet interface;
and sending control information to the second data storage device by using a switch port on the first data storage device so as to provide the second data storage device with target data read from the second storage space based on the control information.
Preferably, the method for transmitting the target data by using the PCIE interface in the data storage apparatus includes:
and mapping the target data in the first data storage device to a memory space corresponding to a PCIE interface in the first data storage device so as to provide the target data for a second data storage device to read by utilizing the PCIE interface.
The above method, preferably, further comprises:
transmitting a notification message using an Ethernet interface in the data storage device.
The present application further provides an electronic device, including: the data storage device and the PCIE interface arranged on the data storage device also include:
and the processor is used for controlling the data storage device to transmit target data by utilizing the PCIE interface.
The application also provides a server, a PCIE interface is arranged on the server, and the server transmits target data by utilizing the PCIE interface.
According to the scheme, the data transmission method, the electronic device and the server provided by the application transmit the target data to other data storage devices by arranging the PCIE interface on the data storage device, so that the target data is transmitted by the switch port, a transmission bottleneck caused by the data transmission of the switch port is removed, and the data transmission efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
Fig. 1 and fig. 2 are diagrams illustrating an application example of a data transmission method according to an embodiment of the present application;
fig. 3 is a flowchart of a data transmission method according to an embodiment of the present application;
fig. 4 to fig. 7 are diagrams of other application examples of a data transmission method according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;
fig. 9 is a diagram illustrating an application example of an electronic device according to an embodiment of the present application;
FIG. 10 is a schematic diagram of a server according to the present application;
fig. 11, 12, and 13 are diagrams of application examples of a server provided in the present application, respectively.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the data transmission method provided in the embodiment of the application, the PCIE interface is arranged on the data storage device, as shown in fig. 1, the data storage device transmits the target data through the PCIE interface, so that the switch port on the data storage device is avoided from transmitting the target data, a transmission bottleneck is not caused, and thus, the data transmission efficiency is improved.
As shown in fig. 2, target data is transmitted between the data storage devices through respective PCIE interfaces. For example, the first data storage device uses its PCIE interface to transmit the target data to be transmitted to the second data storage device, and the second data storage device uses its PCIE interface to receive the target data transmitted by the first data storage device.
The target data refers to data of a data plane that the data storage device needs to transmit, such as data of a GB level, and is different from data such as control information on a control plane.
It should be noted that the first data storage device and the second data storage device in fig. 2 refer to devices capable of storing data, such as a magnetic disk, a hard disk, or a server.
In one implementation, when the data storage device transmits the target data using its PCIE interface, the data storage device may be implemented by the following steps, as shown in fig. 3:
step 301: and transmitting the target data to a first storage space in the first data storage device by utilizing a PCIE interface in the first data storage device.
In which a storage space is provided in the data storage device, for example, as shown in fig. 4, a series of DIMM slots may be provided, and memory banks are mounted on the DIMM slots to form a memory space for storing target data.
Step 302: and transmitting the target data in the first storage space to a second storage space in a second data storage device by using the Ethernet interface so as to provide the second data storage device for reading.
In this embodiment, the target data is cached by using the storage space provided in the data storage device, instead of directly transmitting the target data by using the switch port, so as to improve the transmission performance.
As shown in fig. 5, the first data storage device stores the target data in the first storage space of the first data storage device by using its PCIE interface, then transfers the target data in the first storage space to the second storage space of the second data storage device through the ethernet interface between the first data storage device and the second data storage device, and then the second data storage device can read the target data from the second storage space by using the PCIE interface of the second data storage device, thereby completing the transfer of the target data from the first data storage device to the second data storage device.
In one implementation, the data storage device is implemented using its PCIE interface when transferring the target data, and in addition, the data storage device transfers the control information on the data storage device using its switch port. And the control information is distinguished from the target data. As shown in fig. 6, a PCIE interface and a switch port are disposed on the data storage device, in this embodiment, the data storage device transmits target data by using the PCIE interface thereof, transmits control information by using the switch port, and separates the transmission of the control information and the transmission of the target data, so that the amount of the control information transmitted by the switch port is not high, which does not cause a transmission bottleneck caused by the switch port and does not affect the transmission of the target data.
The control information may include information such as a storage location of the target data in the storage space, so that, as shown in fig. 5, after the first data storage device transmits the control information to the second data storage device through the switch port, the second data storage device can read the target data from the second storage space based on the control information, and complete the transfer of the target data from the first data storage device to the second data storage device.
In one implementation, the data storage device may map the target data into a memory space corresponding to the PCIE interface, for example, an Address Translation Unit (ATU) is used to map the target data into a memory space corresponding to the PCIE interface, so as to provide the target data to other data storage devices for reading by using their PCIE interfaces.
In one implementation, the data storage device may transmit a notification message to the other data storage device using the ethernet interface to notify the other data storage device to read the target data from the memory space.
As shown in fig. 7, a memory space is corresponding to a PCIE interface of the first data storage device, the first storage device maps target data to be transmitted to the memory space corresponding to the PCIE interface through the ATU, and then notifies the second data storage device to read the target data from the memory space by using its PCIE interface.
Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the electronic device may include a data storage device 801, a PCIE interface 802 disposed on the data storage device, and a processor 803, where the processor 803 controls the data storage device 801 to transmit target data through the PCIE interface 802. The specific implementation manner of the processor 803 in the electronic device controlling the data storage device 801 to implement data transmission may refer to the schemes described in fig. 1 to fig. 7, and will not be described in detail here.
In one implementation, the electronic device may be a machine, such as a server, having a data storage device, such as a memory or a hard disk, and a network interface.
Specifically, each electronic device participating in data transmission is provided with a PCIE interface, each electronic device is connected to another electronic device through a PCIE bus, and each electronic device stores memory data in its memory. When the first electronic device needs to obtain the memory data in the second electronic device, the second electronic device may map the memory data needed by the first electronic device to the memory space of the PCIE interface of the second electronic device in a manner of configuring the ATU in advance, and then the first electronic device may read the memory data in the memory space corresponding to the PCIE interface of the second electronic device through the PCIE interface.
Taking an electronic device as a System on Chip (SoC) as an example, each SoC has a Memory DIMM storing Memory data, a processor such as a Central Processing Unit (CPU), a Memory controller (Memory controller) connected to the CPU, and a PCIE interface, where the PCIE interface includes an input/output Space (IO Space) and a Memory Space (Memory Space).
As shown in fig. 9, the SoC0 may inform the SoC1 via Ethernet, the SoC 1: the SoC0 is about to access the memory data of the SoC 1;
the SoC1 maps the Memory data required by the SoC0 from the DIMM to the Memory Space of the SoC1 by the Memory controller through the ATU configuration method in advance, and then notifies the SoC0 through the Ethernet method: SoC1 is ready to receive memory access by SoC 0;
after the SoC0 reads the Memory data in the Memory Space of the PCIE interface of the SoC1 through the PCIE interface of the SoC0, the Memory access is completed, and at this time, the SoC0 may notify the SoC1 of the completion of the access through Ethernet;
after receiving the information of completing the access of SoC0, SoC1 can close the memory image by configuring or compiling ATU.
That is to say, the SoC0 can notify the SoC1 of which Memory address sections the data need to access through Ethernet, and the SoC1 can map the data of the Memory address sections the SoC0 needs to access into the Memory Space of the PCIE interface of the SoC1 by configuring the ATU, thereby completing the access of the Memory data without copying the Memory data for many times, so that a switch port between the SoC0 and the SoC1 is not required to transmit the same data for many times or transmit multiple copies of the same data at the same time, thereby reducing the overhead of a network communication Protocol (Transmission Control Protocol/Internet Protocol, TCP/IP) Protocol, and significantly improving the efficiency of data Transmission and Memory access.
Fig. 10 is a schematic structural diagram of a server according to the present application, where a PCIE interface 1002 is disposed on the server 1001, and the server 1001 transmits target data by using the PCIE interface 1002. The server may be a data storage device in the distributed storage system, such as a cabinet storing a large amount of data.
Taking a server as an example, a cabinet includes a computing node and a storage node, in this embodiment, each cabinet is provided with a Programmable Unit and a PCIE Switch, all nodes on the cabinet are connected to the PCIE Switch through PCIE interfaces of a cabinet backplane by using a PCIE bus, and thus all the nodes can access hardware resources of pcieses of other nodes through the PCIE interfaces and the PCIE bus.
Where the Programmable Unit is a Programmable controller, it will connect a memory controller and a series of DIMM slots through PCIE bus, as shown in fig. 11 and 12, it can install memory bank and then connect it to PCIE Switch. Thus, for other nodes in the enclosure, it appears that this Unit is equivalent to a shared memory pool, and can be provided for each node to access through the PCIE Switch. Meanwhile, the Unit provides a 10G/40G/100G Ethernet interface for interconnection between racks. Because the length of the PCIE bus is limited, the connection of the PCIE bus is not suitable between the racks, and therefore the connection is carried out by using the Ethernet. Because only 1-to-1 Unit connection is needed, the cost is not high even if 40G Ethernet interface is used.
In the prior art, the control plane and the data plane are merged together, and both need to be transmitted through a Switch (Top on Rack Switch, TOR Switch) on the cabinet, and in this embodiment, the data plane and the control plane are separated: the TOR only needs to transmit single control information, and the information quantity is not large, so that only a kilomega switch with lower cost is used, and a switch with more than ten thousand million is not needed; the ethernet port in the Programmable Unit is used for data plane transmission between cabinets, and the Memory in the Unit is used for data plane transmission between nodes in the cabinets, so that the copy of data versions is reduced to the maximum extent, and meanwhile, the transmission of the Memory replaces the ethernet transmission, so that the performance is improved (the Memory access rate is 100 times of that of a gigabit network).
Taking the nodeA5 in the cabinet a to transmit data to other cabinets B, C, D as an example, the embodiment of the present application is explained, as shown in fig. 13:
when a5 in cabinet a sends a large amount of data to a machine in cabinet B, C, D, it first sends the data to a Programmable Unit in BCD cabinet through ethernet interface of the Programmable Unit, and then a5 sends a push message, i.e., a control message, to all nodes in B, C, D through TOR switches, where the nodes locate the data in the Memory Pool of the Programmable Unit in the cabinet and read and retrieve the data locally through PCIE bus. In this way, only 3 copies of data between cabinets are needed, and the nodes in the cabinets access the data through the related scheme described in fig. 8, so that the access rate is greatly increased, the bottleneck of the TOR switch disappears, the pressure of the Programmable Unit increases linearly according to the number of copied cabinets, but the magnitude is much smaller than the number of nodes. In the data transmission process, the data transmission pressure of A5 is relieved, TOR switches of all cabinets are no longer bottlenecks, and a memory scheme is used inside the cabinets to replace a TCP/IP protocol stack, so that the access efficiency is improved. Furthermore, the cabinets can be interconnected by using a high-speed Ethernet without worrying about the sharp increase of the cost.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above detailed description of the data transmission method, the electronic device and the server provided by the present invention enables those skilled in the art to implement or use the present invention through the above description of the disclosed embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A data transmission method is applied to a data storage device of a system-on-chip SOC, wherein a PCIE interface of a high-speed serial computer expansion bus standard is arranged on the data storage device, and the method comprises the following steps:
transmitting target data by using a PCIE interface in the data storage device; the target data refers to data of a data plane which needs to be transmitted by the data storage device; the data storage device transmits a notification message to other data storage devices by using an Ethernet interface so as to notify the other data storage devices to read target data from the memory space;
transmitting control information on the data storage device using a switch port on the data storage device, the control information being different from the target data.
2. The method of claim 1, wherein transferring target data using a PCIE interface in the data storage device comprises:
storing target data into a first storage space in a first data storage device by using a PCIE interface in the first data storage device;
and transmitting the target data in the first storage space to a second storage space in a second data storage device by using an Ethernet interface so as to provide the second data storage device for reading.
3. The method of claim 1, wherein transferring target data using a PCIE interface in the data storage device comprises:
storing target data into a first storage space in a first data storage device by using a PCIE interface in the first data storage device;
transmitting the target data in the first storage space to a second storage space in a second data storage device by using an Ethernet interface;
and sending control information to the second data storage device by using a switch port on the first data storage device so as to provide the second data storage device with target data read from the second storage space based on the control information.
4. The method of claim 1, wherein transferring target data using a PCIE interface in the data storage device comprises:
and mapping the target data in the first data storage device to a memory space corresponding to a PCIE interface in the first data storage device so as to provide the target data for a second data storage device to read by utilizing the PCIE interface.
5. The method of claim 4, further comprising:
transmitting a notification message using an Ethernet interface in the data storage device.
6. An electronic device, comprising: the data storage device of system level chip SOC and the PCIE interface arranged on the data storage device also include:
the processor is used for controlling the data storage device to transmit target data by utilizing a PCIE interface; the target data refers to data of a data plane which needs to be transmitted by the data storage device; the data storage device transmits a notification message to other data storage devices by using an Ethernet interface so as to notify the other data storage devices to read target data from the memory space; and the controller is further configured to transmit control information on the data storage device using a switch port on the data storage device, the control information being different from the target data.
7. A server is provided with a PCIE interface, and the server transmits target data by utilizing the PCIE interface; the target data refers to data of a data plane which needs to be transmitted by a data storage device of the SOC; the data storage device transmits a notification message to other data storage devices by using an Ethernet interface so as to notify the other data storage devices to read target data from the memory space; and the server transmits control information on the data storage device by using a switch port on the data storage device, wherein the control information is different from the target data.
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| US10042794B2 (en) * | 2015-06-12 | 2018-08-07 | Apple Inc. | Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link |
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| CN103368968A (en) * | 2013-07-22 | 2013-10-23 | 厦门市美亚柏科信息股份有限公司 | Data transmission method and system |
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