CN107393817A - A kind of chip structure and its manufacture method - Google Patents

A kind of chip structure and its manufacture method Download PDF

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Publication number
CN107393817A
CN107393817A CN201710610960.3A CN201710610960A CN107393817A CN 107393817 A CN107393817 A CN 107393817A CN 201710610960 A CN201710610960 A CN 201710610960A CN 107393817 A CN107393817 A CN 107393817A
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CN
China
Prior art keywords
chip
wafer
cut
manufacture method
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710610960.3A
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Chinese (zh)
Inventor
王杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201710610960.3A priority Critical patent/CN107393817A/en
Publication of CN107393817A publication Critical patent/CN107393817A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Dicing (AREA)

Abstract

The present invention relates to a kind of chip structure and its manufacture method, the described method comprises the following steps：Step 1: preparing a wafer, one layer of blue film is pasted in wafer rear, wafer frontside pastes one layer of dry film and exposes wafer Cutting Road by exposure imaging；Step 2: wafer frontside is cut, wafer is cut into single chip along Cutting Road, the chip of single is cut into and remains adhered on blue film；Step 3: chip is etched, chip sides are etched into arcuate furrow；Step 4: the face exposure of whole face chip is developed, the dry film of chip front side is removed；Step 5: the chip shipment of full wafer well cutting, the normal flow operation of encapsulation factory.A kind of chip structure of the present invention and its manufacture method, it may ensure that on the basis of elargol coverage rate is met, elargol does not spill over chip surface, ensures the reliability being normally carried out with product of follow-up bonding wire.

Description

A kind of chip structure and its manufacture method
Technical field
The present invention relates to a kind of chip structure and its manufacture method, belong to technical field of semiconductor encapsulation.
Background technology
With the continuous diminution of product size, encapsulate the chip thickness used and be also constantly thinned, give load operation Difficulty is brought, can not ensure that elargol does not spill over chip surface in the case where meeting elargol coverage rate.If meet 100% Elargol coverage rate, easily cause elargol and spill over chip surface, influence follow-up bonding wire craft；Or the usage amount of reduction elargol is come Ensure that elargol does not spill over chip surface, may result in elargol coverage rate deficiency, cause the reliability failures of product.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of chip structure and its manufacturer for above-mentioned prior art Method, it may ensure that on the basis of elargol coverage rate is met, avoid elargol from spilling over chip surface, ensure the normal of follow-up bonding wire Carry out the reliability with product.
Technical scheme is used by the present invention solves the above problems：A kind of chip structure, it includes chip body, described Chip body side X, Y-direction are provided with the groove of arc.
A kind of manufacture method of chip structure, the described method comprises the following steps：
Step 1: preparing a wafer, one layer of blue film is pasted in wafer rear, wafer frontside pastes one layer of dry film and shown by exposing Shadow exposes wafer Cutting Road；
Step 2: wafer frontside is cut, wafer is cut into single chip along Cutting Road, the chip of single is cut into and still adheres to On blue film；
Step 3: chip is etched, chip sides X, Y-direction are etched into arcuate furrow；
Step 4: the face exposure of whole face chip is developed, the dry film of chip front side is removed；
Step 5: the chip shipment of full wafer well cutting, the normal flow operation of encapsulation factory.
The width of cutter is less than the width of Cutting Road in step 2.
The mode etched in step 4 is wet etching, plasma etching or gas etch.
Compared with prior art, the advantage of the invention is that：
1st, ultra-thin chip groove at side surface, the elargol of chip bottom spilling can be accommodated when load, prevents elargol from directly overflowing To chip surface；
2nd, chip sides can accommodate elargol, both can guarantee that the coverage rate of chip bottom elargol, can increase again chip sides with The combination of elargol, increase the binding ability of chip and substrate, improve the reliability of product.
Brief description of the drawings
Fig. 1 is a kind of schematic diagram of chip structure of the present invention.
Fig. 2 ~ Fig. 5 is a kind of schematic flow sheet of the manufacture method each operation of chip structure of the present invention.
Wherein：
Chip body 1
Groove 2.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing embodiment.
Referring to Fig. 1, a kind of chip structure in the present embodiment, it includes chip body 1, described chip body 1 side X, Y Direction is provided with the groove 2 of arc；
Its manufacture method is as follows：
Step 1: referring to Fig. 2, prepare a wafer, paste the higher blue film of cohesive in wafer rear, wafer frontside pastes one Layer dry film, is exposed wafer Cutting Road by exposure imaging；
Step 2: referring to Fig. 3, wafer frontside cutting, wafer is cut into single chip along Cutting Road, cuts into the chip of single Remain adhered on blue film.The width of cutter is less than the width of Cutting Road, prevents from etching into chip edge when etching；
Step 3: referring to Fig. 4, chip is etched, chip sides X, Y-direction are etched into arc by adjusting etching parameter Groove, the mode of etching can be wet etching, plasma etching, gas etch etc.；
Step 4: referring to Fig. 5, the face exposure of whole face chip is developed, and removes the dry film of chip front side；
Step 5: the chip shipment of full wafer well cutting, the normal flow operation of encapsulation factory.
In addition to the implementation, it is all to use equivalent transformation or equivalent replacement present invention additionally comprises there is other embodiment The technical scheme that mode is formed, it all should fall within the scope of the hereto appended claims.

Claims (5)

  1. A kind of 1. chip structure, it is characterised in that：It includes chip body（1）, the chip body（1）Side X, Y-direction are set It is equipped with groove（2）.
  2. A kind of 2. chip structure according to claim 1, it is characterised in that：Groove（2）It is arc.
  3. 3. a kind of manufacture method of chip structure, it is characterised in that the described method comprises the following steps：
    Step 1: preparing a wafer, one layer of blue film is pasted in wafer rear, wafer frontside pastes one layer of dry film and shown by exposing Shadow exposes wafer Cutting Road；
    Step 2: wafer frontside is cut, wafer is cut into single chip along Cutting Road, the chip of single is cut into and still adheres to On blue film；
    Step 3: chip is etched, chip sides X, Y-direction are etched into arcuate furrow；
    Step 4: the face exposure of whole face chip is developed, the dry film of chip front side is removed；
    Step 5: the chip shipment of full wafer well cutting, the normal flow operation of encapsulation factory.
  4. A kind of 4. manufacture method of chip structure according to claim 3, it is characterised in that：The width of cutter in step 2 Width of the degree less than Cutting Road.
  5. A kind of 5. manufacture method of chip structure according to claim 3, it is characterised in that：The mode etched in step 4 It is wet etching, plasma etching or gas etch.
CN201710610960.3A 2017-07-25 2017-07-25 A kind of chip structure and its manufacture method Pending CN107393817A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710610960.3A CN107393817A (en) 2017-07-25 2017-07-25 A kind of chip structure and its manufacture method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710610960.3A CN107393817A (en) 2017-07-25 2017-07-25 A kind of chip structure and its manufacture method

Publications (1)

Publication Number Publication Date
CN107393817A true CN107393817A (en) 2017-11-24

Family

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Application Number Title Priority Date Filing Date
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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109081303A (en) * 2018-08-27 2018-12-25 无锡芯坤电子科技有限公司 A kind of chip double-side cutting technique
CN113675094A (en) * 2021-08-04 2021-11-19 泰兴市龙腾电子有限公司 Inner lead layered manufacturing method of semiconductor frame

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW444415B (en) * 1999-02-02 2001-07-01 Highlight Optoelectronics Inc Light emitting diode die and the manufacturing method thereof
DE102004028680A1 (en) * 2004-06-14 2005-12-29 Asyntis Gmbh Partitioning wafer chips includes etching the walls of a mechanically formed trench in the top wafer surface to extend the trench at least to the lower surface of the wafer
CN101075591A (en) * 2007-05-22 2007-11-21 日月光半导体制造股份有限公司 Chip packing structure, chip structure and method for forming chip
US20130234193A1 (en) * 2012-03-08 2013-09-12 Micron Technology, Inc. Etched trenches in bond materials for die singulation, and associated systems and methods
KR20150005256A (en) * 2013-07-05 2015-01-14 이수진 Lead frame using separated mold, method of manufacturing the same and semiconductor package, method of manufacturing the same
CN105340064A (en) * 2013-07-01 2016-02-17 富士施乐株式会社 Semiconductor piece manufacturing method, circuit board including semiconductor piece, and image forming apparatus

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW444415B (en) * 1999-02-02 2001-07-01 Highlight Optoelectronics Inc Light emitting diode die and the manufacturing method thereof
DE102004028680A1 (en) * 2004-06-14 2005-12-29 Asyntis Gmbh Partitioning wafer chips includes etching the walls of a mechanically formed trench in the top wafer surface to extend the trench at least to the lower surface of the wafer
CN101075591A (en) * 2007-05-22 2007-11-21 日月光半导体制造股份有限公司 Chip packing structure, chip structure and method for forming chip
US20130234193A1 (en) * 2012-03-08 2013-09-12 Micron Technology, Inc. Etched trenches in bond materials for die singulation, and associated systems and methods
CN105340064A (en) * 2013-07-01 2016-02-17 富士施乐株式会社 Semiconductor piece manufacturing method, circuit board including semiconductor piece, and image forming apparatus
KR20150005256A (en) * 2013-07-05 2015-01-14 이수진 Lead frame using separated mold, method of manufacturing the same and semiconductor package, method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109081303A (en) * 2018-08-27 2018-12-25 无锡芯坤电子科技有限公司 A kind of chip double-side cutting technique
CN113675094A (en) * 2021-08-04 2021-11-19 泰兴市龙腾电子有限公司 Inner lead layered manufacturing method of semiconductor frame

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Application publication date: 20171124