CN107369645B - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN107369645B CN107369645B CN201610319283.5A CN201610319283A CN107369645B CN 107369645 B CN107369645 B CN 107369645B CN 201610319283 A CN201610319283 A CN 201610319283A CN 107369645 B CN107369645 B CN 107369645B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
Abstract
The invention discloses a method for forming a semiconductor structure, which comprises the steps of forming a protective layer in a first opening, wherein the protective layer exposes a conductive structure at the joint of the side wall of the first opening and the surface of a substrate; then oxidizing part of the conductive structure to oxidize the conductive structure at the connection position of the side wall of the first opening and the surface of the substrate; and removing the oxidized conductive structure to remove the raised structure on the conductive structure. That is to say, according to the technical scheme of the invention, the oxidized conductive structure is removed, and the protruding structure on the conductive structure and at the connection position of the side wall of the first opening and the surface of the substrate is removed, so that the size of the second opening can be increased, the formation of a cavity when the second opening is filled can be reduced, the filling effect of the conductive material can be effectively improved, the electrical connection performance of the formed interconnection structure is improved, and the reliability of the formed semiconductor structure is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for forming a semiconductor structure.
Background
With the rapid development of Ultra Large Scale integrated circuits (Ultra Large Scale Integration), the integrated circuit fabrication process becomes more and more complex and sophisticated. In order to improve the integration and reduce the manufacturing cost, the number of semiconductor devices per unit area of a chip is increasing, and the planar wiring has been difficult to meet the requirement of high-density distribution of the semiconductor devices.
In order to meet the requirement of interconnection of devices with reduced critical dimensions, in the prior art, the integration level of the devices is further improved by using the vertical space of a chip through a multilayer wiring technology. In a semiconductor structure adopting a multilayer wiring technology, electrical connection between different layers of wiring is realized through an interconnection structure.
The interconnect structure in the prior art is mainly formed by filling a conductive material into the opening. However, as the size of the semiconductor structure decreases, the difficulty of filling the opening with the conductive material increases, which causes a void in the formed interconnection structure, thereby affecting the yield and reliability of the formed semiconductor structure.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to improve the yield and the reliability of a formed semiconductor device.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
providing a substrate; forming a first opening in the substrate; forming a conductive structure on the sidewall of the first opening and the surface of the substrate; forming a protective layer in the first opening, wherein the protective layer exposes the conductive structure at the connection position of the side wall of the first opening and the surface of the substrate; oxidizing a portion of the thickness of the conductive structure; removing the protective layer and the oxidized conductive structure to form a second opening; and filling a conductive material into the second opening to form an interconnection structure.
Optionally, the material of the protective layer includes graphene oxide.
Optionally, the step of forming the protective layer includes: filling a precursor into the first opening, wherein the precursor contains graphene oxide; curing the precursor to form a protective material layer; and removing part of the protective material layer to expose part of the conductive structure at the joint of the side wall of the first opening and the surface of the substrate to form a protective layer.
Optionally, in the step of removing the protective material layer with a partial thickness, removing the partial thickness of the protective material layer by using oxygen plasma; and oxidizing the conductive structure with partial thickness in the process of removing the partial thickness of the protective material layer by adopting oxygen plasma.
Optionally, in the step of filling the precursor, the precursor in a fluid state is filled into the first opening.
Optionally, the step of performing a curing process on the precursor includes: and carrying out curing treatment on the precursor by means of thermal curing or radiation curing.
Optionally, in the step of performing a curing treatment on the precursor by means of thermal curing, the temperature of the thermal curing is less than 280 ℃.
Optionally, in the step of curing the precursor by radiation curing, UV radiation is used to cure the precursor.
Optionally, the step of removing the protective layer includes: and removing the protective layer by a water washing mode.
Optionally, after forming the second opening and before filling the conductive material, the method further includes: and carrying out reduction treatment on the semiconductor structure.
Optionally, in the step of reducing, the semiconductor structure is reduced by hydrogen or hydrazine.
Optionally, the step of removing the oxidized conductive structure comprises: and removing the oxidized part of the conductive structure by means of acid washing.
Optionally, the step of removing the partial thickness of the conductive structure by acid washing includes: and removing the oxidized part of the conductive structure by a hydrochloric acid cleaning mode.
Optionally, in the step of removing the oxidized part of the conductive structure by acid washing, nitrogen gas is added during the acid washing.
Optionally, in the step of forming the conductive structure, the conductive structure includes a seed layer, or the conductive structure includes a seed layer and a partial plating layer located on a surface of the seed layer.
Optionally, in the step of forming the conductive structure including the seed layer, the seed layer is formed by physical vapor deposition.
Optionally, in the step of filling the conductive material, the conductive material is filled by electroplating to form the interconnect structure.
Optionally, after forming the first opening and before forming the protective layer, the method further includes: and forming an adhesion layer or a barrier layer on the side wall and the bottom of the first opening.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the invention, the protective layer is formed in the first opening, and the protective layer exposes the conductive structure at the connecting part of the side wall of the first opening and the surface of the substrate; then oxidizing the conductive structure at the connection position of the side wall of the first opening and the surface of the substrate by oxidizing part of the conductive structure; and removing the oxidized conductive structure to remove the raised structure on the conductive structure. That is to say, in the technical scheme of the invention, the oxidized conductive structure is removed, and the protruding structure on the conductive structure and at the connection position of the side wall of the first opening and the surface of the substrate is removed, so that the size of the second opening can be increased, the formation of a cavity when the second opening is filled can be reduced, the filling effect of a conductive material can be effectively improved, the electrical connection performance of the formed interconnection structure is improved, and the reliability of the formed semiconductor structure is improved.
In an alternative aspect of the present invention, the material of the protective layer is graphene oxide, and may be formed by curing a precursor containing graphene oxide. The precursor is in a fluid state, so that the protective layer can have a good filling effect on the first opening, and the protective effect of the protective layer on the first opening can be improved. And the graphene oxide has good water solubility, so that the protective layer can be removed through water washing, and the residue of the protective layer is reduced. In addition, the graphene oxide can be reduced into conductive graphene, so that the influence of the protective layer on the conductivity of the formed interconnection structure is reduced.
Drawings
FIGS. 1-3 are cross-sectional views of intermediate structures in the formation of a semiconductor structure;
fig. 4 to 10 are schematic cross-sectional views of intermediate structures at various steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the semiconductor structure in the prior art has the problems of poor yield and reliability. The reasons for the problems of good product rate and reliability are analyzed by combining the forming process of the semiconductor structure in the prior art:
referring to fig. 1 and 2, there is shown a schematic cross-sectional view of an intermediate structure during the formation of a semiconductor structure.
As shown in fig. 1, a substrate 10 is first provided, the substrate 10 having an opening 11 therein; then, a conductive structure 12 is formed on the sidewall of the opening 11. Finally, as shown in fig. 2, the opening 11 is filled with a conductive material to form an interconnect structure 13.
In the prior art, an electroplating process is usually adopted to fill the opening 11 with a conductive material. It is therefore necessary to form conductive structures 12 on the sidewalls and bottom of the openings 11 before filling the conductive material to form the interconnect structures 13. Physical vapor deposition is often used to form the conductive structures 12.
As shown in fig. 3, since the conductive structure 12a also covers the surface of the substrate 10a, and the step coverage of the pvd process is poor, after the conductive structure 12a is formed, a protruding structure 14a is formed on the conductive structure 12a at the connection between the sidewall of the opening and the surface of the substrate 10a, and a necking phenomenon occurs.
Due to the formation of the protruding structure 14a, when the opening 11a is filled with a conductive material to form the interconnect structure 13a, a void 15 is easily formed in the interconnect structure 13 a. The formation of the voids 15 may cause the interconnect structure to fail, thereby affecting the yield of the semiconductor structure formed; the interconnect structure may also fail during use, thereby affecting the reliability of the resulting semiconductor structure.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
providing a substrate; forming a first opening in the substrate; forming a conductive structure covering the side wall of the first opening and the surface of the substrate; forming a protective layer in the first opening, wherein the protective layer exposes the conductive structure at the connection position of the side wall of the first opening and the surface of the substrate; oxidizing a portion of the thickness of the conductive structure; removing the protective layer and the oxidized conductive structure to form a second opening; and filling a conductive material into the second opening to form an interconnection structure.
According to the invention, the protective layer is formed in the first opening, and the protective layer exposes the conductive structure at the connecting part of the side wall of the first opening and the surface of the substrate; then oxidizing the conductive structure at the connection position of the side wall of the first opening and the surface of the substrate by oxidizing part of the conductive structure; and removing the oxidized conductive structure to remove the raised structure on the conductive structure. That is to say, in the technical scheme of the invention, the oxidized conductive structure is removed, and the protruding structure on the conductive structure and at the connection position of the side wall of the first opening and the surface of the substrate is removed, so that the size of the second opening can be increased, the formation of a cavity when the second opening is filled can be reduced, the filling effect of a conductive material can be effectively improved, the electrical connection performance of the formed interconnection structure is improved, and the reliability of the formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 4 to 10, cross-sectional views of intermediate structures of various steps of a method for forming a semiconductor structure according to an embodiment of the present invention are shown.
Referring to fig. 4, a substrate 100 is provided.
Specifically, the substrate 100 is used to provide an operation platform for a subsequent process. In this embodiment, the substrate 100 is a substrate with a stacked structure. Specifically, the substrate 100 includes a silicon carbonitride substrate, and a first dielectric layer, a second dielectric layer, a first oxide layer, a titanium nitride layer, and a second oxide layer sequentially disposed on the silicon carbonitride substrate. The material of the first dielectric layer comprises a low-K dielectric material (the dielectric constant is greater than or equal to 2.5 and less than 3.9) or an ultra-low-K dielectric material (the dielectric constant is less than 2.5); the second dielectric layer is made of a low-K dielectric material.
In other embodiments of the present invention, the material of the substrate may also be selected from single crystal silicon, polycrystalline silicon or amorphous silicon; the substrate may also be selected from compounds such as silicon, germanium, gallium arsenide, or silicon germanium; the substrate may also be other semiconductor materials. In addition, the substrate can also be selected from an epitaxial layer or a silicon material on the epitaxial layer.
With continued reference to fig. 4, a first opening 110 is formed in the substrate 100.
The first opening 110 is used to form an interconnect structure. Specifically, in the present embodiment, the first opening 110 includes a trench 110tr for forming an interconnection line and a contact hole 110ct for forming a plug. It should be noted that, in this embodiment, the way that the first opening 110 includes the trench 110tr and the contact hole 110ct is only an example. In other embodiments of the present invention, the first opening may be any one or both of a trench and a contact hole.
Specifically, the step of forming the first opening 110 in the substrate 100 includes: forming a patterned layer on the surface of the substrate 100, wherein the patterned layer is used for defining the size and the position of the first opening 110; and etching the substrate 100 by using the patterned layer as a mask, and forming the first opening 110 in the substrate 100.
The patterned layer may be a patterned photoresist layer formed using a coating process and a photolithography process. In addition, in order to reduce the size of the metal gate structure formed subsequently and the size of the semiconductor device formed, the patterning layer may also be formed by using a multiple patterning mask process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned triple patterning (Self-aligned triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
In this embodiment, after forming the first opening 110, the forming method further includes: a functional structure 101 is formed on the sidewall and bottom of the first opening 110.
Specifically, the functional structure 101 includes a barrier layer and an adhesion layer, and the barrier layer and the adhesion layer are sequentially located on the surface of the sidewall of the first opening 110.
The barrier layer is used to prevent atoms of conductive material subsequently forming the interconnect structure from diffusing into the substrate 100 to cause electrical problems such as shorts or bridges. Specifically, in this embodiment, the material of the barrier layer includes tantalum nitride. The adhesion layer is used to improve the interfacial bonding property of the formed interconnect structure to the sidewall of the first opening 110. Specifically, the material of the adhesion layer comprises tantalum. In addition, the barrier layer and the adhesion layer may be sequentially formed on the surface of the sidewall of the first opening 110 by chemical vapor deposition to form the functional structure 101.
It should be noted that tantalum nitride is better in mechanical properties, but has a relatively large resistance; tantalum has a relatively low resistance, but does not have as good mechanical properties as tantalum nitride. And the interfacial bonding properties of tantalum and conductive materials are better than tantalum nitride. The functional structure 101 composed of the barrier layer and the adhesion layer can effectively improve the reliability of the formed interconnect structure.
Referring to fig. 5, a conductive structure 120 is formed on the sidewall of the first opening 110 and the surface of the substrate 100.
The conductive structure 120 is used for conducting current in the process of forming an interconnect structure by filling a conductive material later. In this embodiment, the conductive material is filled by Electro Chemical Plating (ECP) in a subsequent step. During electroplating, it is necessary to achieve current conduction at the position filled with the conductive material, and therefore, the conductive structure 120 needs to be formed on the sidewall of the first opening 110. Since the material of the subsequently formed interconnect structure is copper, the material of the conductive structure 120 includes copper. In this embodiment, the conductive structure 120 is a copper seed layer.
It should be noted that the conductive structure 120 is a copper seed layer, which is only an example. In other embodiments of the present invention, the conductive structure may further include a seed layer and a partial electroplating layer on the surface of the seed layer.
Specifically, the seed layer in the conductive structure 120 may be formed by physical vapor deposition. Also, during the process of forming the conductive structure 120, the conductive structure 120 also covers the surface of the substrate 100. Due to the poor step coverage of the pvd process, the conductive structure 120 located at the connection between the surface of the substrate 100 and the sidewall of the first opening 110 forms a protrusion 121. The formation of the protrusion 121 may affect the filling of the conductive material during the formation of the interconnect structure, and may easily form a void in the interconnect structure, thereby affecting the reliability of the formed interconnect structure, and affecting the yield and reliability of the formed semiconductor structure.
Referring to fig. 6 and 7, a protection layer 130 is formed in the first opening 110, and the protection layer 130 exposes the conductive structure 120 where the sidewall of the first opening 110 is connected to the surface of the substrate 100.
The protection layer 130 is used to protect the conductive structure 120 on the sidewall and bottom of the first opening 110 (shown in fig. 5) during the process of oxidizing the protrusion 121. Specifically, in this embodiment, the material of the protection layer 130 includes Graphene Oxide (Graphene Oxide).
The graphene oxide material is formed by introducing abundant oxygen-containing functional groups on the basis of the structure of graphene. Therefore, the graphene oxide contains hydroxyl and epoxy groups on the surface and has carboxyl on the edge. All the oxygen-containing functional groups are hydrophilic groups, so that the graphene oxide has good water solubility.
The step of forming the protective layer 130 includes:
as shown in fig. 6, a precursor is filled into the first opening 110, and the precursor includes graphene oxide.
In this embodiment, in order to achieve sufficient filling of the first opening 110 (shown in fig. 5) by the protection layer 130, the top surface of the precursor is higher than the surface of the substrate 100, that is, the precursor fills the first opening 110 (shown in fig. 5) and covers the surface of the substrate 100.
Since the graphene oxide has good water solubility, the precursor is in a fluid state, and the liquid level of the precursor is higher than the surface of the substrate 100. Since the precursor is a solution containing graphene oxide and is in a fluid state, the precursor has a good filling effect on the first opening 110 (as shown in fig. 5), and can effectively protect the side wall and the bottom conductive structure 120 of the first opening 110 (as shown in fig. 5).
After the precursor is filled, the precursor is subjected to a curing process to form a protective material layer 130 s.
In this embodiment, the precursor is cured by thermal curing. Specifically, in the step of performing the curing treatment by thermal curing, the temperature of the thermal curing is less than 280 ℃. In addition, since the liquid level of the precursor is higher than the surface level of the substrate 100, the formed protective material layer 130s fills the first opening and covers the surface of the substrate 100.
It should be noted that the curing process by thermal curing is only an example. In other embodiments of the present invention, the precursor may be cured by radiation curing. Specifically, in the process of curing by radiation curing, UV radiation may be used for curing.
Referring to fig. 7, after the protective material layer 130s is formed, a partial thickness of the protective material layer is removed to expose a portion of the conductive structure at the connection between the sidewall of the first opening 110 and the surface of the substrate 100, so as to form the protective layer 130.
Specifically, in this embodiment, oxygen plasma is used to remove a portion of the thickness of the protective material layer 130 s.
In the process of removing a portion of the thickness of the protective material layer 130s by using oxygen plasma, the oxygen plasma can remove a portion of the protective layer 130, expose a portion of the conductive structure 120 at the connection between the surface of the substrate 100 and the sidewall of the first opening 110 (as shown in fig. 5), and expose the protrusion 121 formed during deposition of the conductive structure 120.
With continued reference to fig. 7, a portion of the thickness of the conductive structure 120 is oxidized.
Since the plasma used in the process of removing a portion of the thickness of the protective material layer 130s is oxygen plasma, it has strong oxidizing property. Thus, during the removal of a portion of the thickness of the protective material layer 130s, the oxygen plasma also oxidizes a portion of the thickness of the conductive structure 120. That is, the exposed portion of the conductive structure 120 is oxidized to form a metal oxide. Therefore, the protrusion 121 located at the connection between the sidewall of the first opening 110 and the surface of the substrate 100 is also oxidized by the oxygen plasma to form an oxide.
It should be noted that if the thickness of the oxidized conductive structure 120 is too small, the protrusion 121 cannot be completely oxidized to form the metal oxide protrusion 121, which may affect the subsequent complete removal of the protrusion 121. Therefore, in the present embodiment, in the step of oxidizing and etching, the thickness of the oxidized conductive structure 120 is more than half of the thickness of the formed conductive structure 120, so as to ensure that the protrusion 121 can be completely removed subsequently. In addition, oxidation of more than half the thickness of the conductive structure 120 may be achieved by repeated oxide etches.
Referring to fig. 8 and 9 in combination, the protective layer 130 (shown in fig. 7) and the oxidized conductive structure 120 are removed, and a second opening 150 is formed.
Specifically, as shown in fig. 8, the protective layer 130 is first removed by water washing (as shown in fig. 7). In this embodiment, the material of the protection layer 130 includes graphene oxide. The graphene oxide has good water solubility. Therefore, the protective layer can be removed by water washing, so that the process difficulty of removing the protective layer 130 (as shown in fig. 7) is reduced, and the residue of the protective layer 130 is reduced.
Next, as shown in fig. 9, the oxidized portion of the thickness of the conductive structure 120 is removed by acid washing. In this embodiment, the conductive structure 120 is made of copper, and thus the material of the oxidized conductive structure 120 is copper oxide. The copper oxide can be removed by means of acid washing. Specifically, the oxidized portion of the thickness of the conductive structure 120 may be removed by a hydrochloric acid cleaning.
It should be noted that, in the present embodiment, at least half of the thickness of the conductive structure 120 is oxidized to form an oxide during the oxidation etching process. After the acid cleaning, the remaining conductive structure 120 has a thickness of at most half the thickness of the formed conductive structure 120.
Since the protrusions 121 are oxidized to oxide during the oxide etching, the protrusions 121 are also removed during the acid washing to remove the oxidized partial thickness of the conductive structure 120. The opening size of the second opening 150 is large compared to the related art.
In addition, because of the coverage of the protection layer 130, the portion of the conductive structure 120 covered by the protection layer 130 is not oxidized, and thus is not reacted with an acid solution during the acid washing process, and is not affected by the acid washing.
In this embodiment, in the step of removing the oxidized portion of the conductive structure by acid washing, nitrogen gas is added during the acid washing. The nitrogen is used for reacting with dissolved oxygen in the solution adopted by the acid cleaning, so that the dissolved oxygen is prevented from reacting with the residual conductive structure 120, the possibility that the residual conductive structure 120 is damaged by the acid cleaning is reduced, and the yield of the formed semiconductor device is improved.
Finally, referring to fig. 10, the second opening 150 is filled with a conductive material to form an interconnect structure 160.
The conductive material may be selected from one or more of tungsten, aluminum, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, or copper. Specifically, in this embodiment, the conductive material is copper. In this embodiment, the first opening 110 (shown in fig. 4) includes a trench 110tr and a contact hole 110 ct. The interconnect structure 160 thus includes interconnect lines 160tr and plugs 160 ct. Specifically, the interconnect structure 160 may be formed by filling a conductive material into the second opening by electroplating.
In this embodiment, the specific parameters of the electroplating process for forming the interconnect structure 160 are as follows: CuSO is selected as electroplating solution4Solution of Cu2+The concentration is 30g/L to 50 g/L. And adding various inorganic and organic additives into the solution, wherein the inorganic additive is chloride ion, and the concentration of the chloride ion is 40mg/L to 60 mg/L; the organic additive comprises an accelerator, a suppressor and a flatting agent, the concentrations of which are respectively 7mL/L to 10mL/L, 1mL/L to 3mL/L and 3mL/L to 6 mL/L; the current for plating was 4.5 to 45 amps. However, it should be noted that, in this embodiment, the specific parameters of the electroplating process are only an example.
Since the protrusion 121 is removed when the oxidized portion of the conductive structure 120 is removed, the upper end of the second opening 150 filled with the conductive material is wider, which is beneficial to improving the filling quality of the conductive material, reducing the possibility of forming a cavity in the filling process of the conductive material, effectively improving the quality of the formed interconnection structure 160, and improving the device manufacturing yield and the device reliability.
After forming the second opening, before filling the conductive material, the forming method further includes: the semiconductor structure is subjected to a reduction process to reduce the protective layer 120 remaining on the surface of the conductive structure 120. In this embodiment, the material of the protection layer 120 is graphene oxide, so that the semiconductor structure may be reduced by hydrogen or hydrazine to reduce the graphene oxide to graphene. The graphene material is a conductor, so the residue of the graphene material does not affect the conductivity of the formed conductive structure 160.
In summary, the protective layer is formed in the first opening, and the conductive structure at the connection between the sidewall of the first opening and the surface of the substrate is exposed from the protective layer; then oxidizing the conductive structure at the connection position of the side wall of the first opening and the surface of the substrate by oxidizing part of the conductive structure; and removing the oxidized conductive structure to remove the raised structure on the conductive structure. That is to say, in the technical scheme of the invention, the oxidized conductive structure is removed, and the protruding structure on the conductive structure and at the connection position of the side wall of the first opening and the surface of the substrate is removed, so that the size of the second opening can be increased, the formation of a cavity when the second opening is filled can be reduced, the filling effect of a conductive material can be effectively improved, the electrical connection performance of the formed interconnection structure is improved, and the reliability of the formed semiconductor structure is improved. Further, in the alternative of the present invention, the material of the protective layer is graphene oxide, and may be formed by curing a precursor containing graphene oxide. The precursor is in a fluid state, so that the protective layer can have a good filling effect on the first opening, and the protective effect of the protective layer on the first opening can be improved. And the graphene oxide has good water solubility, so that the protective layer can be removed through water washing, and the residue of the protective layer is reduced. In addition, the graphene oxide can be reduced into conductive graphene, so that the influence of the protective layer on the conductivity of the formed interconnection structure is reduced.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a first opening in the substrate;
forming a conductive structure on the sidewall of the first opening and the surface of the substrate;
forming a protective layer in the first opening, wherein the protective layer exposes the conductive structure at the connection position of the side wall of the first opening and the surface of the substrate;
oxidizing a portion of the thickness of the conductive structure;
removing the protective layer and the oxidized conductive structure to form a second opening;
filling a conductive material into the second opening to form an interconnection structure;
the material of the protective layer comprises graphene oxide.
2. The forming method of claim 1, wherein the step of forming the protective layer comprises:
filling a precursor into the first opening, wherein the precursor contains graphene oxide;
curing the precursor to form a protective material layer;
and removing part of the protective material layer to expose part of the conductive structure at the joint of the side wall of the first opening and the surface of the substrate to form a protective layer.
3. The forming method according to claim 2, wherein in the step of filling the precursor, the precursor in a fluid state is filled into the first opening.
4. The method of claim 2, wherein the step of subjecting the precursor to a curing process comprises: and carrying out curing treatment on the precursor by means of thermal curing or radiation curing.
5. The method of claim 4, wherein the step of subjecting the precursor to a curing process by thermal curing has a temperature of less than 280 ℃.
6. The forming method according to claim 4, wherein in the step of subjecting the precursor to a curing treatment by means of radiation curing, the precursor is subjected to a curing treatment with UV radiation.
7. The forming method according to claim 2, wherein in the step of removing the partial thickness of the protective material layer, the partial thickness of the protective material layer is removed using oxygen plasma;
and oxidizing the conductive structure with partial thickness in the process of removing the partial thickness of the protective material layer by adopting oxygen plasma.
8. The method of forming of claim 1, wherein the step of removing the protective layer comprises: and removing the protective layer by a water washing mode.
9. The method of forming as claimed in claim 1, wherein after forming the second opening and before filling the conductive material, further comprising: and carrying out reduction treatment on the semiconductor structure.
10. The method of claim 9, wherein the reducing step comprises reducing the semiconductor structure with hydrogen or hydrazine.
11. The method of forming as claimed in claim 1, wherein the step of removing the oxidized conductive structure comprises: and removing the oxidized part of the conductive structure by means of acid washing.
12. The method of claim 11, wherein removing the portion of the thickness of the conductive structure by acid washing comprises: and removing the oxidized part of the conductive structure by a hydrochloric acid cleaning mode.
13. The method of claim 11, wherein the step of removing the oxidized portion of the conductive structure by acid washing includes adding nitrogen gas during the acid washing.
14. The method of claim 1, wherein the step of forming the conductive structure comprises forming a seed layer, or wherein the conductive structure comprises a seed layer and a portion of the electroplated layer on a surface of the seed layer.
15. The method of claim 14, wherein the step of forming the conductive structure including the seed layer comprises forming the seed layer by physical vapor deposition.
16. The method of claim 1, wherein the step of filling the conductive material includes filling the conductive material by electroplating to form the interconnect structure.
17. The method of forming as claimed in claim 1, further comprising, after forming the first opening and before forming the protective layer: and forming an adhesion layer or a barrier layer on the side wall and the bottom of the first opening.
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| CN104616991A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method for fin type field effect transistor |
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| CN104103573A (en) * | 2013-04-02 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
| CN104112697A (en) * | 2013-04-18 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | Copper filling quality improving method |
| CN104124201A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Forming method of electric conduction structure |
| CN104616991A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method for fin type field effect transistor |
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